JPS5974786A - Phase matching device - Google Patents

Abstract

PURPOSE:To eliminate the need for a delay circuit and to attain high integration with reduction of number of component parts, by using an adder to perform processing so as to obtain coincidence of phase between a specific angle frequency signal separated with a separation route of the angle frequency signal and another specific angle freqency signal contained in a main signal. CONSTITUTION:A reproduced luminance signal, i.e., a wide band signal is supplied to an input terminal 21 and then to an input terminal of one side of an adder 22 as well as to an HPF24. The HPF24 consists of a capacitor C1 and a resistance R1, and the output of the HPF24 is supplied to a differential amplifier 25 via a coupling capacitor C2. The signals g1 and g2 delivered from the amplifier 25 are supplied to a limiter 26, and the output of the limiter 26 is applied to the other input terminal of the adder 22 via a phase inverter 23. Then the output of the adder 22 is led out to an output terminal 23.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a phase matching device that is effective as a noise canceler for a magnetic recording/reproducing device such as a video tape recorder.

[Technical background of the invention]

It is generally known that in magnetic recording and reproducing devices such as video tape recorders, noise is generated in the tape head system during recording and reproduction, and this noise is superimposed on the reproduced signal, resulting in a decrease in SA. Examples of noise include modulation noise, sliding noise, and head impedance noise. In order to reduce this kind of noise, conventional video tape recorders use a noise canceling circuit as shown in FIG. 1 for the reproduced signal.

In FIG. 1, the reproduced luminance signal is input to a bypass filter 12 and a delay circuit 15 via an input terminal 11. The reproduced signal containing noise is input to one terminal of an adder 16 through a delay circuit 15. A high frequency component is extracted from the luminance signal input to the high frequency filter 12,
This is further input to an amplifier 13 and a limiter circuit J4. A noise component is outputted from this limiter circuit 14, and after its phase is inverted by a phase inverter 18, the noise component is outputted from the adder 1.
6 is input to the other terminal. Therefore, the adder 16 outputs a reproduced signal from which noise has been removed, and is guided to the output terminal 17. Here, the delay circuit 15 is used to adjust the time with the noise separation path side. The noise separated by the noise separation path and the delay circuit 1
Phase matching with the noise that has passed through 5 is performed.

[Problems with background technology]

In the noise canceling device described above, the delay circuit 15 is usually constituted by a so-called CR circuit including a capacitor and a resistor.

A delay circuit having such a configuration as above involves an increase in the number of components, and still requires a built-in capacitor when integrated, resulting in an increase in chip area.

[Purpose of the invention]

This invention was made in view of the above circumstances, and does not require the above-mentioned delay circuit in the main signal route.
To provide a phase matching device suitable for miniaturization and integration into an integrated circuit (IC), which is designed so that the amount of phase shift between a high-speed filter on the extraction side of a specific signal such as noise and an amplifier has a canceling relationship. The purpose is to

[Summary of the invention]

For example, as schematically illustrated in the embodiment of FIG. 2, the present invention utilizes the phase lead of a specific angular frequency signal by the bypass filter 24 and the phase delay of the integrated differential amplifier 250 to achieve the above-mentioned purpose. It was designed to achieve the following.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. Second
In the figure, a reproduced luminance signal of a broadband signal is inputted to input terminal 2, and this signal is inputted to one input terminal of adder 22 and high delta filter 24.

,, the pass filter 24 includes a capacitor CI and a resistor R1.
The output of this high-nos filter 24 is connected to a differential amplifier 25 via a coupling capacitor C2.
is input. The differential amplifier 25 includes transistors Q1 to
Q4, resistors R2 to R7, and current sources IO, I, ,I.

Then, the output g'+ outputted from this differential amplifier 25
g2 is input to the limiter 26.

The output of the limiter 26 is then applied to the other input terminal of the adder 22 via a phase inverter 27. The output of adder 22 is delivered to output terminal 23.

One embodiment of the present invention is constructed as described above, and there is no need to provide a delay circuit on the main signal line (between the input terminal 21 and one input terminal of the adder 22) as in the conventional case.

■ First, is the total amount of phase shift between the input and output terminals of the Hi-No Yass filter 24 1'? : I'll try it. Here C7<<C2, R7
When determining the transfer function H(ω) as <<R6, ■(ω)-a1/(R1+1/iωc)) ・(1)
− becomes. Then, the phase difference θ between input and output is θ1 =
argH (ccr) = tam-'('9 RICI
)...(2).

(2) Next, consider the amount of phase shift of the differential amplifier 25. In an integrated circuit, a capacitance of Ccb is parasitic between the collector and base of a transistor, and a capacitance of Ce8 is parasitic between the collector and the differential. (Figure 3 shows transistor Q
This is an example of 2. ) Next, the pace of the transistor Q2 is a low impedance drive section by the emitter follower connection of the transistor Q2, so it has a very low impedance in terms of alternating current. Therefore, an integrating circuit consisting of R2, Cab and ces (or Ft3°Ccb, Ceg) is formed at the output end of the differential amplifier 25.

Here, assuming that the input impedance of the limiter 26 is sufficiently large, and finding the transfer function G(ω) of the integrator attached to the collector in FIG. 3, G(1-1)=R2/(1/F
L2+ jω(Ceb + cclll)) (3) Here, Ccbr CcB is determined by the transistor.

Next, when determining the phase difference θ2 by this integrator, θ2=a
rg G(ω) =tan-' (ωa+ (Cab+
Ca5) ) ・(4).

Here, the bypass filter 24 provides a phase lead, and the differential amplifier 25 provides a phase delay. Therefore, if θ1+0220, there is no phase shift. Therefore, if the value of equation (2) is made equal to the value of equation (4), '/ma1cJ=ωR2(Cab +Cam) −(5
) However, the purpose can be achieved if each constant has the relationship shown in equation (5), such as R2=R,1. If the characteristics required for the high-noise filter 24 (due to the capacitor C11 and the resistor R1) are given, then from the relationship in equation (5), the resistance R? of the differential amplifier 25? ,
The value of R,9 can be determined. At this time, if the noise component is considered as a continuous spectrum of a sine wave, the angular frequency ω may be matched to the frequency of the noise that is most desired to be removed. Furthermore, the gain and operating point of the differential amplifier 25 are determined by the resistors R4 and R
5 and current source I. It can be set arbitrarily by FIGS. 5 to 7 show other embodiments of the present invention. The previous formula (5
), when determining the value of resistor R2゜R3, the value becomes too large, causing unreasonableness in IC design (there is a limit to the value of the resistor provided in the IC). It is. That is, as shown in FIG.
2, R, and 9 in parallel, or as shown in FIG. 5, transistors Q2. A capacitor C5 is connected between the collectors of transistors Q3, and transistors Q2. By connecting capacitors C6 and C7 between each collector of Q3 and the reference ground potential, resistors R, ? , R,9 can be designed to be small.

However, even in this case, since Ccb and Ccs are used, the values of the capacitors C3 to C5 are small, and the increase in the selection area is also small.

The other parts are the same as the circuit shown in FIG. 2, so the same reference numerals are given and the explanation will be omitted.

The above description has been made as a noise canceler for reproduced luminance signals in a video tail recorder. However, the present invention is capable of canceling noise at specific angular frequencies separated by a specific angular frequency signal separation path without using a delay circuit in the main signal path. The phase of the signal and the specific angular frequency signal in the main signal is determined by the adder 22.
The main part is processing so that they match.

Therefore, it can be used not only for noise cancellation, but also for canceling other specific signals, or for enhancing specific signals without using the inverter 27.

〔Effect of the invention〕

As described above, the present invention eliminates the need to provide a delay circuit in the main signal route, and provides integration (Is).

In order to reduce the number of components and when separating a specific angular frequency signal in the main signal, the phase of the separated specific angular frequency signal and the specific angular frequency signal of the main signal route is adjusted. A phasing device that can be used can be provided.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram showing a conventional noise canceling circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is an equivalent circuit shown to explain the operation of the circuit in Fig. 2. figure,
FIG. 4, FIG. 5, and FIG. 6 are circuit diagrams showing other embodiments of the present invention. 21...input terminal, 22...adder, 24...)
・Innoya Sfilter, 25...Differential amplifier, 26...
・Limiter, Q1-Q4...transistor. Applicant's agent Patent attorney Takehiko Suzue
jFigure 6

Claims (1)

[Claims] An adder or a subtracter to which a wideband signal is applied to one input terminal via an input terminal; a bypass filter to which the broadband signal is input via the input terminal; and an output of the bypass filter. is input, and the phase shift amount of a signal of a specific angular frequency is set to be delayed by the lead phase sum of the high-pass filter; means for applying the separated signal of the specific angular frequency to the other input terminal of the adder or subtracter, 1. A phase matching device, characterized in that the phase of a frequency signal and a specific angular frequency signal separated in the path of the amplifier match in the adder or subtracter.