JPS597224B2 - flip chip attachment - Google Patents

flip chip attachment

Info

Publication number
JPS597224B2
JPS597224B2 JP53050348A JP5034878A JPS597224B2 JP S597224 B2 JPS597224 B2 JP S597224B2 JP 53050348 A JP53050348 A JP 53050348A JP 5034878 A JP5034878 A JP 5034878A JP S597224 B2 JPS597224 B2 JP S597224B2
Authority
JP
Japan
Prior art keywords
flip
bonding pad
source
chip
grounding metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53050348A
Other languages
Japanese (ja)
Other versions
JPS54141563A (en
Inventor
正昭 中谷
康郎 三井
学 渡瀬
通博 小引
三郎 高宮
茂 三井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP53050348A priority Critical patent/JPS597224B2/en
Publication of JPS54141563A publication Critical patent/JPS54141563A/en
Publication of JPS597224B2 publication Critical patent/JPS597224B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 この発明はフリップチップ構成の半導体チップが装着さ
れるパッケージなどのフリップチップ装着体の改良に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in flip-chip mounting bodies such as packages to which flip-chip semiconductor chips are mounted.

以下、ソース接地のヒ化ガリウム電界効果トランジスタ
(以下「GaAsFET」と呼ぶ)のフリップチップが
装着されるフリップチップ装着体を例にとり、その従来
例を第1図に示す斜視図および第2図に示す第1図の■
−■線での縦断面図で説明する。
Hereinafter, we will take as an example a flip-chip mounting body to which a source-grounded gallium arsenide field effect transistor (hereinafter referred to as "GaAsFET") flip chip is mounted. ■ In Figure 1 shown
This will be explained using a vertical cross-sectional view taken along the line -■.

図において、1はソース接地のGaAsFETのフリッ
プチップ、2、3および4はそれぞれGaAsFETの
フリップチップ1の表面に互いに所定間隔をおいて平行
に設けられ長方形の表面形状を有するソース突起電極、
ドレイン突起電極、およびゲート突起電極である。
In the figure, 1 is a source-grounded GaAsFET flip chip, 2, 3, and 4 are source protrusion electrodes each provided parallel to the surface of the GaAsFET flip chip 1 at a predetermined interval and having a rectangular surface shape;
They are a drain protrusion electrode and a gate protrusion electrode.

5はGaAsFETのフリップチップ1が装着されるフ
リップチップ装着体、6はフリップチップ装着体5の接
地用金属基板、□は接地用金属基板6の表面に取り付け
られたベリリアなどからなるセラミック基板、8、9お
よび10はそれぞれセラミック基板7の表面のソース突
起電極2、ドレイン突起電極3、およびゲ一ト突起電極
4に対応する部位に形成され、これらの突起電極2、3
、および4が同時にボンディング接続される薄膜もしく
は厚膜などの長方形の金属膜からなるソースボンディン
グパッド、ドレインボンディングパッド、およびゲート
ボンディングパッドである。
Reference numeral 5 denotes a flip chip mounting body to which the GaAsFET flip chip 1 is mounted, 6 a grounding metal substrate of the flip chip mounting body 5, □ a ceramic substrate made of beryllia or the like attached to the surface of the grounding metal substrate 6, 8 , 9 and 10 are formed on the surface of the ceramic substrate 7 at positions corresponding to the source protrusion electrode 2, the drain protrusion electrode 3, and the gate protrusion electrode 4, respectively.
, and 4 are a source bonding pad, a drain bonding pad, and a gate bonding pad made of a rectangular metal film such as a thin film or a thick film, which are simultaneously bonded.

なお、ソースボンデイングパツド8の両端部がそれぞれ
厚さの薄い金属膜によつてセラミツク基板7の両端面を
経て接地用金属基板6の両端面に接続されている。とこ
ろが、特に高出力高周波用のフリツプチツプ1では、ソ
ース突起電極2をその長手方向に長くした細長い四角形
にする必要があるので、ソースボンデイングパツド8も
細長い四角形になる。
Note that both ends of the source bonding pad 8 are connected to both end faces of the grounding metal substrate 6 via both end faces of the ceramic substrate 7 by thin metal films. However, especially in the flip chip 1 for high power and high frequency applications, the source projecting electrode 2 needs to be elongated in the longitudinal direction, so that the source bonding pad 8 is also elongated in the form of a rectangle.

このために、ソ.−ス突起電極2から接地用金属基板6
までの電気長が長くなり、ソース寄生インダクタンスL
sが大きくなるので、その最大有能電力利得が低下する
という欠点があつた。また、第3図に斜視図に示すよう
に、複数個のフリツプチツプ1を並列にフリツプチツプ
装着体5に装着して高出力を得る場合でも、各フリツプ
チツプ1のソース突起電極2から接地用金属基板6まで
の電気長が、均一ではなく、各フリツプチツプ1毎に異
なつているので、各フリツプチツプ1の相互間の人出力
インピーダンスがばらつくために、せれぞれの出力を効
率よく合成することができないという欠点もあつた。こ
の発明は、上述の欠点に鑑みてなされたもので、フリツ
プチツプ構成の半導体チツプの接地すべき細長い突起電
極がボンデイング接続されるボンデイングパツドの長手
方向の一方の端縁にこの端縁を全域において接地する接
地用金属膜を設けることによつて、上記半導体チツプの
マイクロ波周波数領域における特性の向上を図り得るフ
リツプチツプ装着体を提供することを目的とする。
For this reason, So. - from the base protruding electrode 2 to the grounding metal substrate 6
The electrical length up to L becomes longer, and the source parasitic inductance L
As s increases, the maximum available power gain decreases. Furthermore, as shown in the perspective view of FIG. 3, even when a plurality of flip chips 1 are mounted in parallel on the flip chip mounting body 5 to obtain high output, the source protrusion electrode 2 of each flip chip 1 is connected to the grounding metal substrate 5. Since the electrical length between the flip chips 1 and 1 is not uniform and differs for each flip chip 1, the output impedance between the flip chips 1 varies, making it impossible to efficiently combine the respective outputs. It was hot too. The present invention has been made in view of the above-mentioned drawbacks, and includes a semiconductor chip having a flip-chip structure. It is an object of the present invention to provide a flip chip mounting body that can improve the characteristics of the semiconductor chip in the microwave frequency region by providing a grounding metal film that is grounded.

第4図はソース接地のGaAsFETのフリツプチツプ
が装着されたこの発明のフリツプチツプ装着体の一実施
例を示す断面図である。図において、7aは長方形の表
面形状を有するソース突起電極2がボンデイング接続さ
れる長方形の金属膜からなるソースボンデイングパツド
8とゲート突起電極4がボンデイング接続される金属膜
からなるゲートボンデイングパツド10とがそれぞれ表
面に設けられソースボンデイングパツド8の長手方向の
端部に平行な側面を有する第1のセラミツク基板、7b
はドレイン突起電極3がボンデイング接続される金属膜
からなるドレインボンデイングパツド10が表面に設け
られ第1のセラミツク基板7aと同一の厚さを有する第
2のセラミツク基板、11は第1のセラミツク基板7a
の長手方向の側面に設けられこの側面に沿うソースボン
デイングパツド8の膜端と接地用金属基板6とを接続す
るソース接地用金属膜である。
FIG. 4 is a sectional view showing an embodiment of the flip-chip mounting body of the present invention in which a source-grounded GaAsFET flip-chip is mounted. In the figure, 7a denotes a source bonding pad 8 made of a rectangular metal film to which the source protrusion electrode 2 having a rectangular surface shape is bonded and a gate bonding pad 10 made of a metal film to which the gate protrusion electrode 4 is bonded. a first ceramic substrate 7b having side surfaces parallel to the longitudinal ends of the source bonding pads 8;
11 is a second ceramic substrate having the same thickness as the first ceramic substrate 7a and has a drain bonding pad 10 made of a metal film on its surface to which the drain projection electrode 3 is bonded; and 11 is a first ceramic substrate. 7a
This is a source grounding metal film that is provided on the side surface in the longitudinal direction and connects the film end of the source bonding pad 8 along this side surface and the grounding metal substrate 6.

なお、ソース接地用金属膜11と第2のセラミツク基板
7bの側面とが互いに接するようにするとともに、ソー
スボンデイングパツド8、ドレインボンデイングパツド
9、およびゲートボンデイングパツド10のそれぞれの
表面がほぼ同一平面になるように、第1、第2のセラミ
ツク基板7a,7bが接地用金属基板6の表面に取り付
けられている。このように構成されたこの実施例のフリ
ツプチツプ装着体5では、ソースボンデイングパツド8
の長手方向の膜端がソース接地用金属膜11によつて接
地用金属基板6に接続されているために、高出力高周波
用のフリツプチツプのような長手方向の長さの長いソー
ス突起電極でも、これと接地用金属基板8との間の電気
長を大幅に短かくすることができるので、上記フリツプ
チツプのソース寄生インダクタンスLsを大幅に低減す
ることができる。
Note that the source grounding metal film 11 and the side surface of the second ceramic substrate 7b are in contact with each other, and the surfaces of each of the source bonding pad 8, drain bonding pad 9, and gate bonding pad 10 are approximately First and second ceramic substrates 7a and 7b are attached to the surface of the grounding metal substrate 6 so as to be on the same plane. In the flip chip mounting body 5 of this embodiment configured in this way, the source bonding pad 8
Since the film end in the longitudinal direction is connected to the grounding metal substrate 6 by the source grounding metal film 11, even a source projecting electrode with a long longitudinal length such as a flip chip for high power and high frequency can be used. Since the electrical length between this and the grounding metal substrate 8 can be significantly shortened, the source parasitic inductance Ls of the flip chip can be significantly reduced.

発明者らの行なつた実1験結果によれば、マイクロ波周
波数領域において、上記フリツプチツプのソース寄生イ
ンダクタンスLsを、第1図に示した従来例のそれに比
べ、1nH程度以上小さくすることが可能となり、その
最大有能電力利得を2dB程度以上改善することができ
た。また、第3図に示したように、複数個のフリツプチ
ツプのソース突起電極をその長手方向に並列にボンデイ
ング接続する細長い長方形のソースボンデイングパツド
でも、その長手方向の膜端が長さの短いソース接地用金
属膜によつて接地されているので、上記各フリツプチツ
プのソース寄生インダクタンスLsが均一でかつ極めて
小さいために、上記各フリツプチツプの相互間に入出力
インピーダンスのばらつきがなく、それぞれの出力を効
率よく合成することができる。更に、ソース接地用金属
膜の厚さが非常に薄く、これを実質的に無視することが
できるので、上記フリツプチツプの形状寸法を、従来例
のフリツプチツプの形状寸法と同程度にすることができ
る。上記実施例では、ソース接地用金属膜を第1のセラ
ミツク基板の側面にのみ設けたが、これを第1のセラミ
ツク基板の側面とこれに接する第2のセラミツク基板の
側面との両方に設けるようにしてもよい。
According to the results of experiments conducted by the inventors, it is possible to reduce the source parasitic inductance Ls of the flip chip in the microwave frequency region by about 1 nH or more compared to that of the conventional example shown in FIG. Therefore, the maximum available power gain could be improved by about 2 dB or more. In addition, as shown in FIG. 3, even in the case of a long rectangular source bonding pad in which the source protruding electrodes of a plurality of flip chips are bonded in parallel in the longitudinal direction, the film end in the longitudinal direction is connected to a short source. Since the flip chips are grounded by the grounding metal film, the source parasitic inductance Ls of each flip chip is uniform and extremely small, so there is no variation in input/output impedance between the flip chips, and each output can be efficiently output. Can be easily synthesized. Furthermore, since the thickness of the source grounding metal film is so thin that it can be virtually ignored, the dimensions of the flip chip can be made comparable to those of conventional flip chips. In the above embodiment, the source grounding metal film was provided only on the side surface of the first ceramic substrate, but it may be provided on both the side surface of the first ceramic substrate and the side surface of the second ceramic substrate in contact with it. You can also do this.

また、上記実施例では、ソース接地の場合について述べ
たが、この他のドレイン接地もしくはゲート接地の場合
についても適用することができる。
Further, in the above embodiments, the case where the source is grounded is described, but it is also possible to apply to other cases where the drain is grounded or the gate is grounded.

なお、GaAsFETのフリツプチツプを装着するフリ
ツプチツプ装着体について説明したが、この発明はこれ
に限らず、この他のマイクロ波電力用FET,MOSト
ランジスタ、薄膜トランジスタなどのフリツプチツプ構
成の半導体チツプを装着するフリツプチツプ装着体にも
適用することができる。以上、詳細に説明したように、
この発明によれば、フリツプチツプ構成の半導体チツプ
の接地すべき細長い突起電極がボンデイング接続される
ボンデイングパツドの長手方向の一方の端縁にこの端縁
を全域において接地する接地用金属膜を設けたので、上
記ボンデイングパツドがその長手方向の長さの長い形状
であるときでも、これを接地する電気長を大幅に短かく
することができる。
Although the flip-chip mounting body for mounting a GaAsFET flip chip has been described, the present invention is not limited to this, and the present invention is applicable to a flip-chip mounting body for mounting semiconductor chips having a flip-chip structure such as microwave power FETs, MOS transistors, and thin film transistors. It can also be applied to As explained in detail above,
According to the present invention, a grounding metal film is provided on one longitudinal edge of a bonding pad to which an elongated protruding electrode to be grounded of a semiconductor chip having a flip-chip structure is connected by bonding. Therefore, even when the bonding pad has a long longitudinal length, the electrical length for grounding it can be significantly shortened.

このために、上記ボンデイングパツドにボンデイング接
続される上記半導体チツプの上記突起電極の寄生インダ
クタンスLsを大幅に低減することができる。よつて、
上記半導体チツプのマイクロ波周波数領域における特性
の向上を図り得るフリツプチツプ装着体を提供すること
ができる。
Therefore, the parasitic inductance Ls of the protruding electrode of the semiconductor chip bonded to the bonding pad can be significantly reduced. Then,
It is possible to provide a flip chip mounting body that can improve the characteristics of the semiconductor chip in the microwave frequency region.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はソース接地のGaAsFETのフリツプチツプ
が装着された従来のフリツプチツプ装着体を示す斜視図
、第2図は第1図の−線での縦断面図、第3図は複数個
のソース接地のGaAsFETのフリツプチツプが装着
された従来のフリツプチツプ装着体を示す斜視図、第4
図はソース接地のGaAsFETのフリツプチツプが装
着されたこの発明のフリツプチツプ装着体の一実施例を
示す断面図である。 図において、1はGaAsFETのフリツプチツプ(フ
リツプチツプ構成の半導体チツプ)、2はソース突起電
極(第1の突起電極)、3はドレイン突起電極(第3の
突起電極)、,4はゲート,突起電極(第2の突起電極
)、6は接地用金属基板、7aおよび7bは第1および
第2のセラミツク基板、8はソースボンデイングパツド
(第1のボンデイングパツド)、9はドレインボンデイ
ングパツド(第3のボンデイングパツド)、10はゲー
トボンデイングパツド(第2のボンデイングパツド)、
11は接地用金属膜である。
FIG. 1 is a perspective view showing a conventional flip-chip mounting body in which a source-grounded GaAsFET flip-chip is mounted, FIG. 2 is a longitudinal cross-sectional view taken along the - line in FIG. 1, and FIG. FIG. 4 is a perspective view showing a conventional flip-chip mounting body equipped with a GaAsFET flip-chip;
The figure is a sectional view showing an embodiment of the flip-chip mounting body of the present invention, in which a source-grounded GaAsFET flip-chip is mounted. In the figure, 1 is a GaAsFET flip chip (semiconductor chip with flip-chip configuration), 2 is a source protrusion electrode (first protrusion electrode), 3 is a drain protrusion electrode (third protrusion electrode), 4 is a gate, protrusion electrode ( 6 is a grounding metal substrate, 7a and 7b are first and second ceramic substrates, 8 is a source bonding pad (first bonding pad), and 9 is a drain bonding pad (first bonding pad). 3 bonding pad), 10 gate bonding pad (second bonding pad),
11 is a metal film for grounding.

Claims (1)

【特許請求の範囲】[Claims] 1 接地すべき細長い第1の突起電極とこの第1の突起
電極をはさんで接地しない第2および第3の突起電極と
を有するフリップチップ構成の半導体チップの上記第1
および第2の突起電極がそれぞれボンディング接続され
る金属膜からなる第1および第2のボンディングパッド
が表面に設けられ上記第1のボンディングパッドの長手
方向に沿う端縁に平行な側面を有する第1のセラミック
基板と、上記第3の突起電極がボンディング接続される
金属膜からなる第3のボンディングパッドが表面に設け
られた第2のセラミック基板とが接地用金属基板上に取
り付けられ、上記第1のセラミック基板の上記側面に上
記第1のボンディングパッドをその長手方向の全域にお
いて上記接地用金属基板に接続する接地用金属膜を備え
たフリップチップ装着体。
1. The above-mentioned first semiconductor chip having a flip-chip structure having a first elongated protruding electrode to be grounded and second and third protruding electrodes sandwiching the first protruding electrode and not being grounded.
and a first bonding pad made of a metal film to which a second projecting electrode is bonded and connected, respectively, are provided on the surface thereof, and the first bonding pad has a side surface parallel to an edge along the longitudinal direction of the first bonding pad. and a second ceramic substrate provided with a third bonding pad made of a metal film on the surface to which the third projecting electrode is bonded are attached to the grounding metal substrate, and the second ceramic substrate is attached to the grounding metal substrate. A flip-chip mounting body comprising a grounding metal film on the side surface of the ceramic substrate that connects the first bonding pad to the grounding metal substrate over the entire length of the first bonding pad in the longitudinal direction.
JP53050348A 1978-04-26 1978-04-26 flip chip attachment Expired JPS597224B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53050348A JPS597224B2 (en) 1978-04-26 1978-04-26 flip chip attachment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53050348A JPS597224B2 (en) 1978-04-26 1978-04-26 flip chip attachment

Publications (2)

Publication Number Publication Date
JPS54141563A JPS54141563A (en) 1979-11-02
JPS597224B2 true JPS597224B2 (en) 1984-02-17

Family

ID=12856399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53050348A Expired JPS597224B2 (en) 1978-04-26 1978-04-26 flip chip attachment

Country Status (1)

Country Link
JP (1) JPS597224B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0583746B2 (en) * 1983-10-19 1993-11-29 Yamaha Motor Co Ltd

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6166436A (en) * 1997-04-16 2000-12-26 Matsushita Electric Industrial Co., Ltd. High frequency semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0583746B2 (en) * 1983-10-19 1993-11-29 Yamaha Motor Co Ltd

Also Published As

Publication number Publication date
JPS54141563A (en) 1979-11-02

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