JPS5972207A - Muting circuit - Google Patents

Abstract

PURPOSE:To prevent a pop sound noise due to a shift in operation point during on/off switching by placing an output terminal in a floating state during muting operation. CONSTITUTION:The 1st and the 2nd constant current sources consisting of transistors (TR) Q11 and Q12, and Q14 and Q15 are connected to the base and emitter of a PNP TRQ10 whose base is an input terminal. Then, a PNPTRQ18 whose base is connected between the base of the TRQ10 and the 1st constant current source, and an NPNTRQ17 whose base is connected between the emitter of the TRQ10 and the 2nd constant current source are connected mutually at the emitters to an output stage. Then, a mute signal current is inputted to a TRQ16 during muting operation to turn off the 1st and the 2nd constant current sources. At this time, the TRs Q17 and Q18 turn off and the output terminal enters the floating state.

Description

TECHNICAL FIELD The present invention relates to a bipolar analog circuit suitable for integrated circuits, and more particularly to a mute circuit suitable for audio power amplifier circuits.

An example of a prior art mute circuit is as shown in FIG.
There is a configuration in which the collector of an NPN transistor Q1 whose emitter is grounded is connected to the input stage of the amplifier 1, and a mute signal is input to the base of the transistor Q1. However, in this mute circuit, since the on-resistance of the mute transistor Q1 is not sufficiently low, there is a problem that the mute output is large.

In addition, as another example of a mute circuit, as shown in FIG. 2, an NPN (NPN) transistor Q2 is inserted as a gate in the output stage of the amplifier 1, and an inverted mute signal is input to the base of the transistor Q2. There is something configured like this. However, in this mute circuit, if the amplifier 1 is a power amplifier, the mute transistor Q2 needs to be a large transistor equal to or larger than the output transistor of the amplifier l.
It becomes an obstacle to integrated circuits.

3rd r1! , l is an example of a buffer circuit used when the amplifier does not have a drive ability, and connects the base terminal of the PNP transistor Q3 whose collector is grounded to the input terminal (7, N which constitutes a complementary circuit).
The output terminal is the emitter interconnection point of the PN) transistor Q4 and the PNP transistor Q5. A bias is applied to the base of the input transistor Q3 by a resistor R1.

By the way, if such a buffer circuit is provided with a mute circuit as shown in Figure 1, the operating point will shift when the input signal is removed during muting, and the next time the mute is released, a pop sound will be heard. A problem arises in which noise is generated.

OBJECTS OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a mute circuit that does not generate popping noises due to movement of the operating point when switching the mute operation on and off.

composition Examples of the present invention will be described below.

FIG. 4 shows a mute circuit of one embodiment, Q□.

is a PN whose collector is grounded as an input stage transistor.
P) A transistor, to the base of which the input signal Vin is applied. Input stage transistor Q□. The base of is grounded through the diode DI, the NPN transistor Q□□, and the resistor R2, but this transistor Q1□ forms a current mirror circuit together with the diode-connected transistor Q□2 whose base and collector are short-circuited. This is a constant current source. The emitter of the input stage transistor QIO is connected to the power supply Vcc via a PNP transistor Q14, and this transistor Q14 is a constant current source forming a current mirror circuit together with a PNP transistor Q15 whose base collector is short-circuited and connected as a diode. It is.

A current mirror circuit consisting of transistors Q0□, Q02 and Q□3, and a current mirror circuit consisting of transistors Q and Q15, are transistors Q□3 and 9.
□It is connected by connecting the collectors of 5 to each other.

The current values of these constant current sources Q□□, Q□4 are determined by the resistance R2
, a diode-connected transistor Q12, and a resistor inserted between the transistor Q12 and the power supply Vcc.

Q16 is an NPN transistor whose emitter is grounded as a mute signal input transistor, and its collector is connected to the connection point between resistor R3 and transistor Q□2.
The mute signal is applied to the base of this transistor Q16.

The output stage of this mute circuit is a complementary circuit in which an NPN transistor Q17 whose collector is connected to the power supply Vcc and a PNP transistor Q□8 whose collector is grounded are interconnected at their emitters, and the base of the transistor Q17 is The emitter of the input stage transistor QIO is connected to the connection point between the constant current source transistor Q, and the base of the transistor Q184 is connected to the connection point between the cathode of the diode D□ and the constant current source transistor Qll, and the transistors Q□7 and Q18 An output signal is taken from the emitter interconnection point of. RL is a load resistance.

Now, in the case of normal operation in which the mute signal current does not flow into the base of the transistor Q1゜, the transistor Q□6 is off, so the bias current ■0 is set by the resistor R3 and the transistor Q12, and this bias current resistance is 0.
Looking at the base current of each transistor, the transistors Q□3, Q□5 and Q□ are connected by the current mirror circuit.
It flows equally to 4.

A bias current I□ defined by (k is the Boltzmann constant, T is the absolute temperature, and 9 is the free weight #) flows through the transistor Qll.

The value of this bias current 11 is changed to 10 by resistor R2.
) If the IA is made smaller, DC coupling is possible regardless of the drive capacity of the output stage transistor such as an amplifier connected to the base of the input stage transistor Q1o, and each bias current value and the output stage transistor Q□7. A buffer circuit with a drive capability determined by the size of Q□8 is constructed.

In addition, in this embodiment, the output stage transistors Q□7 and Q□
The heavy voltage operating point of the output terminal, which is the emitter connection point of 8, is equal to the operating point of the amplifier DC-coupled to the base of the input stage transistor QIO.

Next, during muting, nine streams of mute signals flow into the base of transistor 916 and transistor Q16 is saturated, so the base potentials of transistors Q□3 and Q□□ fall, and transistors Q13 and Q1□ are turned off. Furthermore, since the collector of the transistor Q□3 is connected to the bases of the transistors Q15 and Q14, the transistors Q□5 and Q□4 are turned off because their bases become open. As a result of the constant rM a source transistors Q□4 and Q1□ being turned off in this way, the output stage transistor Q□ connected to their respective collectors
The bases of transistors Q7 and Q□8 are also in an open state, and both transistors Q□7 and Q□8 are also turned off. the result,
Since there is no discharge path other than the output leak laminar flow, the DC heavy pressure operating point before muting is maintained.

Many of the operational amplifiers commonly used in linear circuits have a push-pull configuration in their output stage, and do not have drive capability. The embodiment of the present invention shown in FIG. 1 acts not only as a mute circuit but also as a buffer circuit with drive capability, and therefore can be used in conjunction with the output stage of an operational amplifier. Further, since this embodiment can be DC-coupled with an operational amplifier, it is possible to integrate the circuit with the operational amplifier on one chip.

FIG. 5 shows a mute circuit according to a second embodiment of the present invention.
The state shown is that it is connected to the output stage of an amplifier. PNP
The composite transistor consisting of the transistor Q20 and the NPN (NPN) transistor 21 is an input stage transistor corresponding to the transistor Ql d in FIG. applied. The base of the transistor Q20 is grounded via the diode D1 and the NPN transistor Qll, and this transistor Q□□ is a constant current source that forms a constant current circuit together with the diode D2. The emitter of the input stage transistor Q20 and the collector of the transistor Q21 are connected to the power supply Vcc via a diode D3 and a PNP transistor Q□4, but this transistor Q14 is connected to a diode-connected PNP transistor Q as in FIG. It is a constant current source that forms a current mirror circuit together with □5.

In addition, the emitter of the N P N ) transistor Q22 is grounded via the resistor R4, forming a constant current circuit together with the diodes D4 and D2, and the collector is connected to the collector and base of the transistor Q15.
A current mirror circuit consisting of transistors Q15 and 9□4 is connected to a constant current circuit consisting of a diode D and a transistor Q□1.

The collector of the mute (f-number input transistor Q□6) is connected to the anode of the diode D4.

In the output stage of this mute circuit, a composite transistor capacitor consisting of two NPN transistors Q and Q24 corresponds to transistor Q□7 in FIG. 1, and the base of transistor Q23 is connected to the anode of diode D3 and constant current source transistor □ Connected to the connection point with 4, PNP
) A composite transistor consisting of transistor Q2□ and NPN) transistor Q28 corresponds to transistor Q□8 in FIG. 1, and the base of transistor Q2□ is connected to diode D1.
It is connected to the connection point between the cathode of Q and the constant current source transistor Q□.

Q25 and Q26 are output protection transistors. The output is taken from the emitters of transistors Q24 and 92□ at an interconnection point via a resistor.

The operation of this embodiment is similar to that of the embodiment shown in FIG. 1, and during normal operation when the mute signal current does not flow into the transistor Q element 6, it acts as a buffer circuit with drive capability, and during mute operation, it acts as a buffer circuit with drive capability. , as in Fig. 1, the constant current source transistors Q□4 and Q are turned off, and the transistors in the output stage are also turned off and the output terminal is in a floating state. The fin pressure operating point is maintained.

It should be noted that although the above printed examples are all operated between the power supply Vcc and the ground, it goes without saying that the present invention can be operated in exactly the same way between a high voltage power supply and a low voltage power source.

Effects As described above, the mute circuit of the present invention is configured so that the output terminal is in a floating state during the mute operation, so there is no shift in the operating point between the normal operation and the mute operation 1, so Since no sound noise is generated, it can be combined with a general-purpose amplifier to form an audio amplifier.

Furthermore, since the circuit does not operate during muting, it has the advantage that there is extremely little mute leakage output compared to conventional muting circuits that mute signal systems.

[Brief explanation of drawings]

FIGS. 1 and 2 are circuit diagrams showing conventional mute circuits,
FIG. 3 is a circuit diagram showing a conventional buffer circuit, and FIGS. 4 and 5 are circuit diagrams showing embodiments of the present invention, respectively. Qlo, Q10...Input stage PNP) transistor, Q
□7. Q□8 ``23'' Q24 ``27'' 2
8... Output stage transistor, Qll, Q14... Categorical current source transistor. Patent applicant Ricoh Co., Ltd.

Claims (1)

[Claims] (1) PNP with the base as the input terminal) The load on the base side of the transistor is equipped with a first constant current source, the emitter measurement load is equipped with a second constant current source, and the output stage is equipped with the base side and a PNP transistor whose base is connected between the emitter and the first constant current source, and an NPN transistor whose base is connected between the emitter and the second constant current source, and a mute signal A mute circuit characterized in that an output terminal is in a floating state when the first and second constant current sources are turned off.