JPS597160B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to digital storage devices for electronic computers, electronic exchanges, and the like.

In particular, the present invention relates to a storage device equipped with a circuit that can detect or correct errors in information using redundant bits added to signals. Various methods are known for detecting or correcting errors by adding redundant bits to information bit signals. Among these, the method of adding redundant bits to each word of information bits is widely used,
When the number of bits in one word is small, redundant bits account for a large proportion of the total signal bits, which has the disadvantage that storage, transmission, or processing equipment becomes larger and more expensive. Generally, the conditions for adding m bits of redundant bits to m big+ information, detecting 2 bit errors, and correcting 1 bit error are 2n≧m+n+l...
...(1).

In this case, when m is small, the ratio of n becomes large and the device becomes expensive. Since the number of bits in one word is limited by conditions other than device design conditions, the proportion of redundant bits can be reduced by adding redundant bits to information bits of two or more words at once. .

In other words, the condition for adding l redundant bits to information compiled into m-bit words and detecting 2-bit errors or correcting 1-bit errors is 21≧reason. × +l+1 ・・・・・・・・・(2
) is satisfied.

On the other hand, as the number of information bits accessed simultaneously from a storage circuit increases, the device generally becomes more complex and expensive.

However, in recent years, the processing speed of digital signals has increased significantly due to the development of integrated circuits, so even if the number of information bits to be accessed at the same time is one word at a time, the number of information bits can be selected and processed sequentially in a sufficiently short period of time. It became possible to do it. The present invention focuses on this point, and provides a storage device that can detect and correct errors by adding a series of redundant bits to information of two or more words.

SUMMARY OF THE INVENTION An object of the present invention is to provide an inexpensive and highly reliable storage device by reducing the proportion of added redundant bits in the total.

The present invention provides a temporary storage register with a capacity for k words in the write circuit or read circuit of a memory circuit, detects or corrects errors simultaneously for k words of information bits, and reads or writes data in the memory circuit. is characterized in that it is performed by sequentially selecting one word or a small number of words.

This will be explained in detail below using the drawings.

FIG. 1 is a circuit diagram of a device according to an embodiment of the present invention.

In the figure, 1 is an input terminal, 2, 3, 4, 5 are registers, 6 is a redundant signal addition circuit, 7 is a register, 8 is a selection circuit, 9 is a storage circuit, 10 is a distribution circuit, 11, 12, 13, 14 ,1
5 is a register, 16 is a selection circuit, 17 is a decoding circuit, 18
is a correction circuit, 19 is an output terminal, 20 is an error detection circuit, 2
1 is an error output, and 22 is a control circuit. The device shown in FIG. 1 is a storage device suitable for an electronic computer or an electronic exchange, and stores a digital signal applied to an input terminal 1 in a storage circuit 9, and outputs it to an output terminal 19 when necessary. This is a reading device.

Each circuit on the input side of the memory circuit 9 is a write circuit, and each circuit on the output side is a read circuit. These circuits are configured to be controlled by a control circuit 22. There are four registers 2 to 5 in the write circuit (k=4), which are used to temporarily store input signals, and each has a storage capacity for one word.

The register 7 is for temporarily storing the redundant signal added by the signal adding circuit 6. The selection circuit 8 is a switch circuit for making a selection when writing the contents of each register into the storage circuit 9. The distribution circuit 10 sequentially reads out the contents of the storage circuit 9 and reads out the contents of the memory circuit 9,
Then, the signal read out from the storage circuit 9 is temporarily stored.
Each register 11-15 has a storage capacity for one word. Register 15 is for temporarily storing redundant signals. The selection circuit 16 is a switch circuit for selecting the contents of each register when sending the read signal to the output terminal 19. The error detection circuit 20 is a circuit that detects errors in a series of signals sent out, and sends a signal to an error output 21 if there is an error. The decoding circuit 17 is a circuit for decoding the position of an erroneous bit when there is an error, and the signal of that bit is corrected by the correction circuit 18. The path through which one of the outputs of the correction circuit 18 is fed back to the write circuit is a rewrite loop for rewriting the output signal. The feature of the device shown in FIG. 1, which is an embodiment of the present invention, is that a redundant signal is added to the signal applied to the input terminal 1 to perform error detection or correction, instead of performing error detection or correction for each word. -4) It consists in doing things one word at a time. That is, when the signal applied to the input terminal 1 is temporarily stored in registers 2 to 5 for each word, a redundant signal is added by the signal addition circuit 6 to the information bits for the four words. , is temporarily stored in register 7. By doing so, the number of bits of the added redundant signal can be significantly reduced.

To give a concrete example using the above-mentioned equation (1), the number m of information bits that can correct a 1-bit error is as shown in Table 1 for the number n of added redundant bits. That is, as the number m of information bits increases, the number of additional bits n
The proportion of

In the device shown in FIG. 1, signals temporarily stored in registers 2 to 7 are sequentially written into a storage circuit 9 via a selection circuit 8.

This is another feature of the present invention, which reduces the number of bit signals that are sequentially selected and processed simultaneously, making the device economical. Also when reading out the contents of the memory circuit 9, the distribution circuit 1
It is read out sequentially starting from 0.

Error detection and correction using redundant bits is performed for four words at a time. Signals for four words are read out to registers 11 to 14, and their redundant signals are temporarily stored in register 15, respectively.

These are sequentially selected by the selection circuit 16 and sent to the output terminal 19 via the correction circuit 18. At this time, the error detection circuit 20 simultaneously detects whether there is an error in the contents of each register, and if there is an error, a signal is sent to the error output 21. Further, the error correction circuit 18 is informed of the position of the bit to be corrected via the decoding circuit 17. The correction circuit 18 performs correction by replacing the bit with O or 1. The signal path returning from the correction circuit 18 to the input terminal 1 is used once when corrected information is written into the storage circuit 9 again.

In the above example, the number of registers in each of the write circuit and the read circuit is k+1, but if the number of registers is further increased as in equation (2) above, the ratio of the number of redundant bits will be further reduced, which is advantageous. becomes.

Next, a specific example of the error detection or correction circuit means will be explained.

In the explanation of the embodiment shown in FIG. 1, the l word was described as having an 8-bit structure, but since explaining this example would result in a long number string, the next example will be explained assuming that one word has l bits. That is, a means for performing inspection and correction by adding redundant bits to 4-bit information will be described. 2
.

, 21, 22, 23 for the 4-digit information signal bits,
The bits of the additional redundant signal for testing are assumed to be A, B, and C, and are arranged as follows. A, B, 23, C, 22, 2l, 2 On the other hand, Table 2 shows the bits of each digit corresponding to decimal numbers 1 to 10.

In this case, the A bit has even parity at digit numbers 1, 3, 5, and 7, the B bit has even parity at digit numbers 2, 3, 6, and 7, and the C bit has even parity at digit numbers 4, 5, 6, and 7. are used to obtain each. Now, decimal number 6 (
1100110), and as a result of the error, 1
If 100 by 10 is read out, the error is corrected as follows. Odd-even test digit numbers 4, 5, 6, 7 Odd parity... 1 Same digit numbers 2, 3, 6, 7 Even parity not... 0 Same Digit numbers 1, 3, 5, 7 Odd parity not... 1 So, the odd-even parity results are 10 from top to bottom.
1......5 in decimal, indicating that the fifth digit number is incorrect.

If the fifth digit of the above erroneous result is replaced from 0 to 1, the correct result will be obtained. If there is no error in the read signal, the combination of odd-even parity is 000 (=0).
Next, regarding the example of 1 word and 1 bit, the circuit configuration for error detection and correction will be explained using the embodiment shown in FIG.

FIG. 2 is a diagram showing an example of the circuit configuration of the signal addition circuit 6 of the embodiment shown in FIG.

Each gate circuit G1 is an exclusive OR circuit (Exclusive OR circuit).
iveOR), and the two inputs are [1,0] or [
0, 1], the output becomes 1. Digit numbers 1, 2, and 4 are redundant additional signal bits. FIG. 3 is a diagram showing an example of the circuit configuration of the error detection circuit 20, decoding circuit 17, and correction circuit 18 of the embodiment shown in FIG.

In the figure, each gate circuit G1 is an exclusive OR circuit, G2 is an OR circuit, and G3 is an AND circuit. Outputs marked with ○ are inverted outputs. Similarly, no matter how many bits one word has, or even if k is even larger, a larger structure can be obtained by expanding the above structure. To make the explanation easier to understand, error detection and correction means have been described using one word and one bit, but as described above, the effect of the present invention becomes greater as the number of information bits increases.

As described above, according to the present invention, writing to or reading from a memory circuit is not performed for a plurality of words at once, but for each word or a small number of words. Since adding redundant bits all at once does not interfere with signal processing, adding redundant bits at once to multiple words can This has the effect of reducing the ratio of the number of signal bits to the total signal bits, thereby making it possible to obtain a memory device that can be used economically.

In addition, in the above description, a case has been described in which both the write circuit, which is the input side, and the read circuit, which is the output side, of the memory circuit 9 are provided with an error detection and correction circuit, but the circuit may be provided only with respect to the write circuit. .

In that case, errors occurring in the memory circuit 9 or during reading cannot be detected and corrected, but detecting and correcting errors in the input signal may be sufficient for practical purposes. In addition, the readout circuit is also equipped with an error detection and correction circuit, and when it is necessary to shorten the readout time, the control is switched so that the readout is performed directly without performing the error detection and correction operation. It can also be configured.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a device according to an embodiment of the present invention. FIG. 2 is a circuit configuration diagram of a redundant signal adding circuit portion of an apparatus according to an embodiment of the present invention. FIG. 3 is a configuration diagram of a circuit for error detection and correction provided in the readout circuit of the apparatus according to the embodiment of the present invention. 1... Input terminal, 2, 3, 4, 5...
...Register, 6...Redundant signal addition circuit, 7.
...Lujistar, 8...Selection circuit, 9...
...Memory circuit, 10...Distribution circuit, 11,1
2, 13, 14, 15... register, 16...
...Selection circuit, 17...Decoding circuit, 18.
... Correction circuit, 19 ... Output terminal, 20.
...Error detection circuit, 21...Error output,
22... Control circuit, Gl, G2, G3...
...Gate circuit.

Claims (1)

[Claims] 1. Comprising a write register that temporarily stores an input digital signal, a storage circuit that stores the signal temporarily stored in the register, and a read register that reads and temporarily stores the contents of the storage circuit. In the storage device, at least one of the write register and the read register is configured to have a capacity capable of storing a plurality of words of digital signals, and the plurality of words are temporarily stored in the register configured to have the capacity. For digital signals of words, there is a means for simultaneously detecting or correcting errors for a plurality of words by adding a group of redundant bits, and a means for detecting or correcting errors for the plurality of words at the same time. A storage device comprising means for selectively writing into or reading from the storage circuit.