JPS5971546A - Reverse assembly method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL APPLICATION The present invention converts executable code output from an assembler in a data processing system into a corresponding set of pre-assembly words and associates this executable code with Concerning disassembly methods for debugging software.

Background Art and Problems A typical logic state analyzer has a disassembler function. To debug a software package represented by executable code, a disassembler is used to convert a set of executable code generated by an assembler of a data processing system into a corresponding set of assembly language mnemonics. For example, as shown in FIG. 1A, during the software development process, an assembler or compiler generates executable code.

Note that this assembler uses assembly information from the user.
Receives the command (, issues a command capable of executing i+J 41:.

This executable code is comprised of a number of binary codes representing assembly language instructions and is available to the target system (eg, a microprocessor). As shown in FIG. 1B, a logic analyzer disassembler is used for software analysis. Here, the executable code utilized on the target system is translated into a corresponding set of assembly 88% mnemonics. The corresponding series of assembly language instructions is analyzed to debug the series of assembly language instructions.

If the target system of Figure 1A correctly executes an assembly language instruction as defined by a corresponding set of assembly language mnemonics, then that execution immediately produces the result desired by the user. If this is the case, then the series of assembly language instructions (or the Western equivalent of this assembly language instruction) has been accurately described.

As mentioned above, an assembler assembles a series of assembly language instructions input by a user and generates executable code made up of a number of binary codes. The target system is typically, but not limited to, a microprocessor. This microprocessor executes the binary code generated by the assembler. A logic analyzer can monitor the execution of these binary codes. To debug (tweak) this code, the binary code (executed by the microprocessor) must be translated back into a set of assembly language instructions, i.e., a corresponding set of assembly language instructions that can be interpreted by the user. It is necessary to disassemble it into Monisoku.

In order to disassemble a number of binary codes into a corresponding set of assembly words, the information necessary to create a table must be entered and stored in memory. This table has two columns of information, the first of which consists of a list of binary codes representing all binary codes that the microprocessor can generate. The second column also includes a correspondence list of assembly language mnemonics (instructions) related to binary codes.

Each binary code associated with a number of binary codes generated by the microprocessor is disassembled as follows.

That is, first, in the first column of the table stored in memory, the address (location) of the binary code to be disassembled is
Search for. Next, in the second column -ζ, confirm the corresponding assembly directive (instruction). Thus, by using this table, a large number of binary code 1's generated by a microprocessor can be disassembled into a corresponding set of assembly language binary codes.

However, with conventional disassemblers, the task of creating the tables described above is extremely tedious, if not impossible. For most 8-bit microprocessors, the first column of this table consists of a list of 2e (or 256) entries. Although 256 entries would be better, for a 16-bit microprocessor, the first column of the tickle would consist of a list of 21 @ (i.e., 65536) binary code entries. Therefore, the user must register 65,536 binary codes and related instructions to create a table. When creating this table, the memory capacity required to store the table becomes enormous. Therefore, disassembly using conventional disassemblers (particularly for 16-bit processors) has been impractical, if not impossible.

Nowadays, conventional disassemblers include read-only memory (ROM) with encoded firmware. This firmware debugs a series of assembly language instructions executed by the microprocessor. However, this ROM disassembles assembly language instructions that only certain types of microprocessors execute. If another type of microprocessor is used to execute the above instructions, this ROM
The firmware within is not capable of disassembling instructions.

So °ζ, the firmware R allows you to remove the old ROM and accurately disassemble assembly language instructions.
Need to convert to OM. Executing a series of assembly language instructions using a different microprocessor requires removing the old ROM and converting it with a new ROM, making the use of conventional disassemblers very limited.

OBJECTS OF THE INVENTION Accordingly, one of the objects of the present invention is to provide a disassembly method that improves the drawbacks of conventional disassemblers.

Another object of the present invention is to improve the drawbacks of the prior art by allowing the user of a disassembler to input information necessary for table creation.

Still another object of the present invention is to provide binary codes and related assembly language commands (commands) necessary for creating the table related to disassembly processing when the user inputs the information necessary for creating the table. The purpose is to reduce the number of items to a large extent and improve the shortcomings of conventional disassemblers.

Another object of the present invention is to reduce the number of entries required by the user when creating a table and to simplify the user's processing of binary needs and instructions associated with this code, thereby ameliorating the shortcomings of the prior art. It is.

Another object of the invention is to distinguish disassembled data information and instructions from executable code.

SUMMARY OF THE INVENTION The above-mentioned and other objects of the present invention are to enable a disassembler to generate all binary codes that can be generated by an assembler and all I11 items of corresponding assembly language mnemonics (commands) associated therewith when creating a table. Realize.

These binary codes and assembly language binary codes are stored in the form of a series of decision tree tables (branching sequentially based on decisions), and the elements associated with each branch of this decision tree are The input to the disassembler of the present invention is directly matched to the format of the user documentation issued by the processor manufacturer. The branches of the decision tree are also linked together in the form of a decision tree. Furthermore,
A disassembler according to the present invention is capable of disassembling executable code and thus identifying the instruction and data information contained in this code. Instructions within this executable code are identified by a first verification means, and data information within this code is identified by a second verification means.

The first and second validation means capture the instruction and data information as part of the executable code, and the capture memory of the capture device (such as a logic analyzer) stores the instruction and data information. The instructions and data information are then processed by a disassembler.

Example As mentioned above, an assembler (i.e., a microprocessor)
In order to disassemble the executable code outputted by the software, that is, a large number of binary codes, it was necessary to create the above-mentioned table. However, in conventional disassemblers,
The task of creating this table was extremely tedious, if not impossible. Therefore, a primary objective of the present invention is to reduce the number of entries of binary codes and associated instructions required to create this table, and to simplify this input. The first purpose is to reduce the number of items.
It utilizes the following general principles:

When i + j = n, 2rL>2' +2j In the embodiment of the present invention, if the assembler is a microprocessor and this microprocessor has 16 pins, then
Each binary code, or each bus state generated by this microprocessor, is a 16-bit binary number. However, the binary number that a microprocessor can generate is 21
Since there are 216 possible instructions, 216 possible instructions need to be disassembled.

Previously, a disassembler was created in memory and required a stored table. In the example above, the first column of this table is 2 (for a 16-bit microprocessor).
It consisted of a list of 16 binary numbers, and the second column consisted of a corresponding list of 216 instructions. The large number of items required made this table difficult, if not impossible, to create. In addition, conventional disassembly is a disassembly R dedicated to various microprocessors.
It was necessary to install the OM inside the logic analyzer.

On the other hand, the disassembler of the present invention also needs to create the above-mentioned table. However, each table created and stored in memory is organized in the form of a decisilon tree, and instead of one table requiring 211i item lists, they are linked together in the form of a tree. Two or more tables are used. This example uses two tables linked together, each table having 28 entries in the first and second columns.

Since 2111 > 2@+ 2fl, each of the first and second columns of the two tables according to the present invention can be created with fewer entries than the number of entries required for a conventional single table. Similarly, four tables linked to Jl in the form of a decision tree may be used.

In this case, each table requires 241 entries in the first and second columns. 216 > 24 +24 +24
+24, so creating four decision tree tables is easier than creating a traditional single table. FIG. 2 shows an example of a decision tree concept using the present invention.

In FIG. 2, multiple tables are linked together in the form of a decision tree. Next, the configuration of each table will be explained with reference to FIG. 38 and FIG. 3B. The disassembler of the present invention disassembles executable code into a set of corresponding assembly language monomonics.
First, table 1 is referred to, and then it is determined whether table 2 or table 3 is to be referred to. If table 2 is referred to, it is further determined whether table 4 or table 5 is to be referred to next. After referring to table 5, it is further determined whether to refer to table 10 or table 11 next. Referring to the combination of Tables 1, 2゜5 and l'l, one binary code (
16-bisoto binary code) into the corresponding assembly language bimonics. If a 16-bit binary code has to be disassembled, we need 24 entries in each column of Tables 1.2.5 and 11 to convert this 16-bit binary code into the corresponding assembly code. Disassemble. Each column of these tables has 24
It is easier to provide 2 items.

3A and 3B show a display of a cathode ray tube by the disassembler of the present invention. These representations are: - An example of the decision tree structure of the table described above. FIG. 3A shows a table for r 0PCODCU 1 (opcode 01) J. This r 0PCODE ff
The first column of the IJ table (lot is an 8-bit binary code.

The second column (12) is l'c for referencing other tables.
"all (call)" column. The third column (I4) is the rDIsPLAY (display) column of part of the binary code for the instruction. In FIG. 3A, the first column α [is, for example, 2
Hex code r 0100OXXXJ Teal. Ko (7)
:U -)', binary number 1-01000 J is increment (
ING) command.

Also, the lower three digit attribute bits "×χX" are ignored when this table is searched, and the (
, proceed to the table determined in column (12) and called rRBG 16J. This table I-RE! G 16J is shown in Figure 3B. 3-digit attribute bit r'XXX J is 1'
If it is 000J, it corresponds to register identifier rAXJ. Therefore, 1'0P
l'RIE CODE RI J table (Figure 3A)
By linking to the G16J table (Figure 3B) in a decision tree format, the binary code l' 010
It is determined that 0OOOOJ corresponds to the increment register AX (INCAχ) instruction.

The tables of FIGS. 3A and 3B are formatted in a unique manner to simplify the binary code (FIG. 3A) entries and their corresponding instructions. As mentioned above, the microprocessor executes each instruction and generates a binary code for each instruction. (executes a series of assembly hundred word instructions,
Each microprocessor manufacturer (which makes the software to be debugged) publishes user documentation in which the binary code generated by the microprocessor corresponds to each instruction. The format of the tables shown in FIGS. 3A and 3B is designed to correspond directly to the format of user documentation published by microprocessor manufacturers.

This matching format facilitates inputting many binary codes and associated corresponding instructions into the disassembler of the present invention when creating the table described above.

FIG. 4 shows a number of binary codes stored in the logic analyzer's disassembled acquisition memory.

These codes originate from a microprocessor and correspond to the many instructions that the microprocessor executed. A one-six analyzer (capture device) according to the present invention captures binary codes from a microprocessor and stores them in an capture memory. Please note that these binary codes are not subject to disassembly processing by the disassembler of the logic analyzer of the present invention, nor are they related to the assembly language bimonics corresponding to the binary codes. .

The microprocessor is part of the user circuit.

This user circuit includes a first memory (e.g., ROM) that stores a series of assembly language instructions, and a second memory (e.g., ROM) that stores data information used by the microprocessor when executing the instructions stored in this first memory. For example, random access memory (RAM). In FIG. 4, a first column of information (I6) includes address data indicating an address in a first memory of the user circuit that stores assembly language instructions and a second memory of the user circuit that stores data information. The second column (18) consists of a number of tag bits, which are part of the code executable by the microprocessor. A distinction is made between binary codes generated by the microprocessor and representing assembly language instructions stored in a first memory, and binary codes generated by the microprocessor and representing data information stored in a second memory. The third column (20) corresponds to the address in the first column (16) and consists of assembly language instructions and data information expressed in hexadecimal notation.However, the instructions and data information in the third column correspond to the addresses in the first column (16). Note that it is not easy to decipher and understand because it is expressed as .

To debug the assembly language instructions in the first memory of the user circuit, the 413th! The information in column (20) of fI can be easily read, i.e., the microprocessor can easily determine and analyze the instruction and data information generated and stored in the acquisition memory of the inverse assembler of the logic analyzer. , these commands and data information are the first
It is necessary to determine the extent to which it accurately reflects the sequence of assembly language instructions stored in memory.

However, as mentioned above, in order to convert the information shown in Figure 4 to the information shown in Figure 5, the information must be manually stored in the disassembler's memory (RAM) and the table described above must be created. No. This table consists of a number of binary codes in the first column that can be generated by the microprocessor and the corresponding instructions or assembly words in the second column. Place the binary or preferably hexadecimal assembly language instruction in the third column (20) of FIG. Place it in

Using this arranged assembly mnemonic, a logic analyzer such as Neo is displayed in FIG.

However, as mentioned above, when an 8-bit or higher microprocessor in the user circuit is used in combination with a conventional logic analyzer disassembler, the task of creating tables is not impossible, but extremely difficult. . Yo °C
1. FIG. 2 shows the decision tree structure of the table stored in the RAM of the logic analyzer according to the present invention.

3A and 3B simplifies the task of creating tables.

FIG. 6 is a system block diagram of a logic analyzer disassembler according to the present invention.

-Lf circuit (26) connects t! to the system bus. It has a first memory (typically ROM) (26A),
This memory stores the firmware/software to be debugged. The user circuit (26) also has a microprocessor (26B) connected to the system bus, which executes firmware/software and which executes executable code, i.e. a number of binary Generates code. Additionally, the user circuit (26) includes a second memory connected to the system bus.
(Representative 2 is RAM) (26G). The microprocessor (26B) further connects to the personality module (2). This personality module receives a binary code from a microprocessor (26B), stored in a first memory (26A), and receives a received assembly command instruction and stores it in a second memory (26C). Distinguish between stored and received data information.Also, the personality module (
28) allows one tag bit to be processed by a microprocessor (
26B ) to the assembly language instruction received from °ζ
and assigns other tag bits to data information received from the microprocessor. A typical personality module that performs the function of the personality module (2B) shown in FIG.
χX (for example, P for 6809 type microprocessor)
MIII) module. The details of the structure of this personality module (2 days) are disclosed in U.S. Patent Application No. 312466 (corresponding to Japanese Patent Application Laid-open No. 58-80743) filed on October 19, 1981. (7) Mei IIIM
There are two disclosures. Personality module (28)
Other modules that perform this function include Tektronix Incorporated standard part number P00.
There is 9-MC68000.

Personality: - receives assembly language instructions, data information, and corresponding tag bits from a module (28) connected to a module (28). Insert the other end of the data acquisition probe (bond) A (30) into the memory (4o
). Other data acquisition probe bonds, namely Probe Bod B (34), Probe Bod C (36) and Probe Bod D (3B), are also connected to the acquisition memory (40) in the form of a data bus. . Probe bonds (3o), (34), (36) and (3
8) each has 8 probe tips. These probe tip wires, personality module (
28) or a plurality of logic signals (representing a number of binary codes) from the terminals of a device under test, such as a microprocessor (26B) in a user circuit (26). These probe bonds transfer multiple logic signals to the acquisition memory (40). Acquisition memory (4o) is probe bond (3o), (34), (36) and (3 days)
The area is divided into ``ζ'' areas corresponding to each area.

Load the memory address register (42) into the memory
(40) to address a specific location in this memory. The logic signal from the probe bond is vh multiplied into the addressed location of the acquisition memory (40) defined by the memory address register (42).

The logic signal acquired by probe bond A (30) is stored in the area for probe bond A of acquisition memory (40). Similarly, “Probe Bod” (34)
.

Each acquisition probe bond is further connected to a word recognition circuit (
44) Connect to human power. This word recognition circuit (44)
detects whether the acquisition memory (40) has accumulated the desired word from the acquisition probe and, in response to this detection,
Provides the output signal to the main bus of the logic analyzer's disassembler.

This output signal includes data, address and control information. The above-mentioned desired word is a word input by the user using the menu on the display before starting data acquisition. The word recognition circuit (44) is converted into a counter (46)
Connect to. When the word recognition circuit (44) receives the desired word from the acquisition probe pot, the counter (46)
) to drive.

The clock circuit (48) also drives the counter (46) so that the counter (46) counts a predetermined number.

counter (46) to memory address register (42)
), and when the count value of this counter reaches a predetermined number, it sends a signal to the memory address register (42). The memory address register (42) is connected to the counter (4
6), the address setting function by this memory address register is stopped. Therefore,
Acquires the logic signal from the acquisition probe and stores it in memory (
40) to stop further accumulation.

A controller interface/register circuit (50) is connected to the output of the acquisition memory (40) to receive stored data from the acquisition memory (40) in continuous mode.

An interface/registration circuit (50) is further connected to the main bus (52) of the inventive disassembler and supplies stored data to this main bus. Further, the interface/register circuit (50) is connected to the memory address register (42), the acquisition memory (40) and the word recognition circuit (44). Therefore, the interface/
When the register circuit (50) receives control data from the main bus (52), this circuit (50) controls the accumulation/flooding mode of the acquisition memory (40) and the addressing of the acquisition memory (40). The address change speed of the memory address register (42) that performs this is controlled, and the desired word detected by the word recognition circuit (44) is controlled.

Microprocessor (54), keyboard (56), R
AM (58), ROM (60) and display controller (
62) to the main bus (52) of the disassembler of the logic analyzer.

The microprocessor (54) is the central processing unit. This microprocessor (54) is connected to the keyboard (56)
The information from the acquisition memory (40) received via the controller interface/register circuit (50) is processed according to the instructions received from the controller and the firmware stored in the ROM (60), and the control is performed according to this processing. Generate a signal. The RAM (58) stores the above-mentioned table in the form of a decision tree. That is, the keyboard (56)
, the disassembly of the logic analyzer, UnoR
The binary code and its related instructions are stored in the AM (58). The firmware stored in the ROM (60) allows the microprocessor y”t (54
) creates a table in the form of a decisidy tree according to the binary code inputted by the keyboard (56) and the associated commands, and stores it in the RAM (58). The display controller (62) operates in response to instructions from the ROM (60) and processing instructions from the microprocessor (54), and displays on the display monitor (64) of the disassembler of the logic analyzer. The display on the display monitor (64) takes place with the aid of a character generator (66) connected between the display monitor (64) and the display controller (62).

The display monitor (64) displays the displays shown in FIGS. 3A and 3B. Microprocessor in user circuit (26B
) and the associated instructions from the user documentation of the logic analyzer are transferred to the disassembler of the logic analyzer via the keyboard (56), and the user of this disassembler can see the display on the monitor (64). . These binary codes and instructions are stored in the user circuit (26
Microphone 1 in ) represents all the binary codes that can be generated by the J processor (26B) and the associated assembly language code.

The operation of the system block diagram of the logic analyzer disassembler according to the present invention shown in FIG. 6 is illustrated in FIG.
In connection with FIGS. 3A, 3B, 4 and 5,
This will be explained next.

1: Users of the I-thick analyzer disassembler should:
Microprocessor (26B) in user circuit (26)
First refer to the user documentation. A °ζ table is created using this user documentation and stored in RA,M (5B) in a decision tree format. Note that the information is input using the keyboard (56). The user produces a display as shown in FIG. 3A on the display monitor (64) using the disassembler of the logic analyzer according to the present invention. Using the user documentation, the display on the monitor (64), and the keyboard (56), the user completes the information shown in FIG. 3A. Note that this information is the binary code of the first column aω, the second column (1
2), the name of the other reference table, containing the instruction associated with the binary code in the third column (14). Next, the user can monitor (64) the disassembler of the logic analyzer.
Then, create a display as shown in FIG. 3B nine times to complete the information displayed there. That is, the user circuit (26
) in the microprocessor (26B), the user uses the keyboard (56) to select the microprocessor (26B).
26B> can occur, enter a number of binary codes.

In response to instructions from the firmware stored in the ROM (60), the microprocessor'+ (54) stores tables such as those shown in FIGS. 3A and 3B in the RAM (58). These tables contain the binary codes and associated digits entered manually by the keyboard (56). The microprocessor (54) stores the table in the RAM (54) in the form of a decision tree shown in FIG.
8) Accumulate. Therefore, the number of items required by the disassembler of the logic analyzer is small to create a table to be stored in the RAM (5B).

Create a table in the form of a decision tree shown in Figure 2.
When accumulated in AM (58), the inventive disassembler:
Microprocessor (26B) in the user circuit (26)
) is now ready to import many binary codes. Binary information representing a series of assembly language instructions stored in the ROM (26A) of the user circuit (26) is analyzed and debugged. Microprocessor (26B) is ROM
(28M) Executes the stored instructions and generates a large number of binary codes in accordance with the execution. The personality module (28) receives a number of binary codes, assigns one tag bit to an assembly language instruction contained within the number of binary codes, and assigns other tag bits to these two
Assign to the data information contained within the hex code. Data Acquisition Probe Bod A (30) has many binary codes.
and associated tag bits and stores the binary code and tag bits in the logic analyzer disassembler's acquisition memory (40). In response to a signal from the clock circuit (48), the memory address register (42) registers the probe pound A (30).
Addresses a location in the memory (40) of the acquisition corresponding to. When the word recognition circuit (44) receives the desired word from the acquisition probe, a counter (46) generates an output signal which controls the memory address register (42). Therefore, the memory atlas register (42) ceases its addressing function and the acquisition memory (4o) is placed in probe pot “A(3)”.
Stop new accumulation of binary code and tag bits from 0). The capture memory (4o) contains information in the format shown in FIG.

As mentioned above, the RAM (5B) is the Decine 9 shown in Figure 2.
Contains a table in tree format.

An example of a table format is as shown in FIGS. 3A and 3B.

The microprocessor (54) is loaded into the memory (40)
Using the table stored in the RAM (58), the assembly language command shown in the third column (20) of Fig. 4 is executed as shown in the second column (24) of Fig. 5. Convert to related assembly mnemonics. Further, the microprocessor (54) stores the converted assembly words as shown in FIG. 5 in the RAM (5B). The display controller (62) receives the assembly language mnemonics converted from the RAM (5B) and outputs them from the character generator (62).
66), these twenty-one monitors are displayed on the display monitor (64) in the format shown in FIG.

As mentioned above, the firmware stored in the ROM (60) causes the microprocessor (54) to store tables in the RAM (58) in the form of decision trees as shown in FIGS. 2, 3A, and 3B. do. RAM (5
8) accumulates this table, the acquisition memory (40
) is converted into a series of corresponding assembly language mnemonics according to the above-mentioned table and stored in the RAM (58). ROM related to (60
) The encoded firmware has the following algorithm.

The table is structured as follows.

Table definition: Describe the table environment.

Contents: What data is the table name? Ta channel on the table entered or added to the table. Explain whether there is an item of Ru.

Items 0-255: Each item includes a "value".

This "value" is "bit care" in binary values with a mask of be. If the mask value is zero (mass ), then the data Compare with this value. of the mask The value is 1 (means rXJ; mask), then this No comparison is made on bits.

Next, each item is 17 digits from 0 to 9. Contains gin. Each act option is the option that should be displayed. Naru String, Opsoyo null parameter mask, and two optional ・Contains a table.

, take in appropriate data and read it from the lj (or base\-) memory according to the definition of the algorithm table that outputs the table u'P.

Next, the first item is compared with the read data.

Process each data tip as follows:

If the mask is zero, compare the data hits and if they match, keep and compare with the next hit. If the "l-don't care" mask is 1, this pip 1- will automatically match. All bits are compared, and if they match, this is the item to be used.

If a "mismatch" occurs, the comparison begins in the next item 1 in the table. This lasts until there is a match or the item ends. This table is not called once the item is finished.

If there is a match, it is necessary to determine 1-action within 1 item.

The possible l-actions are as follows.

Indication of string (e.g. l MOVB, I ) Removal of parameter bits (hint to go to other table) Call of other table This continues until test 14I 1-Action is completed.

If there is a match, advance from the current table to the table being called. If no table is being called, perform disassembly for this line of captured data.

The ability to assign tag bits to instructions and data information in executable code is a function of the personality
On behalf of Jules (28), mic 1p1"
It can be seen that this can also be done by encoded post-processing algorithms in the ROM (60) combined with the ROM (60).

As described in the Achievements of the Invention section, since the present invention performs disassembly using a table in the form of a decision tree, the binary code and related assembly language code required to create this table are The number can be significantly reduced. Therefore, various disassemblers can be easily created, and the storage capacity for tables can be significantly reduced.

[Brief explanation of drawings]

Figure 18 shows a software development process that uses a high-level language or assembler language to generate a set of executable code, and Figure 1B shows the process of converting the executable code into a set of assembly language code. Leverage 17 assembly poverty (
Figure 2 is a diagram illustrating the concept of a decision tree of a table used in the present invention, and Figures 38 and 3B are diagrams showing the process of debugging and analyzing software (software created by a user). FIG. 4 is a representation of a cathode ray tube to explain the present invention, FIG. 4 is a diagram without a binary code to explain the present invention, and FIG. 6 is a system block diagram of the present invention. (26) is the user circuit, (28) is the personality module, (30) is the data acquisition probe bot A
, (34) is the data acquisition probe board I3, (3
6) is the data acquisition probe bot C1 (3rd day) is the data acquisition probe bot D, (40) is the acquisition memory, (42) is the memory address register, (44)
is a word recognition circuit, (46) is a counter, (50) is a controller interface/register circuit, (54) is a microprocessor, (56) is a keyboard, and (58) is an RA.
M, (60) is a ROM. DEFINE MNEMONIC5TABLE NAM
E: Souken [mouth MODE: Kyojoku-Doguchi ρ 1's IO + 211XXX
DEC++++--X TAB -=AAA REG+6 2 no 1 10XXX PUSH+
＋＋−＋−−XTAB −−−−−＾^^ Floor name 16 3886 MNEMONIC5

Claims (1)

[Claims] Using the correspondence table of the decision tree structure between the binary code signal and the corresponding assembly language binary monic,
A disassembly method characterized in that a hexadecimal code signal is converted into the above-mentioned assembly award mnemonic.