JPH04338841A - Debugger device - Google Patents

Abstract

PURPOSE:To attain the output of the easy-to-see display of correspondence between a source program and a translated code by showing the executing flow of a computer program in a diagram and securing the correspondence between the shown executing flow and the code output in regard of the visible display output processing of the computer program. CONSTITUTION:If an output instruction is received when a program 1 is debugged by a conversion result program 2 obtained by giving the prescribed conversion to the program 1, an analyzing part 3 analyzes the executing order of instruction codes for the program 1. Then the part 3 produces a flag 5 by providing successively the prescribed identification signals of the instruction codes forming the program 1 in the executing order. An output part 4 outputs a prescribed graphic showing the graph 5 and a prescribed visible display 6 where the codes of both programs 1 and 2 are set in parallel with each other. Then a correspondence analyzing part 7 analyzes the correspondence relation of the processing routes, and the part 4 adds the analyzing result of the part 7 to the output of the visible display.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debugger device for outputting a visual display of a necessary program when debugging a computer program.

0002

[Prior art and problems to be solved by the invention] Figure 2 (a
) is an example of a source program written in a known programming language, and this program is translated by a compiler to produce assembly code written in so-called assembler language, as shown in Figure 2(b). get.

The assembly code is processed by an assembler to obtain a necessary target program in machine language, the target program is executed, and the program written in the source program is debugged.

[0004] A debugger device that assists in debugging prints out (a) and (b) in FIGS. On the output, the person considers the correspondence between the source program and the assembly code and gives appropriate instructions for debugging.

[0005] In order to convert a program to be executed on a parallel processing computer, a compiler is provided with a well-known trace scheduling method ("Bulldog" by J.R. Ellis).
:A Compiler for VLIWA Archi
The MIT Press,
1986) may be applied.

In that case, the execution frequency of each processing path in the program is evaluated using an appropriate method, and necessary conversions are made to the program so that the paths that are executed relatively frequently can be executed quickly. Assembly code as shown in FIG. 2(c) is generated from the source program in FIG. 2(a).

In the example of FIG. 2(c), the operands of some instructions are omitted and the branch destinations are illustrated with broken lines.
The block CE1 is the condition judgment instruction of the source program and is the processing when the condition is met, and the branch in that block
If the condition is satisfied in the instruction, it branches to the block of TRACE2, and in TRACE2, it branches to the last unconditional branch.
Return to the TRACE1 block.

In FIGS. 2A and 2B, it is relatively easy to associate the source program with the assembly code, but in FIG. The correspondence with normal assembly code becomes increasingly difficult to see.

The object of the present invention is to provide a debugger device that can output an easy-to-see display of the correspondence between a program written as a source program and translated code by illustrating the flow of program execution and associating it with code output. do.

0010

Means for Solving the Problems FIG. 1 is a block diagram showing the configuration of the present invention. The figure shows the configuration of a debugger device, which is provided with an analysis section 3 and an output section 4 for debugging a given program 1 using a conversion result program 2 obtained by performing a predetermined conversion on the program 1.

When there is a predetermined output instruction, the analysis unit 3 analyzes the execution order of the instruction codes in the execution of the program 1, and assigns a predetermined identification symbol to each instruction code constituting the program 1. A connected graph 5 is created according to the execution order.

The output unit 4 outputs a predetermined visual display 6 in which a predetermined figure representing the graph 5, the code of the program 1, and the code of the conversion result program 2 are juxtaposed. The correspondence analysis unit 7 also includes a correspondence analysis unit 7, which analyzes the correspondence relationship between the processing paths of the program 1 and the conversion result program 2, and generates information 8 indicating the correspondence relationship, and the output unit 4 , in the case of the output of the visual display, by referring to the correspondence relationship information 8, a plurality of different predetermined information are displayed for each corresponding processing path of the graphic of the graph 5, the program 1, and the conversion result program 2. Output is made in the same display mode selected from the display modes.

[0013]

[Operation] When the debugger device of the present invention specifies and outputs a program such as that shown in FIG. ) can be output side by side with the conversion result programs, and by using appropriate highlighting etc., the correspondence of processing paths among the three displays can be displayed in an easy-to-see manner.

[0014]

[Example] When the analysis unit 3 in FIG. 1 receives a predetermined output instruction, it sequentially analyzes the instruction codes of the specified program 1, creates information on a graph 5, and notifies the output unit 4, and also When analyzing, the correspondence analysis unit 7 is notified.

[0015] If the program 1 has a line number, statement number, or block number, the analysis unit 3 uses any of these numbers as an identification symbol, and if there is no such number, it uses it as an identification symbol. , each instruction code is given a number in the order of its arrangement on the program and used as an identification symbol.

As illustrated in FIG. 3(a), the information in graph 5 is provided with preceding instruction symbol and successor instruction symbol columns in the section for each identification symbol, and in the preceding instruction symbol column, the preceding instruction symbol column is provided. Record the identification symbol of one or more preceding instruction codes if there is one, or the value indicating that there is no preceding instruction, and record one or more identification symbols of one or more preceding instruction codes if there is an instruction to proceed to next. The configuration is such that an identification symbol of a successor instruction code or a value indicating that there is no next instruction is recorded.

FIG. 4 shows an example of the processing flow of the analysis unit 3. When the identification symbols of instruction codes are set as described above in processing step 10, terms corresponding to those identification symbols are set in processing step 11. A table having a configuration as shown in FIG. 3(a) is created, and all preceding instruction symbol columns and successor instruction symbol columns are initialized to predetermined values indicating blank columns. Each column is made large enough to record the required maximum number of identification symbols.

After the above preparations, necessary control information etc. are initialized, and in processing step 12 it is determined whether all instruction codes have been completed, and if there are instruction codes to be processed, they are picked up in order from the beginning, and in processing step 13 Identify the successor instruction for that instruction.

If there is a successor instruction (generally multiple for decision branch instructions, one for other instructions), processing step 1
In Step 4, record all of those identification symbols in the successor instruction symbol column of your own section.

Next, in processing step 15, the own identification symbol is recorded in the preceding instruction symbol column of all the identification symbol entries just recorded, and the process returns to processing step 12. Also processing step 1
If there is no successor instruction in step 3, the process directly returns to step 12.

[0021] In this way, the instruction codes of the program are successively extracted and processed one by one, and the process ends when all the instruction codes have been processed. Through the above processing, the
) The information of the content of (a) is created as graph 5 from a source program such as (a).

In outputting a visual display, the output unit 4 creates and outputs a figure as shown in FIG. 3(c), for example, based on the graph information shown in FIG. 3(b). For example, the correspondence analysis unit 7 executes an analysis similar to the compiler's translation process on the source program of the program 1 without actually generating a translation result, thereby determining the relationship between the code of the converted program 2 and the code of the program 1. Correspondence information 8 indicating correspondence is created. The correspondence information 8 is, for example, information that associates each identification symbol of the program 1 with the line range of the conversion result program 2.

The output unit 4 generates a graph figure from the graph 5 as described above, and outputs it together with the codes of the program 1 and the conversion program 2 in a format as shown in FIG. 5(a), for example. At this time, the correspondence relationship information 8 is referred to, and as shown by the shaded area in the figure, the correspondence of the processing paths is displayed in an appropriate predetermined highlighted manner to facilitate differentiation.

The above is a case where a source program is specified as program 1. However, if program 1 is ordinary assembly code, a visual display as shown in FIG. 5(b), for example, can be output by almost the same processing. .

[0025]

[Effects of the Invention] As is clear from the above description, according to the present invention, when outputting a visible display of a necessary program for debugging a computer program, the flow of program execution is illustrated. By associating the output with the code output, an easy-to-read display of the correspondence between the source program and the translated code is output, which has a significant industrial effect of improving work efficiency in program debugging.

[Brief explanation of drawings]

[Figure 1] Block diagram showing the configuration of the present invention

[Figure 2]
Diagram showing an example of program code display

[Figure 3] Explanatory diagram of the graph

[Figure 4] Processing flow diagram of the analysis section

[Figure 5] Diagram showing an example of the output of the present invention

[Explanation of symbols]

1 Program 2 Conversion result program 3 Analysis department 4 Output section 5 Graph 6 Visible display 7 Correspondence analysis section 8 Correspondence information 10-15 Processing steps

Claims (2)

[Claims] [Claim 1] A conversion result program (2) obtained by performing a predetermined conversion of a given program (1) into the program.
When performing debugging, an analysis section (3) and an output section (4) are provided, and when a predetermined output instruction is received, the analysis section (3) outputs the instructions for executing the program (1). The execution order of the code is analyzed and a graph (5) is created in which predetermined identification symbols of the instruction codes constituting the program are connected according to the execution order, and the output unit (4) outputs the graph (5). It is characterized by being configured to output a predetermined visual display (6) in which a predetermined figure representing the program, the code of the program (1), and the code of the conversion result program (2) are juxtaposed. Debugger device. 2. A correspondence analysis unit (7) is provided, the correspondence analysis unit analyzes the correspondence relationship between the processing paths of the program (1) and the conversion result program (2), and determines the correspondence relationship. The output unit (4) generates information (8) indicating the correspondence relation information (8) in the case of outputting the visible display (6).
By referring to , a plurality of different predetermined display modes are selected for each corresponding processing path of the graphic of the graph (5), the program (1), and the conversion result program (2). 2. The debugger device according to claim 1, wherein the debugger device outputs data in the same display mode.