JPS5970021A - Dynamic type semiconductor device - Google Patents

Abstract

PURPOSE:To keep normally the operation of a circuit without excessive delay even if a power voltage is changed by providing a charging circuit precharging a precharge terminal to the power voltage. CONSTITUTION:Enhancement type MOS TRs 1, 2 constitute a push-pull type dynamic circuit. The charging circuit 100 executes a booster trapping action precharging a terminal OUT to the power voltage. An enhancement MOS TR3 connects the source to a booster trapping node (a), the gate to a power supply VDD and the drain to a precharge signal phi1 of which rise time is faster than that of a precharge signal phip by t3. One end of an electrostatic capacitor 4 is connected to the node (a) and the other end is connected to the signal phip. Selection of the time t3 and the capacitor 4 makes it possible to change the precharging level in accordance with the variation of the power voltage, so that the circuit can be operated without excessive delay even if the voltage is temporarily raised especially during a precharging period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a dynamic integrated circuit device, which enables normal circuit operation even when the power supply voltage used varies.

[Prior art]

Conventionally, the circuit shown in FIG. 1 has been widely used as a push-pull type dynamic circuit. (1) in the figure.

(2) is an enhancement type transistor in which φp is at a high level during the precharging period, usually at the power supply voltage level VDD, and OUT is precharged to the level of VDD-VT. Here VT is the threshold voltage of the MOB transistor. When circuit operation begins.

IN rises to a high level, and MOS sets the OUT precharge level to the ground level (0 ■).
) is discharged through the transistor (2), and the next stage circuit detects the low level of this OUT, and a signal is transmitted. In this conventional device, if the power supply voltage temporarily increases by t during the precharge period and then decreases again, and one circuit operation starts, the circuit may not operate normally. This will be explained based on the waveform diagram in Figure 2. In normal operation when the power supply voltage is VDD (L), IN
OUT is at the precharge level V after
It takes a certain delay time t1 determined by the stray capacitance of the OUT terminal, the current drive capability of the MOB transistor (2), the rising waveform of IN, etc., until the voltage reaches 0V from DD-VT.

on the other hand.

If the power supply voltage rises to VDD (goods) by t during the precharge period, the level of e f'p rises to VDn (El) by t, so the OUT charging level mode DD (L) -
VT color rises to L to vDD(II) -VT. After that, the power supply voltage returns to VDD), and the level of φp decreases to VDD.
Even when the voltage returns to DD (L), the precharge level of OUT is maintained at the level of VDD (II) - VT. In the subsequent circuit operation, when IN rises and discharges OUT, the low level VDD (L) must discharge the high precharge level VDD times -VT, and the normal operation is performed as shown in Figure 2. The delay time t! is large compared to the time tl! This results in a delay in circuit operation.

As described above, in the conventional circuit, the power supply voltage rises by L during the precharge period, and even when the voltage returns to the original state, the circuit operation is delayed.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones such as L. By providing a charging circuit that precharges the OUT terminal to the power supply voltage, the precharge level changes in accordance with fluctuations in the power supply voltage. It is an object of the present invention to provide a semiconductor device configured to maintain the power supply voltage level during one circuit operation, and in which the circuit operation can be performed normally without excessive delay even if there is a fluctuation in the power supply voltage.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 8th
In the figure, (1) and (2) are enhancement type MO8) transistors that constitute a push-pull type dynamic circuit, as in Figure 1, and (1ω) is.

A charging circuit (3) with a bootstrap function that precharges the OUT terminal to the power supply voltage has a source as a bootstrap node (a), a gate as a power supply VDD, and a drain as a second precharge signal φp, J:st, only. Enhancement type MC)S) transistor connected to the first precharge signal φf with early rising time, (4)
C @ one end to bootstrap node (a) and the other end.

This is a capacitance connected to the precharge signal -p.

(hereinafter abbreviated as boost node) Below, the circuit operation of the present invention will be explained based on Figure @4.

Here, as in the description of the conventional circuit, the power supply voltage rises once during the precharge period.

This shows the circuit operation when the circuit returns to its original state.

In the circuit shown in FIG. 8, the boost node (1) is precharged by the precharge signal φf whose rise time is earlier than φp by t3 during the precharge period.

-p rises due to capacitive coupling of capacitance jl(4).

The potential in (a) decreases by t. Its size is determined by the precharge level at e d', the capacitance (4), and the boost node (a
), ts depends on the ratio of stray capacitance of the node (
Select t until the precharge level in a) is sufficient.

By increasing the ratio of the capacitance (4) to the stray capacitance of the node (a) by about 8 times or more, the boost node (1) has a voltage (t) that is lower than the threshold voltage (VT) of the MOS transistor in the power supply voltage. VDD +Vn) appears, and the power supply voltage is precharged to the OUT terminal.

If there is no fluctuation in the power supply voltage, then IN rises and
The time until OUT is discharged is t4.

On the other hand, even if the voltage is increased once and the precharge level at the C) UT terminal increases, if the N voltage returns to its original level, the boost node (a) Therefore, the precharge level of the OUT terminal returns to the power supply level at that time, and then IN rises to 0.
The time until UT is discharged is t4, which is equal to the case where there is no voltage fluctuation.

In the embodiment L, the charging circuit is an enhancement type MO8.
) We have shown an example of a transistor (3) and a capacitor (4), but as shown in Figure 5 (101), the ON resistance is about 5 times higher than the ON resistance of the MOS transistor (2). The effect does not change even if it is composed of only a resistor block with a size of .

Also, the details of the operation of the 9 circuits are omitted, but the charging circuit (1
), are applied to other specific dynamic circuits are shown in Figures 6, 7, and 8, and examples of application of the t-distribution charging circuit (101) are shown in Figures 9, 10, and @11. show.

(2-1), (2-2), (7), (8), (
9) , 01 , 01 , U , 01 , α4
.

QQ, ◇η, (to), a groan, (e), is an enhancement type MO8 transistor, (c), is MOB
capacity.

〔Effect of the invention〕

As shown in t below, according to the present invention, by providing a charging circuit that sets the terminal to be precharged to the power supply voltage during the precharge period, the precharge level changes in accordance with fluctuations in the wL power supply voltage. Therefore, even if there are fluctuations in the power supply voltage, especially temporary voltage rises during the precharge period.

Circuit operations can now be performed normally without excessive delay.

[Brief explanation of drawings]

Figure 1 shows a conventional push-pull dynamic circuit;
The figure is a waveform diagram illustrating the operation of the circuit shown in Figure 1 when there is a fluctuation in the power supply voltage. Figure 8 is a diagram showing a charging circuit with a boost effect according to an embodiment of the present invention. Figure 4 6 is a waveform diagram showing the circuit operation of the present invention, FIG. 6 is a diagram showing other embodiments of the present invention, FIG. 1 is a diagram showing an example in which the charging circuit of the present invention is applied to an MO8 dynamic circuit. (i), (2), (2-1)I(2-2),
(3) , (7) e (s) , (9) , Q
tl, U. (2), α field, α4. (lf9.Qη, (II,
Ql, (E)...Enhancement type MO8) transistor, Qυ...Resistance, (4)...Capacitance, θ1
9, C2]) ・MO8 capacity, (100), (1
01) - Charging circuit type Shinto Kuzuno - Fig. 1 Fig. 2 Kazumasa and Takashi - Me Ikkan Tenhen Hatsuto - Purchasing - Fig. 3 Fig. 5 Fig. 4 O @ Fig. 7 Figure 8 N Procedural amendment (spontaneous) Mr. Commissioner of the Patent Office 1, Indication of the case Patent application No. 181008/1982 2
, Title of the invention Dynamic type semiconductor device 3, Person making the amendment 5, Detailed description of the invention and brief description of the drawings in the specification to be amended 6, Contents of the amendment 119

Claims (1)

[Scope of Claims] (1) A dynamic semiconductor device characterized by being provided with a charging circuit that precharges a bridge terminal to a power supply voltage. (2) The above-mentioned charging circuit is constituted by an enhancement type transistor and a capacitance, and enables a bootstrap effect using 22 types of precharge signals having different rise times. Dynamic semiconductor device according to claim 1. Dynamic semiconductor device according to claim 1, wherein the m-circuit filled with (3) is comprised only of resistors.