JPS5970011A - Digital gain adjusting circuit - Google Patents

Abstract

PURPOSE:To prevent a luminance level from being inverted at the adjustment of gain by providing the titled circuit with a signal selecting circuit switching a detected overflow signal of an upper bit to a digital signal indicating a specific value. CONSTITUTION:A bit shifting circuit 30 is provided with input side terminal groups bphi-b23 and output side terminal group group Sphi-S15 and can shift the relation of these connections relatively up to 8 bits. Input signal lines Iphi-I7 are connected to the terminals b8-b15 and the remaining terminals bphi-b7 and b16-b23 are earthed. Output signal lines Nphi-N7 are connected to the terminals Sphi-S7 and the terminals S8-S15 are connected to an OR circuit 40, an overflow signal detecting circuit. When the circuit 40 detects an overflow signal (s), the signal selecting circuit 50 transmits a signal indicating the maximum level outputted from a maximum value signal generating circuit 60 from a maximum value signal line M to an output line V. Consequently, the luminance level can be prevented from inversion at the gain adjustment of a digitized video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a gain adjustment circuit for a digital signal represented by a plurality of binary bits, and in particular utilizes the principle of digital multiplication by bit shift operation. The present invention relates to a new gain adjustment circuit that prevents brightness-related level inversion caused by overflow of upper bits when performing gain adjustment of a video signal.

(To) Background of the Invention Recently, digital image processing technology, which digitizes video signals captured by solid-state imaging devices such as CCDs and performs various corrections and analyzes with high precision using computers, has become popular in various fields. It is being adopted. In this case, the analog video signal is converted into, for example, an 8-pit digital signal and processed, but if the image is dark, the gain of the digital signal is increased to increase the contrast.

((3) Prior Art and Problems As a gain adjustment method for such digital signals, it is common to use a conventional digital multiplication method using bit shift. However, depending on the amount of shift, the upper bits of the input bits as the multiplicand may be dropped, causing brightness reversal.In other words, the shipit shift operation treats the upper bits as invalid. This is because the output is truncated and the middle and lower bits are carried by that amount.

If there is a valid bit in the upper bits that have been discarded, the signal that appears on the output bit F line as a result of multiplication will be higher than the other bits, even though the actual video signal as the multiplicand represents a high brightness level. This may appear as a value smaller than the value of the video signal, which causes a big problem in maintaining the magnitude relationship between input and output.

(1) Purpose of the Invention The present invention has been made based on the above-mentioned conventional situation, in which, when adjusting gain using digital multiplication by bit shift operation, the magnitude relationship of the multiplication result is impaired with respect to the magnitude relationship of the actual digital μλ force signal. The purpose of this invention is to provide a gain adjustment circuit that prevents the loss of high-order bits, and more specifically, to improve the quality of reproduced images by preventing level inversion of the video signal output due to the loss of upper bits. This is what we are trying to achieve.

(e) Structure of the Invention Briefly stated, in order to achieve the above object, the present invention provides an interconnection relationship between an input bit line and an output bit fin in a signal transmission path of a digital signal represented by a plurality of bits. In a configuration including a bit shift circuit for shifting gain adjustment, as a result of the bit shift,
A circuit is provided for detecting an overflow signal of an upper input bit disconnected from the output bit line, and a signal for switching the digital signal on the output bit line to a digital signal representing a specific value in response to the detection of the overflow signal. This device is characterized by being provided with a selection circuit.

(f) Embodiments of the Invention Preferred embodiments of the invention will now be described in more detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a gain adjustment circuit according to the present invention, in which both input and output are 8-bit
The luminance level is expressed as a value signal. The bit shift circuit 30 has a group of 24 input side terminals from bφ to 1)28 and a group of 16 output side terminals from Sφ to S15, and the connection relationship between them is relatively divided into 8 bits. It is now possible to shift up to This bit shift operation may be performed by an electronic switch operation, but the figure shows a configuration in which one terminal group is manually slid relative to the other terminal group.

Of the input side terminal group bφ to b28, eight input signal lines Eφ to F are connected to the center 8-bit terminals b8 to b15, and the remaining empty terminals bφ to 8 bits each are connected to the center terminals b8 to b15.
b7 and b16-b28 are connected to ground potential to represent logic 50'. On the other hand, among the output terminal group Sφ to S15, the first 8 bits of terminals Sφ to S7
Eight output signal lines Nφ to N7 are connected to the terminals 88 to S15 for the remaining 8 bits, and terminals 88 to S15 for the remaining 8 bits are connected to the input of a logical sum (OR) circuit 40 as an overflow signal detection circuit. Reference numeral 50 indicates a signal selection circuit, which normally passes the 8-bit digital signal N appearing on the output signal lines Nφ to N7 as it is onto the output line V, but when the output of the OR circuit 40 is When the overflow signal J is detected, the data to the output line is switched and the 8-bit digital signal indicating the maximum level /L/ from the maximum value signal generation circuit 60 is transferred from the maximum value signal line M. It acts to transmit the signal to the output line V. In other words, this signal selection circuit 50 switches the 8-bit output signal line V to /l in response to the detection of overflow signals.
/ 'l' serves as a clamp,
These circuit functions can be easily accomplished using existing integrated circuits called data processors.

Now, in this invention, the gain adjustment of the digital signal is performed using the circuit configuration as described above, but now, the signal given to the input signal line E φ to F expresses the luminance level with 8-bit luminance resolution. was digital μ
Assume that it is a video signal.

In this case, the input data does not always have 8 significant bits, and if the object is dark, the effective bits will be reduced. Therefore, for video signals with 8 or fewer effective bits, the effective bits are shifted to higher order bits to increase the gain, and the most significant bit of the output signal line has a significant number to achieve the optimum gradation and optimum contrast. Adjustments are made to obtain a reproduced image. Furthermore, even if the video signal has 8 significant digits, if you want to clearly visualize the information in the low-brightness level part, you can similarly perform a bit shift operation to cut out the information in the high-brightness part. The gain is adjusted so that the contrast of low-luminance areas is selectively increased and displayed.

In the configuration shown in FIG. 1, the gain adjustment described above is performed by shifting the connection between the input and output terminals of the bit shift circuit 80. In the case shown in the figure, the input bit line is shifted upward by two bits. A connected relationship (dotted line connection relationship) is shown. In this way, the terminal 1) 18 of the fifth digit of the input bitfin is connected to the most significant bit terminal S7 of the output bit line, and each input bit line below the fifth digit is also shifted by 2 bits, while the output bit line is shifted by 2 bits. Terminal Sφ for the lower 2 bits of the bit line
, Sl is connected to ground terminal 1)6.1)7, so
The digital video signal from the input bits φ to FF appears on the output bit line in the form of the lower 6 bits (φ to 6) shifted to the upper part by 2 bits and multiplied by 4. To sum up, this bit shift circuit 40 executes digital multiplication using the input video signal as the multiplicand and the bit shift amount as the multiplier, and as a result, a video signal with the optimum gradation is obtained. There is a conventional problem, as mentioned at the beginning, in that the upper two digits (6.F) of the input video signal are truncated as invalid bits. In other words, if the upper two digits of the input video signal are always invalid bits, there is no problem with simply shifting by two bits, but if these upper bits have significant digits,
In reality, the input video signal, which is the multiplicand, is larger than the number that is considered as the maximum significant digit at that time, so even though the output should be a signal indicating the highest brightness level, If the significant number of the calculation execution digit part is small, the brightness level I appearing on the output bit lines Nφ to N7 as a result of multiplication by 1 will be low, and the brightness level will be reversed and the reproduced image will become unnatural and inaccurate. That's why.

However, in the present invention, in order to prevent the above-mentioned level inversion, an OR circuit 40 is provided to detect an overflow signal of the upper bits accompanying a bit shift. Therefore, as mentioned above, the input bit fins 6. If a significant figure appears in any of the F, an overflow of the multiplication result is detected by the OR circuit 40, and an overflow signal is given to the signal selection circuit 50. Then, the signal selection circuit 50 is configured to give the 8-bit output twin ■ a signal of 0, % l# that exhibits the maximum brightness, regardless of the magnitude of the digital signal on the output bit fins Nφ to N7 at that time. Signal switching takes place. In this way, even if the effective signal of the upper bits of the input bitfin is lost as a result of bit shifting, the phenomenon of brightness level inversion is compensated for, so that unnatural brightness inversion will not occur in the reproduced image.

Although the present invention has been described above for gain adjustment for brightness and contrast adjustment of digital video signals, it is possible to apply it to gain adjustment for other digital signals that involve digital multiplication. Not even. Furthermore, the bit shift circuit 30 can be easily configured to automatically adjust by combining electronic logic circuits, and the signal selection circuit 50 is also equipped with an 8-state buffer amplifier with an enable terminal for each bit, so that the overflow signal can be easily adjusted. The data on the 8-bit output line V
It is possible to easily set the value to the maximum value. Furthermore, the signal applied to the output line (2) at the time of overflow signal detection does not necessarily have to exhibit the maximum value, but may be set to a specific value as appropriate depending on the purpose of the circuit.

(2) Effects of the Invention As is clear from the above explanation, in short, the present invention detects and outputs an overflow-like class of upper bits when performing gain adjustment using a digital multiplication method using a bit shift operation. It is based on the idea of flagging data to a specific value, and is highly effective in correctly transmitting the magnitude relationship of input signals to the output side. In particular, according to the present invention, it is possible to prevent the brightness level inversion phenomenon when performing gain adjustment of a digitalized video signal, which is extremely advantageous in obtaining accurate and natural reproduced images. It is.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the digital gain adjustment circuit according to the invention. In the figure, 80 is a bit shift circuit, 40 is an OR circuit as an overflow detection circuit, 50 is a signal selection circuit, 60 is a maximum value signal generation circuit, φ to F are input bit lines, Nφ to N7 are output bit fins, and M is an output bit fin. Maximum value signal twin, ■ indicates the output line.

Claims (1)

[Claims] (1) In a configuration in which a bit shift circuit for gain adjustment that shifts the interconnection relationship between the input bit line and the output bit fin is provided in the signal transmission path of a digital signal represented by a plurality of bits, as a result of the bit shift,
A circuit is provided to detect an overflow signal of an upper input bit line disconnected from the output bit line, and in response to the detection of the overflow signal, the digital JI/I/ signal on the output bit fin is made to exhibit a specific value. A digital gain adjustment circuit comprising a signal selection circuit for switching to a digital signal.