JPS55117318A - Level converting device - Google Patents

Level converting device

Info

Publication number
JPS55117318A
JPS55117318A JP2484179A JP2484179A JPS55117318A JP S55117318 A JPS55117318 A JP S55117318A JP 2484179 A JP2484179 A JP 2484179A JP 2484179 A JP2484179 A JP 2484179A JP S55117318 A JPS55117318 A JP S55117318A
Authority
JP
Japan
Prior art keywords
control signal
form
supplied
number
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2484179A
Inventor
Ryoichi Wada
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Priority to JP2484179A priority Critical patent/JPS55117318A/en
Publication of JPS55117318A publication Critical patent/JPS55117318A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/002Control of digital or coded signals

Abstract

PURPOSE:To decrease the number of digits and then increase the processing speed for the control signal by converting the control signal into the form of the floating decimal point and then giving multiplication to the D/A-converted audio signal. CONSTITUTION:Input audio signals CHA and CHB which are expressed in the digital form are supplied to multipliers 5 and 6 each. On the other hand, the setting position information of variable resistances VRA and VRB are supplied to level tables 3 and 4 after conversion by A/D converters 1 and 2 each. These tables 3 and 4 memorize the levels to be controlled in accordance with the setting position of the variable resistance, and then convert the control signal into the form of the floating decimal point featuring the fixed effective digit number. These output are supplied to multipliers 5 and 6 to be delivered in the form of the CHM signal after multiplication by signals CHA and CHB plus addition 7. Thus the number of digits is decreased for the control signal to be multiplied to increase the processing speed.
JP2484179A 1979-03-02 1979-03-02 Level converting device Pending JPS55117318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2484179A JPS55117318A (en) 1979-03-02 1979-03-02 Level converting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2484179A JPS55117318A (en) 1979-03-02 1979-03-02 Level converting device

Publications (1)

Publication Number Publication Date
JPS55117318A true JPS55117318A (en) 1980-09-09

Family

ID=12149428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2484179A Pending JPS55117318A (en) 1979-03-02 1979-03-02 Level converting device

Country Status (1)

Country Link
JP (1) JPS55117318A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5970011A (en) * 1982-10-14 1984-04-20 Fujitsu Ltd Digital gain adjusting circuit
JPS6211170A (en) * 1986-07-25 1987-01-20 Hitachi Denshi Ltd Power detection circuit
JP2009505611A (en) * 2005-08-22 2009-02-05 フリースケール セミコンダクター インコーポレイテッド Bounded signal mixer and operating method
JP2009533003A (en) * 2006-04-04 2009-09-10 クゥアルコム・インコーポレイテッドQualcomm Incorporated Automatic gain control

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5970011A (en) * 1982-10-14 1984-04-20 Fujitsu Ltd Digital gain adjusting circuit
JPS6211170A (en) * 1986-07-25 1987-01-20 Hitachi Denshi Ltd Power detection circuit
JPH0450767B2 (en) * 1986-07-25 1992-08-17 Hitachi Seisakusho Kk
JP2009505611A (en) * 2005-08-22 2009-02-05 フリースケール セミコンダクター インコーポレイテッド Bounded signal mixer and operating method
JP4862045B2 (en) * 2005-08-22 2012-01-25 フリースケール セミコンダクター インコーポレイテッド Bounded signal mixer and operating method
JP2009533003A (en) * 2006-04-04 2009-09-10 クゥアルコム・インコーポレイテッドQualcomm Incorporated Automatic gain control

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