JPS5969841A - Data processor - Google Patents

Abstract

PURPOSE:To execute the extraction of the square root of two bits always at two cycles speedy by connecting the 1st and 2nd registers and shifting them simultaneously at the shift mode. CONSTITUTION:The contents of the 3rd register 3 are subtracted from the contents of the 1st register 1 by an arithmetic device 4. If the contents of the 1st register 1 are larger than that of the 3rd register 3, a carrying signal form the device 4 is outputted to a signal line 17 and the 1st selecting circuit 6 shifts the output from the device 4 to the upper direction by one bit. Since the status of the uppermost bit of the 2nd register 2 is inputted to the lowmost bit of the 1st register 1 through a signal line 15, the 1st selecting circuit 6 selects and outputs the data. Thus, the square root operation by the extraction of the square root of two bits can be operated at two cycles by using the small number of hardwares and the operation can be executed rapidly at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Description of the technical field to which the invention pertains) The present invention relates to a data processing device equipped with a microprogram control device, and particularly to a square root calculation circuit in a data processing f'll device.

(Description of Prior Art) A conventional arithmetic circuit for calculating a square root uses a special shifter or selector during a shift operation in an arithmetic operation. Therefore, even when shifting two registers by one bit, it is necessary to perform the shift operation over two cycles, or it is necessary to provide double shifters and selector circuits. There was an increase in the amount of circuitry. Therefore, in order to find the square root using the conventional square root method of 2 bits at a time, we need to perform one subtraction operation, two shift operations (or four times), and one addition operation for correction depending on the subtraction result. It is necessary to do
3-4 cycles for every square root of 2 bits, or 5-6
Since the calculation takes many cycles, there is a drawback that the performance deteriorates.

(Detailed Description of the Invention) An object of the present invention is to store data to be square rooted in the least significant bit by a carry signal of an arithmetic circuit in a square root operation employing an open square formula in binary 2-bit units. Data obtained by shifting the most significant bit of the second register in the first register upwards by one bit, or by shifting the output of an arithmetic circuit upwards by one bit. By selecting the obtained data and setting it in the first register, and shifting the second register using the shift mode signal, it is possible to eliminate the need for addition for correction and overlap subtraction and shift. By connecting the first register and the $2 register and performing a shift operation in shift mode at the same time, it is possible to always perform 2-bit square root calculation in 2 cycles + L speed at low cost. The purpose of this invention is to provide a processing device.

(Description of structure and operation of the invention) A data processing device according to the present invention includes first to third registers, an operation circuit, a microprogram control circuit, and first to third registers.
It includes a third selection circuit and first and second shift control circuits.

When the first to third registers are given a shift mode signal, they shift in the upper direction of the internal data storage at a rate of 1 bit per clock regardless of the input data, and the shift-in data is stored in the least significant bit. It has a function to set. The arithmetic circuit receives data in at least a first register of the first to third registers as an operand, inputs data in a second register as an operand, and executes an operation. The microprogram control circuit stores all calculation routines and executes the microprogram. If there is no carry signal from the arithmetic circuit in the first shift control circuit, the data in the first register is shifted one bit in the upper direction in response to the carry signal, and the least significant bit is transferred to the second register. When the data of the most significant bit is input and there is a carry signal from the arithmetic circuit, the data of the arithmetic circuit is shifted upward by one bit in response to this, and the data of the second register is transferred to the least significant bit. This is a circuit that inputs data of the most significant bit.

The second selection circuit is a circuit for selecting the output of the first selection circuit or other external input data. When there is an arithmetic cycle signal for the arithmetic circuit, the third selection circuit selects the data obtained by shifting the data in the third register upward by one bit and the third digit from the least significant bit. A circuit for selecting between a series of data consisting of a rising signal and fixed logic value data 01 given to the lowest two bits, or other external input data. be. The first shift control circuit uses a shift cycle signal from the microprogram control t111 circuit to shift the data in the first register upwards by one pit, and transfers the data in the most significant bit of the second register to the least significant bit. This is a circuit for sending out a shift mode signal so that it can be set. The second shift control circuit sets these signals in the second register when there is an operation cycle signal or a shift cycle signal, and outputs a shift mode signal so that the internal data can be shifted upward. This is a circuit for output.

(Description of an embodiment) Next, an embodiment of the data processing device according to the present invention will be described.
In particular, an operation for calculating a square root will be explained using a diagram as an example. The data processing device according to the present invention includes first to third registers 1 to 3, a performance W circuit 4, a microprogram control circuit 5, first to third selection circuits 6, 7, 10, and first and third registers. This embodiment includes second shift control circuits 8 and 9.

In Figure 1, the first register 1 is cleared,
Set the value to be calculated as the square root in the second register 2,
A constant is written to the third register 3, and the lowest two bits are 01.
and all other values are 0.

First, before starting the calculation to find the square root, the microprogram control circuit 5 sends out a shift cycle signal twice via the signal line 11. At this time, a shift mode signal is sent to the signal line 1 from the first shift control circuit 8 and the second shift control circuit 9, each of which is composed of an OR gate.
3 and 14, the first register l transmits the state of the most significant bit of the second register 2 to the signal line 1.
The second register 2 takes in the state of the most significant bit of the third register 3 as shift-in data via the signal line 16. As a result, the contents of the first register 1 and the second register 2 are each shifted by two bits to the designated position.

Therefore, the lowest two bits of the first register 1 are
The square root is calculated and the most significant two bits of the number are set, and all others are set to O.

When data is set in each register as described above, a square root operation is performed to obtain the square root of 2 bits in 2 cycles as shown below.

1. First, the contents of the third register 3 are subtracted from the contents of the first register 1 by the arithmetic unit 4. At this time, if the content of the first register 1 is greater than the content of the third register 3,
Carry from arithmetic unit 4 (No. M occurs on signal line 17,
The output from the arithmetic unit 4 is shifted to the first selection circuit 6 by one bit in the upper direction. At this time, the state of the most significant bit of the second register 2 is input to the least significant bit via the signal line 15, and the selection circuit 6 of $1 selects and outputs this data. During this period, an arithmetic cycle signal is sent from the microprogram control circuit 5 via the signal line 12, so that the second selection circuit 7 selects and outputs the output of the first selection circuit 6. As a result, the value output from the first selection circuit is set in the first register 1. The calculation cycle signal is input to the second shift control circuit 9, and the shift mode signal sent from the second shift control circuit 9 via the signal line 14 causes
The data in the second register is shifted by one bit in the upper direction. At this time, the lowest two bits of the third selection circuit 10 are a constant of 01, and the carry signal from the arithmetic unit 4 is inputted via the signal line 17 to the third lowest bit. Therefore, for the upper bits, the selection circuit 10 of $3 selects data that is shifted upward by one pit from the contents of the third register 3. Therefore, 1 is inserted into the third bit before the constant 01 of the lowest two bits by a carry signal via the signal line 17, and this data is set in the third register 3. If the contents of the first register 1 are one digit or more smaller than the contents of the third register 3 in this calculation cycle, the carry signal from the calculation unit 4 will not be generated via the signal line 17, so the first selection The data from the first register 1 is shifted upward by one bit in the circuit 6, and the most significant bit 15 of the second register 2 is inputted as the least significant bit of the first register 1. And the third
Since the state of the carry signal input from the least significant bit of the selection circuit 10 to the third bit via the signal line 17 does not become the logical value l, the third register 3 contains the lowest two bits.
O will be inserted before the bit constant 01.

Next, a shift cycle signal is sent from the microprogram control circuit 5 via the signal line 11, and the shift cycle signal is inputted via the signal line 11 to the first shift control circuit 8 and the second shift control circuit. At 9, shift mode signals are generated via signal lines 13 and 14, respectively, and the contents of the first register 1 and the second register 2 are shifted upward by one pit.

In the above two cycles, the square root of 2 pits is performed, and at the same time, the next 2 bits of the 217th register 2 to be square rooted are taken into the first register 1 for the next square root calculation. Thereafter, by repeating the calculation cycle and the shift cycle alternately, the square root is calculated before the constant 01 in the lowest two pits of the third register 3.

For example, if the above two cycles are repeated n times, a 2n-bit square root is performed, and an n-bit square root is calculated before the lowest 2-bit constant of the third register 3.

Note that the signal line 18 for the shift mode signal in FIG. 1 is used for diagnosis, displaying register contents, writing data to the register, etc.

(Detailed Description of the Invention) As explained above, according to the present invention, the shift mode is specified by shifting data upward in 1-bit units and setting shift-in data at the lowest position. By using the first to third registers, controlling the shift operation by the lth to third selection circuits, and the first and second shift control circuits to execute a square root operation,
Since the square root operation W using 2-bit square root can be calculated in 2 cycles using less hardware, it is fast and
This has the effect that calculations can be executed quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data processing device for performing square root calculation according to the present invention. 1.2.3...Register 4...Arithmetic circuit 5...
Microprogram control circuits 6, 7, 10...Selection circuits 8, 9...Shift control circuits 11-18...Control signal lines 21-29...Data signal lines

Claims (1)

[Claims] When a shift mode signal is applied, the internal data is shifted in the upper direction at a rate of 1 pit per clock regardless of the input data, and the shift-in data is set in the least significant bit. 3 registers and
An arithmetic circuit that inputs the data of at least the first register among the first to third registers as an operand and inputs the data of the 20th register as an operand, and an arithmetic routine; If there is no carry signal from the microprogram control circuit for executing the program and the arithmetic circuit, the data in the first register is shifted upward by one pit in response to the carry signal to the lowest register. The data of the most significant pit of the second register is input to the pit, and if there is a carry signal from the arithmetic circuit, the data of the arithmetic circuit is shifted upward by one pit in response to this. a first selection circuit for selecting to input the data of the most significant pit of the second register to the least significant bit; and an output of the first selection circuit or other external input data. a second selection circuit for selecting one of the two registers; and, if there is an cycling signal to operate on the arithmetic circuit, data obtained by shifting the data in the third register upward by one pit; , the carry signal at the third bit from the least significant bit, and fixed logical value data 01 given to the two least significant bits, or other external data. A third selection circuit for selecting the input side data and a shift cycle signal from the microprogram control circuit shift the data in the first register in the upper direction by one pit, and the third selection circuit selects the input side data. a first shift control circuit for sending out a shift mode signal so that the data in the most significant pit of the second register can be set; A data processing device that performs square root calculations, which includes a second shift control circuit that sets these signals in a second register and outputs a shift mode signal so that internal data can be shifted upward. Device.