JPS5969532U - delay switch - Google Patents

delay switch

Info

Publication number
JPS5969532U
JPS5969532U JP16481482U JP16481482U JPS5969532U JP S5969532 U JPS5969532 U JP S5969532U JP 16481482 U JP16481482 U JP 16481482U JP 16481482 U JP16481482 U JP 16481482U JP S5969532 U JPS5969532 U JP S5969532U
Authority
JP
Japan
Prior art keywords
transistor
capacitor
resistor
diode bridge
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16481482U
Other languages
Japanese (ja)
Other versions
JPH0138995Y2 (en
Inventor
金田 博史
隆司 山本
Original Assignee
松下電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電工株式会社 filed Critical 松下電工株式会社
Priority to JP16481482U priority Critical patent/JPS5969532U/en
Publication of JPS5969532U publication Critical patent/JPS5969532U/en
Application granted granted Critical
Publication of JPH0138995Y2 publication Critical patent/JPH0138995Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の回路図、第2図、第3図は同上の動作
説明用の波形図、第4図は本考案の一実施例の回路図で
あり、Vsは交流電源、SWは操作スイッチ、DBlは
第1のダイオードブリッジ、DB2は第2のダイオード
ブリッジ、C1は第1のコンデンサ、C2は第2のコン
デンサ、Qlは第1のトランジスタ、Q2は第2のトラ
ンジスタ、Q3はトランジスタ、R7は第1の抵抗、R
6は第2の抵抗、Rxは第3の抵抗、Lは負荷、2はト
ライアック、3は電流トランス、5はFET、5はサイ
リスタ、7はインピーダンス切替回路である。
FIG. 1 is a circuit diagram of a conventional example, FIGS. 2 and 3 are waveform diagrams for explaining the operation of the same as above, and FIG. 4 is a circuit diagram of an embodiment of the present invention, where Vs is an AC power supply and SW is a circuit diagram of an embodiment of the present invention. Operation switch, DBl is the first diode bridge, DB2 is the second diode bridge, C1 is the first capacitor, C2 is the second capacitor, Ql is the first transistor, Q2 is the second transistor, Q3 is the transistor , R7 is the first resistor, R
6 is a second resistor, Rx is a third resistor, L is a load, 2 is a triac, 3 is a current transformer, 5 is an FET, 5 is a thyristor, and 7 is an impedance switching circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 交流電源と負荷の間に双方向性の電力制御素子を介装し
、該電力制御素子の両端に操作スイッチと電流トランス
の1次巻線との直列回路を接続し、電流トランスの2次
巻線には2次出力を整流する第1のダイオードブリッジ
を接続するとともに該第1のダイオードブリッジの直流
出力端子間には充電抵抗を介して時定数用の第1のコン
デンサと、放電用回路との並列回路を接続し、前記電力
制御素子の一方の電極と制御極との間に電力制御素子の
制御電流をオンオフし得るように第2のダイオードブリ
ッジの一対の直流出力端子間に限流抵抗とスイッチング
要素との直列回路を接続し、高抵抗値の第1の抵抗と第
1のトランジスタの直列回路に低抵抗値の第2の抵抗と
第2のトランジスタとの直列回路を並列接続するととも
に、第1のトランジスタのコレクタを第2のトランジス
タのベースに接続し、第1の抵抗と第1のトランジスタ
の直列回路に第3、の抵抗を介して充電される第2のコ
ンデンサを接続して該コンデンサの両端電圧を第1のト
ランジスタのベース・エミッタ間に印加してコンデンサ
の両端電圧が所定レベル以上あれば第1のトランジスタ
をオンし、第2のトランジスタをオフする2端子のイン
ピーダンス切替回路とスイッチング素子との直列回路を
前記第2のダイオードブリッジの直流出力端子間に接続
し、   −前記第1のコンデンサの両端電圧を逆バイ
アス方向に印加して第1のコンデンサの充電電荷が無い
状態でスイッチング素子をオンするようにするとともに
インピーダンス切替回路とスイッチング素子との接続点
の電圧レベルが所定レベル以上あるとスイッチング要素
をオンさせる遅れスイッチにおいて、前記インピーダン
ス切替回路の第1のトランジスタのベースと第2のコン
デンサとの間に゛第3の抵抗を直列挿入して成る遅れス
イッチ。
A bidirectional power control element is interposed between the AC power source and the load, a series circuit of an operation switch and the primary winding of the current transformer is connected to both ends of the power control element, and the secondary winding of the current transformer is A first diode bridge for rectifying the secondary output is connected to the line, and a first capacitor for a time constant and a discharging circuit are connected between the DC output terminals of the first diode bridge via a charging resistor. A current limiting resistor is connected between the pair of DC output terminals of the second diode bridge so that the control current of the power control element can be turned on and off between one electrode of the power control element and the control pole. A series circuit of a first resistor and a first transistor having a high resistance value is connected in parallel with a series circuit of a second resistor and a second transistor having a low resistance value. , the collector of the first transistor is connected to the base of the second transistor, and a second capacitor charged through the third resistor is connected to the series circuit of the first resistor and the first transistor. A two-terminal impedance switching circuit that applies the voltage across the capacitor between the base and emitter of the first transistor, and turns on the first transistor and turns off the second transistor if the voltage across the capacitor exceeds a predetermined level. and a switching element connected in series between the DC output terminals of the second diode bridge, - applying a voltage across the first capacitor in a reverse bias direction so that there is no charge in the first capacitor; a delay switch that turns on the switching element when the voltage level at the connection point between the impedance switching circuit and the switching element is equal to or higher than a predetermined level; A delay switch consisting of a third resistor inserted in series between the second capacitor and the second capacitor.
JP16481482U 1982-10-30 1982-10-30 delay switch Granted JPS5969532U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16481482U JPS5969532U (en) 1982-10-30 1982-10-30 delay switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16481482U JPS5969532U (en) 1982-10-30 1982-10-30 delay switch

Publications (2)

Publication Number Publication Date
JPS5969532U true JPS5969532U (en) 1984-05-11
JPH0138995Y2 JPH0138995Y2 (en) 1989-11-21

Family

ID=30361238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16481482U Granted JPS5969532U (en) 1982-10-30 1982-10-30 delay switch

Country Status (1)

Country Link
JP (1) JPS5969532U (en)

Also Published As

Publication number Publication date
JPH0138995Y2 (en) 1989-11-21

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