JPS5968890A - Equalizing signal generating circuit in semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent mis-readout of data, by forming an equalizing signal having different timing so that each equalizing switch is operated by a delay in a sense system at data readout, allowing to attain the most effective equalizing. CONSTITUTION:Equalizing signals phie1, phie2, phie3 applied to equalizing switches Qe1, Qe2, Qe3 from equalizing drivers 5, 6, 8 and a control signal phic to an output buffer 9 are outputted with a little delay in matching with the delay of each section of the sense system. Thus, common data lines CD, CD' and a sense circuit 7 are equalized with a delay for the sense system and the equalization to each section is attained most effectively, to prevent mis-readout. Since the driver is provided at each equalizing switch, the load is decreased and the driver is reduced accordingly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an equalize signal generation circuit in a semiconductor memory device.

In a semiconductor memory device, when the level of a data line changes from a low level to a low level depending on the stored data when reading data, or from a low level to a high level, the level changes from one level to the other all at once. If this is done, the time required for the signal to change becomes longer and the reading speed becomes slower.

Therefore, conventionally, in semiconductor storage devices such as static RAM (random access memory), the read speed is improved by increasing the rising and falling speed of the level in the data line, common data line, sense amplifier, etc. Therefore, an equalization method has been proposed in which the data line or the like is adjusted to a level intermediate between the high level and low level of the signal immediately before data is read out.

However, in a semiconductor memory device to which a conventional equalization method is applied, equalization switches provided on data lines, common data lines, sense amplifiers, etc. are turned on by the same equalization signal, and equalization is performed at the same timing. was.

Therefore, in conventional equalized semiconductor memory devices, due to the signal delay up to the sense amplifier, the circuit after the sense amplifier (output buffer sofa) is There was a risk that data would be output and read incorrectly.Furthermore, in the conventional equalization method, the load on the circuit that generates the equalization signal becomes heavy, and the rise and fall of the waveform of the equalization signal becomes dull. 15, there was a problem in that a large driver circuit was required.

Therefore, the present invention provides the most effective equalization by forming equalization signals with different timings so that each equalization switch is operated with a delay corresponding to the delay in the sense system when reading data. It is an object of the present invention to prevent erroneous reading and to enable the use of a relatively small driver.

The present invention will be explained below using the drawings.

FIG. 1 shows an example of the configuration of a static RAM equipped with an equalization signal generation circuit according to the present invention.

In the figure, reference numeral 1 denotes a memory cell array in which a plurality of memory cells are arranged in an IJ sock shape. Although only one memory cell M is shown in the drawing for convenience, in reality, multiple word lines and multiple pairs of data lines are provided, and each word line W and each pair of data lines D Memory cells each consisting of a flip-flop are provided in the enclosed area.

In the memory cell M, the X decoder 2 sets one word line corresponding to the X address signals Axo to Axi to the selection level, and the is selected by turning on the Y switches Sy and Sy'.

An equalization switch M is installed between the data line and D.
An O8FET Qe+ is provided. This MOSF
ET Qe+ is the X-system address signal Ax.

It is turned on by the equalize signal I21el output from the data line equalize driver 5 which is operated in response to the signal geo from the signal generating circuit 4 which detects changes in Axi and generates pulse signals. When the equalizing switch MO8FETQe+ is turned on, the data line and b are electrically connected. Therefore, the data line and D are set to a level intermediate between the high level and the low level of the data line, regardless of the previous data.

Note that the data line D is precharged by a precharge MO8FET (not shown) when selected.

In addition, in the above data line, D is Y switch Sy, Sy'
are selectively turned on by the X decoder 3, they are connected to the common data lines CD and CD', respectively.

Between the common data lines CD and CD', there is a MO8FET switch for equalizing the common data lines.
Qe2 is provided. This MO8FETQe2 is turned on by the equalize signal φe2 of the common data line equalize driver 6 which receives the equalize signal 121e1 output from the data line equalize driver 5 and outputs it with an appropriate delay. The equalized signal ρe2 can be formed, for example, by arranging inverters that shape the waveform of the equalized signal peIf and applying an appropriate delay using the inverters. In this case, the delay amount of the equalize signal φe2 is set to match the delay time of the signal on the data line D by checking the delay time.

Reference numeral 7 denotes a sense circuit for sensing data by detecting a level difference between the data lines D connected to the common data lines CD and CD'. This sense circuit 7 consists of two stages of differential amplifiers 7a and 7b, and an equalizing switch MO8 is placed between the differential output lines of the previous stage differential amplifier 7a.
FET Qe 3 is provided. This MO8FET
QealL is turned on by the equalize signal le3 from the sense circuit equalize driver 8 which receives the equalize signal pez output from the common data line equalize driver 6 and outputs it after an appropriate delay.

Next, 9 is an output buffer 7 which receives the output from the sense circuit 7 and outputs read data.
For example, two MO8FETs Qd+ and Qd2 connected in series may be turned on and off in a complementary manner in response to differential outputs from the sense circuit 7, respectively. The output buffer 9 receives the equalization signal φe3i outputted from the sense circuit equalization driver 8, and outputs the control signal φe from the control signal generation circuit 10 after an appropriate delay.
By controlling the NOR gates G+ and G2, a signal corresponding to the output of the sense circuit 7 is supplied.

The delay amounts of the equalize signal ρe3 and the control signal φC are also set to match the delay times in the sense system (common data line and sense circuit), respectively.

As a result, from the time the word line W is driven until the output of the sense circuit is determined, the output of the gate (G+02) is made low level by the control signal pc, and the MO8FE
Both TQd+ and Qdz are turned off. Therefore, by equalizing the sense circuit 7, an intermediate level signal is supplied to the output buffer 9, and the MO8FET
A through current is prevented from flowing through Qd1 and Qd2.

In this way, in the above embodiment, each equalizing driver 5, 6, 8 and equalizing switch Qe+%Qe
Equalized signals 1e+, l' supplied to z, Qe3
The control signal gc to e2, 121e3 and the output buffer 9 is output with a slight delay corresponding to the delay of each part of the sense system, as shown in FIGS. 2(d) to 2(g).

Therefore, the common data lines CD, CD' and the sense circuit 7 are each equalized with a delay corresponding to the delay of the sense system, and equalization in each part is performed most effectively. Furthermore, since the control signal mc to the output buffer 9 is also supplied with a delay corresponding to the data delay, the output buffer 79 is operated and data is output after the output of the sense circuit 7 is determined. As a result, the output waveform of the output buffer 9 becomes as shown in FIG. be done.

Moreover, in the past, one equalization signal turned on all equalization switches and operated the output buffer, which required a considerably large driver for the signal generation circuit, but in the present invention, each equalization switch Since a driver is provided for each, the load is reduced and the driver can be made smaller accordingly. Therefore, a plurality of drivers and delay circuits are required, but overall the chip area hardly increases and the equalized waveform does not become distorted.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an example of a static RAM equipped with an equalization signal generation circuit according to the present invention, and FIG. 2 is a timing chart of signals at various parts in the circuit. D, D...number of data, CD, CD'...common data line, 7...sensing circuit, Qel-Qe3°"-equalizing switch, φe1-f13e3...equalizing signal.

Claims (1)

[Claims] 1. In a semiconductor memory device in which the data line, the common data line, and the sense amplifier each have an equalizing switch, and these switches are controlled by an appropriate equalizing signal formed based on an external signal, the above-mentioned Equalize signals are separately supplied to each of the equalize switches at appropriate timings so that the equalize switches are operated with a time difference corresponding to the signal delay in the sense system when reading data. An equalize signal generation circuit in a semiconductor memory device, characterized in that: