JPH01158692A - Static type semiconductor memory - Google Patents

Abstract

PURPOSE:To execute an inverse information reading at high speed by equalizing for reducing the level difference of the respective complementary inputs of respective amplifying means. CONSTITUTION:In the initial time of a selective access operation, the complementary signals of a first complementary data bus line pair 5, the output of an initial step sense amplifier 7, the output of a post step sense amplifier 8, a second complementary data bus line pair 5' and the output of a main amplifier 11 are set to an intermediate level between a high level and a low level. When the complementary output signal of the amplifier 11 is simultaneously set to the intermediate level, the output terminal 18 of an output buffer circuit 12 is brought into a high impedance state. During the intermediate period of the selective access operation, the amplifiers 7, 8, 11 are controlled to a high amplified gain state. Accordingly, the complementary signals of the amplifiers 7, 8, 11 and the line pair 5' are changed at high speed to obtain the output signal of the high level or the low level in the terminal 18. During the end period of the selective access operation, when an output enable control signal OE goes to the high level, the level of the intermediate period is maintained and when the signal OE goes to the low level, the high impedance state is obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a static semiconductor memory.

In particular, the present invention relates to sense circuit technology suitable for high-speed operation and low power consumption.

[Conventional technology]

Conventionally, regarding the sense circuit of static semiconductor memory, I. Nis. C.C. 86, Digest of Technical Papers (1986) No. 2
Pages 08 to 209 (ISSCC86, Digest
of Technical Papers (198
6).

pp208-209), and I-E-E.
E., Journal of Solid State Circuits, Nisshi 21, (1986) pp. 692-703 (IEEE, Journal of 5ol
id 5tate Circuits, SC-21 (
1986 Lpp 692-703).

On the other hand, the inventor of this application has set the development goals for static semiconductor memory as large storage capacity of 1 megabit or more, high-speed operation with access time of 40 nanoseconds or less, and low power consumption of 0.5 watt or less during operation. It was set to

However, in order to achieve the above-mentioned development goal, the above-mentioned conventional technology known before the application was not sufficiently improved from the viewpoint of high-speed operation and low power consumption.

[Problem to be solved by the invention]

FIG. 3 shows a static type memory studied by the present inventor before filing the application. In the figure, 1 is a memory cell, 2
3 is a word line, 3 is a column switch for selectively connecting a predetermined bit line pair (group) 4 to a first data bus line pair (group) 5, 7 is a first-stage sense amplifier, 8 is a second-stage sense amplifier, 5' is a second data bus line pair (group) for transmitting the 8 output pairs (group) to the main amplifier 11, 12 is an output buffer, 18 is a signal output terminal, and 20 is a data latch built into 12. The circuit 10 represents an equalization circuit.

In the memory shown in Figure 3, the sense amplifiers are 7°8 (groups).
Since the output is directly connected to the data bus line pair 5' (group) of the cylinder 2, the sense amplifier is operated only at the beginning of the operation cycle, and the amplified signal is latched by the latch circuit 20 in the output buffer circuit 12. There is a need. In this case, in order to avoid latching of erroneous information due to the offset of the amplifier 7.8.11, a sufficient time margin is required for latching, which poses a problem that it is not suitable for high-speed operation.

Further, no consideration is given to equalization between the complementary signals at the stage subsequent to the output of the sense amplifier 7, and it takes a long time to complete the equalization between the pair of complementary input signal lines of the first stage sense amplifier 7, which is not suitable for high-speed operation. This problem was clarified through studies by the present inventor.

The present invention was made based on the above study results of the inventor, and its purpose is to provide a large storage capacity,
An object of the present invention is to provide a static semiconductor memory that operates at high speed and has low power consumption.

[Means to solve the problem]

In order to achieve the above object, a static semiconductor memory according to the present invention includes: (1) each of a plurality of memory cells, a plurality of complementary bit line pairs, a first complementary data bus line pair, and the plurality of complementary bit line pairs; and a first switching means connected between the plurality of complementary data bus line pairs and a first amplification means responsive to complementary signals on the first complementary data bus line pair; a plurality of memory mats, each bit line pair connected to a selected group of the plurality of memory cells; (2) a second complementary data bus line pair; and (3) complementary outputs of the first amplification means. and (4) second amplification means responsive to complementary signals on the second complementary data bus lines; (5) second switching means connected between the second pair of complementary data bus lines; and third amplifying means for generating an output signal in response to the complementary outputs of the two amplifying means.

(6) first equalizing means for reducing a level difference between complementary inputs of the first amplifying means in response to a first control signal; (7) complementary inputs of the second amplifying means in response to a second control signal; (8) third equalizing means for reducing a level difference between complementary inputs of the third amplifying means in response to a third control signal; The operation of the first amplification means is controlled by a fourth control signal, the operation of the second amplification means is controlled by a fifth control signal, and the operation of the first amplification means is controlled by a fifth control signal, and An address signal is supplied to the stub-type semi-thick body memory, and in response to a change in the level of the address signal, the levels of the first, second and third control signals are changed to the levels of the first, second and third equalizing means. The levels of the first, second and third control signals are then set to values such that a level difference reduction operation is performed. The levels of the fourth and fifth control signals are set to a value such that the level difference reducing operation of the second and third equalizing means is canceled, and in response to the change in the level of the address signal, the levels of the fourth and fifth control signals are and the second amplification means is predetermined to a value such that the second amplification means operates in a high amplification gain state, and then the levels of the fourth and fifth control signals are
It is characterized in that the amplifying means is set to a value such that it operates in a low power consumption state.

[Effect]

In response to the level change of the address signal, a selective access operation of the memory cells is started. This selective access operation is executed by word line selection in the row address system and column selection in the column system by decoding the address signal after the level has changed.

This column selection is performed by the first and second switching means.

During the initial stage of this selective access operation, the first, second
Then, the level difference reducing operation of the third equalizing means is executed. As is well known, u1nc high from the memory cell)
Or 0''' (low) digital information is read out, and the level of each complementary input of the sense multi-stage amplification means is determined based on this read digital information.The current read digital information is different from the previous read digital information. In some cases, the relationship is inverted.In this case, one and the other of the complementary inputs of the sensing multistage amplification means are respectively from the "1" level to the II O7 level and from the N OI+ level to the 111 level.
Changes to If level. Part 1. The second and third equalizing means set one and the other of the complementary inputs of the sense multistage amplifying means to an intermediate level between the 111 n level and the 110 p level, so that the above-mentioned inverted information reading can be performed at high speed. can be executed.

Part 1. The sensing multistage amplification means is controlled to a high amplification gain state before the level difference reduction operation of the second and third equalization means is canceled.

When the level difference reduction operation is canceled, an intermediate period of one selective access operation begins, and the read information from the selected memory cell after the level difference reduction operation is canceled is read by the sense multi-stage amplification means in a high amplification gain state. Amplified at high speed.

Maintaining the sense multistage amplification means in a high amplification gain state after the high-speed amplification is finished is not desirable in terms of power consumption.

Furthermore, in order to reduce power consumption, it is effective to stop the operation of the sense multi-stage amplification means after the high-speed amplification ends, but in this case, the information readout output after the high-speed amplification ends disappears. Therefore, during the final stage of the selective access operation after the end of high-speed amplification, the sense multi-stage amplification means is controlled to a low power consumption state so that the information readout output by high-speed amplification is not lost and is maintained. be done.

In addition, despite the large storage capacity of more than 1 megabit,
Read information from one selected memory cell is transmitted to a first complementary data bus line pair in the mat to which the memory cell belongs, and complementary signals on the first complementary data pie line pair are amplified by a sense amplifier. After that, the signal is transmitted to the second complementary data bus line pair common to the entire semi-sensitive memory chip, thus enabling high-speed operation.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a block diagram of a static type semiconductor memory according to an embodiment of the present invention.

A 1 megabit memory cell is divided into multiple memory mats 14.
It is divided into 15, 16, and 17 parts. Memory peripheral circuits such as word line selection drive circuits and column selection drive circuits are connected to these memory mats 14, 15, 16 .
It is located between 17.

In order to constitute a static type semiconductor memory, memory cells 1 and 1' are constituted by flip-flop type memory cells. When word line 2 is selected, memory cell 1 is selected, and the read complementary signal from memory cell 1 is transferred to line 4. It is transmitted to line 4'. The complementary signals described in the present invention are equivalent to differential signals, meaning two signals such that if one of them changes to a high level, the other changes to a low level. For example, memory cell 1 has digital value u 1
If u is stored, a high level signal is read out on line 4' and a low level signal is read out on line 4. On the other hand, when word line 2' is selected, memory cell 1' is selected, and the read complementary signal of memory cell 1' is sent to line 4.
, 4'.

In this way, lines 4, 4' operate as a complementary bit line pair.

Column switch 3 operating as first switching means
The complementary signals on the complementary bit line pair 4, 4' are transmitted to the first complementary data bus line pair 5 via the complementary bit line pair 4, 4'. While the second complementary data bus line 5', which is commonly provided throughout the semiconductor memory chip, has a large parasitic capacitance, the first complementary data bus line pair 5, which is provided in one memory mat 14, has a relatively small parasitic capacitance. Has capacity. Therefore, although the signal amplitude of the read information complementary signal transmitted from the memory cell 1 to the complementary bit line pair 4, 4' is minute, the complementary signal is transmitted to the first complementary data bus line pair 5 at high speed. be done. Note that the bias circuit 6 sets the potential of the first complementary data bus line pair 5 to a predetermined level during a read operation.

A first amplification means is configured by a multi-stage connection of the first-stage sense amplifier 7 and the second-stage sense amplifier 8. The first amplifying means 7.8 performs voltage amplification in response to complementary signals on the first complementary data bus line pair 5.

An equalization circuit 10 is connected between the complementary inputs of the first-stage sense amplifier 7, and this equalization circuit 10 consists of a P-channel MOSFET with an arrow and an N-channel MOSFET without an arrow.
It is configured by parallel connection with O3FET. Also in the following description, MOSFETs with arrows are P-channel, and MOSFETs without arrows are N-channel. Similarly, the other equalization circuits 10', 10', and 10'' are P-channel MOSFET and N-channel MO3FE.
Equalize circuit 10'
are connected between the complementary inputs of the rear-stage sense amplifier 8, and the equalizer circuit 10'' is connected between the complementary outputs of the rear-stage sense amplifier 8.The equalizer circuit 10 particularly operates as a first equalizing means, The first data bus equalize signal φBE1 controls the first data bus φBE1.

φBEI is the first control signal.

The complementary output signal of the subsequent sense amplifier 8 is transmitted to the second complementary data bus line pair 5' via the transfer gate type multiplexer 9 which operates as a second switching means. Although the second complementary data bus line pair 5' has a large parasitic capacitance, the signal amplitude of the complementary output of the subsequent sense amplifier 8 is relatively large. Complementary signals are transmitted.

The main amplifier 11, which operates as a second amplifying means, performs voltage amplification in response to complementary signals on the second complementary data bus line pair 5'. An equalization circuit 14 is connected between complementary inputs of the main amplifier 11. Therefore, at least one of the equalization circuits 10'' and 14 operates as a second equalization means, and for example, the second data bus equalization signals φBE2 and φBE2 are second control signals.

The output buffer circuit 12, which operates as a third amplification means, generates an output signal 18 in response to the complementary output of the main amplifier 11. Since the complementary output of the main amplifier 11 varies between a level approximating the power supply voltage and a level approximating the ground voltage, the output buffer circuit performs voltage amplification, but its main amplification function is current amplification6. Output terminal 18
In order to increase the current driving capability in the output buffer circuit 12, the effective element area of the N-channel MOSFETs M1 and M2 constituting the push-pull output stage of the output buffer circuit 12 is equivalent to the effective element area of the MOSFETs in the memory cells 1 and 1'. It is set large. An equalization circuit 15 operating as a third equalization means is an output buffer circuit 1
The main amplifier output equalization signal φ8219'η is the third control signal.

Sense amplifier selection boost signal φS which is the fourth control signal
The first stage sense amplifier 7 and the second stage sense amplifier 8 are controlled by ^. In addition, the main amplifier 11 is controlled by the main amplifier selection boost signal φH^ which is the fifth control signal.
is controlled.

Note that the column switch 3, which operates as a first switching means, is constituted by a parallel connection of a P-channel MO3FET and an N-channel MOSFET, similarly to the transfer gate type multiplexer 9, which operates as a second switching means. Therefore, the equalization circuit to,
10', 10', 10''.

-14, 15, column switch 3, and multiplexer 9 are P-channel MOSFET and N-channel MO3F
Since the MOSFET is connected in parallel with the MOSFET, no level loss of the threshold voltage of the MOSFET occurs during the signal transmission operation or the level difference reduction operation.

Next, referring to the operation waveform diagrams in FIGS. 2(A) to (T),
The operation of the static semiconductor memory shown in FIG. 1 will be explained in more detail.

First, as shown in FIG. 2(A), a plurality of memory cells 1
．． In order to access the selected one (1) from 1', an address signal input is externally supplied to the memory chip. In response to the level change of this address signal, selective access operation of the memory cells is started. In the initial stage of this selective access operation, word line selection in the row address system is performed by decoding the address signal after the level change (see Figure 2 (B)), and column selection in the column system is performed (see Figure 2 (B)). (D), see Figure 2 (M)).

At the beginning of this selective access operation, the sense amplifier selection signal changes from low level to high level (see FIG. 2 (H)), and this high level sense amplifier selection signal is transmitted to the first stage sense amplifier 7 and the second stage sense amplifier 8. , and these sense amplifiers 7.8 are activated. Similarly, the sense amplifier selection boost signal φS^ changes from low level to high level (see FIG. 2 (I)), and this high level sense amplifier selection boost signal φS^ is applied to the first stage sense amplifier 7 and the second stage sense amplifier 8. supplied to,
These sense amplifiers 7.8 are controlled to a high amplification gain state.

Similarly, at the beginning of this selective access operation, the main amplifier activation signal is already at a high level (see FIG. 2 (P)), and this high level main amplifier activation signal is supplied to the main amplifier 11. main amplifier 11
becomes active.

On the other hand, the main amplifier selection boost signal φ changes from low level to high level (see FIG. 2 (Q)), and this high level main amplifier selection boost signal φ is supplied to the main amplifier 11, The amplifier 11 is controlled to a high amplification gain state.

Therefore, in the initial stage of this selective access operation, from the memory cell 1 to the complementary bit line pair 4°4', the column switch 3', the first complementary data bus line pair 5, the first stage sense amplifier 7, the second stage sense amplifier 8, and the multiplexer 9,
A complementary signal transmission path to the complementary output of the main amplifier 11 via the second complementary data bus line pair 5' has already been established. On the other hand, at the initial stage of this selective access operation, the first data bus equalize signals φBE1. The equalization signals such as vote a, second data bus equalization signal φBEi $spz, main amplifier output equalization signal φHe, and "l'η" are provided by the equalization circuit 10.10'.

It is set to a value such that a level difference reduction operation of 10', 10 to 14.15 is executed. Therefore, while these level difference reduction operations are being executed, FIG. 2(F), (
J), (K), (N), and (R), the first complementary data bus line pair 5, the output of the first stage sense amplifier 7, the output of the second stage sense amplifier 8, and the second complementary data bus line pair 5.
', the complementary signal output from the main amplifier 11 is set at an intermediate level between high level and low level. When the complementary output signals of the main amplifier 11 are at the intermediate level at the same time, the output transistor Ml of the output buffer circuit 12.

Since the circuit constants are set so that the gates 19 and 19' of M2 are both at ground potential, the output terminal 18 is in a high impedance state. That is, since the input thresholds of the inverters 121 and 122 of the output buffer circuit 12 are set lower than the intermediate level of the complementary outputs of the main amplifier 11, the outputs of the inverters 121 and 122 are both at a low level. Therefore, regardless of the level of the output enable control signal ○E, the NAND circuit 123
The outputs of inverters 125 and 1.26 both go to high level, and the outputs of inverters 125 and 1.26 both go to low level. Therefore, the output N-channel MO3FET M 1 .

Both M2 are turned off, and the output terminal 18 is placed in a high impedance state.

In the intermediate period of the selective access operation, as shown in FIG.
), (G), (L), and (0), the first data bus equalize signal φBIEit φBEI, the sense amplifier equalize signal φSEt stone a, and the second data bus equalize signal φBl! , $B+! 2. Equalization signals such as main amplifier output equalization signals φMB and pyp are sent to equalization circuits 10, 10', 10', and 10''.

It changes to a value that eliminates the level difference reduction operation of 14.15. On the other hand, even during this intermediate period, the first stage sense amplifier 7 and the second stage sense amplifier 8 are activated by the sense amplifier selection boost signal φS^ and the main amplifier selection boost signal φA^.
, the main amplifier 11 is controlled to a high amplification gain state. Therefore, by eliminating the level difference reduction operation, as shown in Fig. 2 (J
), (K), (N).

As shown in (R), the output of the first stage sense amplifier 7, the output of the second stage sense amplifier 8, the second complementary data bus line pair 5
', the complementary signal output from the main amplifier 11 changes at high speed in response to information read from the memory cell. When the output enable control signal OE is at a high level, MO3FETM 1 of the output buffer circuit 12 responds to the complementary output signal of the main amplifier 11.

One of M2 is turned on and the other is turned off, and a high level or low level output signal is obtained at the output terminal 18.

At the end of the selective access operation, FIG. 2(I),
As shown in (Q), sense amplifier selection boost signal φS
^, the main amplifier selection boost signals φ and ^ change from high level to low level. - On the other hand, even at this final stage, the sense amplifier selection signal and the main amplifier activation signal remain at high level, as shown in FIGS. 2(H) and (P). Therefore, the first-stage sense amplifier 7, the second-stage sense amplifier 8, and the main amplifier 11 operate in a low amplification gain state and a low power consumption state, as shown in FIGS. 2(J) and (K).

As shown in (N) and (R), the complementary signals of the output of the first-stage sense amplifier 7, the output of the second-stage sense amplifier 8, the second complementary data bus line pair 5', and the output of the main amplifier 11 are at the level of the intermediate period. hold. Therefore, when the output enable control signal OE is at a high level, the output terminal 18 of the output buffer circuit 12 maintains the level of the intermediate period. The output buffer circuit 12 is of a tri-state type, and when the output enable control signal OE is at a low level, the outputs of the inverters 125 and 126 are always at a low level, and the output terminal 18 is in a high impedance state.

Next, the internal circuit of the static type semiconductor memory shown in FIG. 1 will be explained in detail.

FIG. 4 shows a circuit diagram of an amplifier circuit used as the sense amplifier 7.8 or the main amplifier 11 in FIG.

This amplifier circuit is connected to a power supply 24 and a ground point 25,
It has complementary input terminals 20.21 and complementary output terminals 22.23. N-channel MOSFET Q s 1~QN
8 is a drive transistor whose gate responds to the complementary input signal, whose source is connected to the current source 26, 27, and whose drain provides an output signal. The P-channel MO3FETs Q P 1 to QP4 are current mirror type load transistors. The current source 26 supplies a predetermined constant current in response to the sense amplifier selection signal or the main amplifier activation signal, and the switch 28 and the current source 27 supply a large constant current in response to the sense amplifier selection boost signal or the main amplifier selection boost signal. Transfer current to N-channel MO3FETQ
Supply to NI~QN11. Since the switch 29°3o is also turned on in response to the sense amplifier selection boost signal or the main amplifier selection boost signal, this turning on causes the N-channel MO3FETs QN5 to QNa to contribute to the amplification operation of the amplifier circuit. Otherwise, switch 29,
30 is off, so N-channel MO3FETQN
g=QN8 does not contribute to the amplification operation.

Therefore, when the switches 28, 29, 30 are on, this amplifier circuit operates in a high amplification gain state, and the switches 28, 29, 30 are on.
When 9.30 is off, this amplifier circuit operates in a low amplification gain state and a low power consumption state.

FIG. 5 shows an embodiment in which the amplifier circuit of FIG. 4 is partially modified. That is, the current source 26 in FIG. 4 is N in FIG.
Changed to channel MOSFET QN1s,
Switch 28 and current source 27 in FIG. 4 are changed to N-channel MOSFET QN14 in FIG. 5, and switches 29 and 30 in FIG.
It has been changed from QN9 to QNix. Therefore, in FIG. 5, the control input terminal 29 is supplied with the sense amplifier selection signal or the main amplifier selection signal, and the control input terminal 30 is supplied with the sense amplifier selection boost signal or the main amplifier selection boost signal.

FIG. 6 shows an embodiment in which the amplifier circuit of FIG. 5 is further partially modified. The difference from the embodiment shown in FIG. 5 is that the terminal 31
P-channel MOSFE in response to a select boost signal of
A current path is formed from TQps to Qpzz to further adjust the gain and output level.

Note that in the embodiments shown in FIGS. 4, 5, and 6, circuits in which the P-channel MO8 is the load and the N-channel MO8 is the driver are described as examples, but similar amplifier circuits can be implemented even with the reverse circuit configuration. Of course it can be achieved.

FIG. 7 is a circuit diagram for explaining in more detail a part of the output buffer circuit 12 of FIG. 1, and is characterized in that signal transmission paths between outputs are connected. This waveform change control circuit 13 is a P-channel MOSFET Q p zo
and N-channel MO3FET QNzo, Qp
The gate, source, and drain of zo are connected to the input of CMOS inverter 126, the positive power supply 24, and the drain of QNzo, respectively, and the gate and source of QN20 are connected to the positive power supply 24 and the output of CMOS inverter 126, respectively. The gate of the output N-channel MO3FETM 2 is driven by the output of the CMOS inverter 126 and the output of the waveform change control circuit 13.

FIG. 8 shows the operating waveforms of each part in the circuit of FIG. The case where the change control circuit 13 is connected is shown.

First, a case where the waveform change control circuit 13 is omitted will be described. The input signal of CMOS inverter 126 is
As shown in Figure (A), when the input signal changes from high level to low level, C
The output signal of the MOS inverter 126 changes from low level to high level at high speed as shown in FIG. 8(B).

Then, the drain voltage of the output N-channel MO3FETM 2 changes from high level to low level as shown in FIG. 8(C). The output terminal 18 of the output buffer circuit 12 of the static semiconductor memory normally has a number of 10 to 1
A parasitic load capacitance of 00 pF is equivalently connected to the output buffer circuit 12.
Through the output of the N channel/L/MO3FETM L, it is charged to about 5 volts of positive +71 volts and rA24. On the other hand, in order to increase the current drive at the output terminal 18, the output buffer circuit 12 has both N-channel MO3FE
The effective element areas of TM 1 and M 2 are set to be considerably large. As shown by the broken line in Figure 8(B), the CMOS
When the output signal of the inverter 126 changes rapidly from a low level to a high level, the N-channel MO3FETM 2 exhibits an excessive peak value during the discharge of the parasitic load capacitor to the ground potential point, as shown in FIG. 8(D). A transient current flows.

When this transient current with an excessive peak value flows through the ground line, transient noise is generated in the ground line, which results in malfunction of other circuits, and it takes a long time to recover.

In order to avoid this problem, the waveform change control circuit 13 is placed in the output buffer circuit m12.

Therefore, before time t1, the input signal to the CMOS inverter 126 is lower than the power supply voltage of the power supply 24 to the P-channel MOSFET.
When ET Q p to falls below the threshold voltage,
At time tz, MOSFETs Qpzo and QNzo start to conduct, causing the output signal of CMOS inverter 126 to rise as shown in FIG. 8(B). CMOS inverter 1
26 output signal rises from the power supply voltage
When a voltage lower than the threshold voltage of the 3FET Qszo is reached, the N-channel MOSFET Qszo is cut off, so the rise in the output signal of the CMOS inverter 126 is determined by the inverter operation of the CMOS inverter 126 itself.

By adding the waveform change control circuit 13 to the CMOS inverter 126 in this way, the CMOS inverter 12
The change of the output signal No. 6 from low level to high level occurs over a long period of time from time t2 to time t8. Therefore, the peak value of the transient current flowing through the N-channel MO3FETM 2 can be reduced as shown by the solid line in FIG. 8(D).

According to the embodiment described above, a 1 megabit static semiconductor memory with 4-bit parallel output is fabricated using a 0.8 micron rule CMOS process, has a high-speed operation with a typical access time of 15 nanoseconds, and operates at 20 MHz. We were able to achieve low power consumption of 250 milliwatts.

〔Effect of the invention〕

According to the invention, a first amplification means and a second amplification means.

Since equalization is performed to reduce the level difference of each complementary input of the third amplifying means, the complementary bit line pair, the first switching means, the first complementary data bus line pair, the first amplifying means, and the second switching means.

Even if there is a slight offset or unbalance in the second complementary data bus line pair and the second amplifying means, the inverted information can be read out at high speed by setting an intermediate level by equalization.

Further, the read information from one selected memory cell is transmitted to the first amplifying means controlled to a high amplification gain state and the second amplifying means controlled to a high amplification gain state.
Since the signal is amplified by the amplification means, high-speed sense amplification is possible. On the other hand, after that, the first amplification means and the second amplification means are controlled to a low amplification gain state in which the information readout output by high-speed sense amplification is maintained without being lost, thereby realizing low power consumption. be able to.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of a static type semi-quadram memory according to an embodiment of the present invention, and FIGS. 2(A) to (T) show operations for explaining the operation of the static type semiconductor memory of FIG. 1. FIG. 3 shows a block diagram of a static type semiconductor memory studied by the inventor before filing the application, and FIGS. A circuit diagram of an amplifier circuit used as an amplifier is shown, and FIG. 7 is a circuit diagram for explaining in detail a part of the output buffer circuit in the embodiment of FIG.
8(A) to 8(D) show operating waveforms of each part in the circuit of FIG. 7. Fig. 2<A)-'1)l-"u space input (B) Select 1 shaku word (0) Bi, J1 Hajime -----------1+De:=:== ＝：＝＝＝、：（・Please read 3 tl---------
'----3rd country Figure 7 Figure 8

Claims (1)

[Claims] 1. A static semiconductor memory comprising: (1) a plurality of memory cells, a plurality of complementary bit line pairs, a first complementary data bus line pair, and the plurality of complementary bit line pairs. and a first switching means connected between the plurality of complementary data bus line pairs and a first amplification means responsive to complementary signals on the first complementary data bus line pair; a plurality of memory mats, each bit line pair connected to a selected group of the plurality of memory cells; (2) a second complementary data bus line pair; and (3) complementary outputs of the first amplification means. and (4) second amplification means responsive to complementary signals on the second complementary data bus lines; (5) second switching means connected between the second pair of complementary data bus lines; (6) a third amplifying means for generating an output signal in response to the complementary outputs of the two amplifying means; and (6) a first equalizing means for reducing a level difference between the complementary inputs of the first amplifying means in response to the first control signal. (7) second equalizing means for reducing a level difference between complementary inputs of the second amplifying means in response to a second control signal; (8) second equalizing means for reducing a level difference between complementary inputs of the second amplifying means in response to a third control signal; and third equalizing means for reducing a level difference between complementary inputs, the operation of the first amplifying means is controlled by a fourth control signal, and the operation of the second amplifying means is controlled by a fifth control signal. , an address signal is supplied to the static semiconductor memory in order to access one memory cell selected from the plurality of memory cells, and the first, second and third memory cells are connected in response to a change in the level of the address signal. The level of the third control signal is set to a value such that the level difference reduction operation of the first, second and third equalizing means is performed, and then the level of the first, second and third control signal is set to the level of the first, second and third equalizing means. , the levels of the fourth and fifth control signals are set to values such that the level difference reduction operations of the second and third equalizing means are canceled, and in response to the change in the level of the address signal, the levels of the fourth and fifth control signals are The levels of the fourth and fifth control signals are set to values such that the first and second amplification means operate in a high amplification gain state, and the levels of the fourth and fifth control signals are then set to values such that the first and second amplification means operate in a low power consumption state. A static semiconductor memory characterized by being set to . 2. The static semiconductor memory according to claim 1, wherein when the first and second amplifying means operate in a low power consumption state, the first and second amplifying means operate in a high amplification gain state. A static semiconductor memory characterized in that the levels of the fourth and fifth control signals are set so that information read by the controller is retained without being lost. 3. The static semiconductor memory according to claim 2, wherein after the level difference reduction operations of the first, second, and third equalizing means are canceled, the operations of the first and second amplifying means are stopped. A static semiconductor memory characterized in that it can be switched from a high amplification gain state to the low power consumption state. 4. A static semiconductor memory comprising: (1) each of a plurality of memory cells; (2) a sense amplifier for amplifying read information from a selected one of the plurality of memory cells; 3) an output buffer circuit that generates an output signal at an output terminal in response to a complementary output signal of the sense amplifier, and the output buffer circuit includes: (a) one of the complementary output signals has an input thereto; (b) an output transistor whose output current path is connected between the output terminal and a first operating potential point and whose control input is responsive to the output of the inverter; (c) whose input is responsive to the output of the inverter; a waveform change control circuit connected to the input of the inverter, the output of which is connected to the output of the inverter, the waveform change control circuit having a gate connected to the input of the inverter; A P-channel MOSFET whose source is connected to the second operating potential point and whose drain is connected to the second operating potential point.
an N-channel MOSFET connected to the drain of the channel MOSFET, its gate connected to the second operating potential point, and its source connected to the output of the inverter;
1. A static semiconductor memory characterized by having T. 5. The static type semiconductor memory according to claim 4, wherein the inverter is constituted by a CMOS inverter, and the output transistor is constituted by a MOSFET.