JPS5967877A - Current limiting system for inverter - Google Patents

Abstract

PURPOSE:To reduce the fluctuation of a current by flowing a load current during an overcurrent detection signal generating period through a circulating circuit formed of the variable control semiconductor switch and a diode, thereby limiting the overcurrent in good responsiveness. CONSTITUTION:A power source has an input filter 1, a DC/DC converter 2, an intermediate filter 3, an inverter 4 and an output filter 5. The inverter DC input voltage is detected by a voltage detector 21, and the converter 2 is controlled on the basis of the output. When the overcurrent is detected by a current detector 28, a load current is flowed through a circulating circuit formed of transistors U-Z of the inverter 4 and a diode, thereby stopping the rise of the load current.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an overcurrent limiting scheme for an inverter with a control circuit consisting of a three-phase bridge of controllable semiconductor switches each having a diode in antiparallel and without pulse width control function.

For example, when an auxiliary power supply device that supplies power to a railway vehicle's cooling system is configured with an inverter, the widely fluctuating power supply voltage received from the overhead wire via a current collector is stabilized to an appropriate level by a DC-DC converter. The reason for converting the DC intermediate circuit voltage to the DC intermediate circuit voltage and then using it as the inverter DC input voltage is that stable operation of the inverter is not only ensured, but also that the withstand voltage margin of the semiconductor elements that make up the inverter is small. preferable. In this case, even if the control circuit for each controllable semiconductor switch in the inverter does not have a pulse width control function, the inverter AC output voltage can be increased by controlling the inverter DC input voltage by the DC-DC converter. can be maintained at a desired value.

By the way, in the above-mentioned auxiliary power supply device, an inrush current is generated when various electrical devices such as lighting equipment come into contact with the auxiliary power supply device in addition to the cooling device. Therefore, in the case of a distributed power supply system in which one inverter is installed in each train, conventionally the inverter has a current capacity that can tolerate the starting current, making the device large and expensive. was. In order to avoid increasing the size of the inverter, it is necessary to limit the current of the inverter. In the case of an inverter control circuit that does not have a pulse width control function, in order to limit the inverter current, the DC input voltage of the inverter may be lowered by reducing the current flow rate of the DC/DC converter. However, since an intermediate filter is provided between the DC-DC converter and the inverter for voltage smoothing, even if the response speed of the current limiting loop is sufficient against overcurrents that rise slowly, The current limit loop cannot respond immediately to an overcurrent that rises.

Therefore, it is conceivable to use pulse-off of all controllable semiconductor switches in conjunction with the same treatment as overcurrent protection in the event of a load short-circuit accident. However, in this case, the load current after the pulse-off flows back to the DC input side of the inverter via the diode installed in parallel with the controllable semiconductor switch, so the current attenuation is fast, but the voltage reduction operation of the current limit loop On the other hand, the reversely flowing load current has the effect of charging the smoothing capacitor of the inverter DC input circuit and increasing the voltage. For this reason, the gradual current limiting action of the current limiting loop does not work effectively, and the switching operation between the normal inverter control state and the pulse-off state is frequently repeated, causing severe fluctuations in the load current. This prevents the drive machine from starting smoothly, making it impossible to start or requiring a long time to start, resulting in an unacceptable negative impact on other loads.

An object of the present invention is to not only limit overcurrent with good responsiveness, but also to enable smooth current limiting with little current fluctuation.

This object is achieved according to the invention by the features described in the claims. According to this configuration, during the generation period of the overcurrent detection signal, the load current flows through the circulation path formed by the controllable semiconductor switch and the diode of the inverter, so that it does not flow back to the DC input side of the inverter.

The free circulation operation is temporarily canceled when the control signal of any of the controllable semiconductor switches is reversed, but if the overcurrent detection signal continues, the new circulation operation is immediately resumed.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

1 to 3 show an embodiment in which the overcurrent limiting method according to the present invention is applied to a vehicle auxiliary power supply device, FIG. 1 shows an example of the configuration of the main circuit portion, and FIG. 2 shows a configuration example of the control device portion. A configuration example is shown, and FIG. 3 shows a detailed embodiment of the main parts of the control device shown in FIG. 2.

The vehicle auxiliary power supply device shown in FIG. 1 includes an input filter 1. DC-DC converter device 2, intermediate filter 3
, an inverter 4, and an output filter 5. The inverter 4 consists of six controllable semiconductor switches U each having a diode in anti-parallel.

A transistor is used here as each controllable semiconductor switch in the three-phase bridge of v, w, x, y, and z. The DC-DC converter 2 cooperates with the input filter 1 and the intermediate filter 3 to convert a fluctuating DC high voltage received from an overhead line via a current collector into a voltage value suitable as the DC input voltage of the inverter 4. Convert to a stabilized intermediate circuit voltage with. The DC-DC converter device 2 is also composed of transistors, but since there is a limit to the withstand voltage of the transistors, it is composed of a plurality of unit converters connected in series with each other on the input side and connected in parallel with each other on the output side. .

Here, a case is shown in which the system is configured with two unit converters. The two unit converters are constructed as known ringing choke converters, each consisting of a transistor Q or Q2, a transformer T or T2, and a blocking diode D or D2. Input filter 1 includes smoothing reactor L1 and smoothing capacitor C1
,C,. Two smoothing capacitors C, , C2 which are divided into two parts of the input filter 1 and connected in series with each other.
Since the common connection point of both unit converters and the unit converter input side common connection point are connected, it serves as a voltage dividing capacitor for balancing the input voltage sharing between both unit converters. Transistor Q of both unit converters,
, Q2 are controlled according to the same on/off command.

An output filter 5 provided on the inverter 4 serves to sinusoidize the voltage supplied to a load (not shown). In this case, because of the small size of the output filter 5, the inverter 4 is preferably pulse width modulated.

The inverter DC input voltage is detected by a voltage detector 21. The voltage actual value signal Vd detected by this voltage detector 21 is input to a voltage regulator 22 shown in FIG. The voltage regulator 22 compares the voltage actual value signal d with the voltage target value signal 2 from the voltage setting device 23, forms a conduction rate command signal according to the voltage control deviation obtained as a result of the comparison, and controls the conduction. is applied to the rate control circuit 24. Conductivity control circuit 24
controls on/off both transistors Q, , Q2 in the DC-DC converter device 2 according to the duty ratio command signal.

Further, an inverter output current detector 25 is provided on the output side of the inverter 4. Although not shown in detail, the inverter output current detector 25 includes a rectifier circuit, converts the AC detection signal into a DC signal, and supplies this to the current regulator 26 shown in FIG. 2 as the actual current 11M value signal Ia.

When the current actual value signal 8 exceeds the current limit setting signal l'' from the current limit value setting device 27, the current regulator 26 acts on the output limiting circuit of the voltage regulator 22 to lower the current conduction rate of the converter. This causes the inverter output current to remain within the limit value.

The voltage actual value signal Vd is guided as an inverter output frequency command signal to the voltage/frequency converter 41, where it is converted into a pulse with a frequency proportional to the signal, and then input to the inverter control circuit 42. The three control signals u, v, w generated by the inverter control circuit 42 are transmitted as control signals to the transistors U, V, W on one DC input terminal side in the inverter 4, and are also transmitted to the inverter 53, respectively.
1 to 533 and transmitted as control signals for the transistors X, Y, and Z on the other DC terminal side. In this case, the control circuit 42 controls two transistors U and X, ■ and Y, which belong to the same output terminal as described above.
W and Z are controlled on and off in an inverse relationship to each other, and on each DC input terminal side, a state in which an ON command is given to two transistors and a state in which an OFF command is given to only one transistor occurs alternately. to control individual transistors. The simplest example of such a control circuit 42 is a pulse distribution circuit in which the three control signals each have a pulse width of 180° and a phase difference of 120° from each other. However, the output filter 5
In order to reduce the size of the device, it is preferable to configure the control circuit to perform predetermined pulse width modulation to remove low-order harmonics below a predetermined order. FIG. 6 shows pulse width modulation control signals u, V, which do not contain harmonics below the 19th order.
An example of the waveform of W is shown. In this case, there is no need for a pulse width (angle) control function, and a fixed pulse width data is sufficient.

The current limiting loop by the current regulator 26 described above throttles the current flow rate of the converter to lower the inverter DC input voltage when the inverter output current (2) exceeds the limit value Any. As the inverter DC input voltage decreases, the inverter output frequency is lowered, thereby keeping the ratio between the inverter output voltage and the inverter output frequency constant. Therefore, even when current limiting is applied to avoid large inrush currents that occur when an induction motor of a cooling system is directly started, the ratio between the motor's primary side pressure and its frequency can be maintained constant. This allows a constant driving torque to be ensured. However, because of the presence of the intermediate filter 3 made of the smoothing capacitor C, the inverter DC input voltage is not instantaneously reduced even if the converter current flow rate is reduced.

FIG. 4 shows the time course of the inverter direct current human power torque V4 during and before and after starting up the electric motor. As described above, since the current limiting loop by the current regulator 26 has a response delay, an excessive current flows through the inverter during the period T until the inverter DC input voltage drops to the value 1.

In order to prevent this, according to the present invention, the current detection signal of the current detector 28 provided on the DC side of the inverter is led to the comparator 44 and compared with the setting signal 5 of the setting device 45, and the detected value When Id exceeds the set value 5, an overcurrent detection signal a is generated, and this overcurrent detection signal is sent to the control circuit 4.
The signal is transmitted to the logic circuit 43 inserted before the inverting stages 531 to 533 on the output side of No. 2. This logic circuit 43
A specific example is shown in FIG.

In FIG. 3, u, v, and w are three-phase control signals derived from the control circuit 42 of FIG. 2, and as already mentioned, these are pulse width modulated signals as shown in FIG. 6, for example. . 501 to 502 are monostable circuits that generate a "1" signal for a certain period of time at the rising and falling points of the modulation signals u, v, and w, respectively. Each monostable circuit 501 to 503
can each consist of two monostable elements and one negation element. That is, an input signal is applied directly to one monostable element, and an input signal is applied to the other monostable element via a negation element, and the outputs of both monostable elements are OR-combined. The output signals of the monostable circuits 501-503 are led to set input terminals S of three RS flip-flops 511-513 via an OR gate 504. Modulation signals u, V, and w are provided by EXOR gates 521 and 52, respectively.
2,523, and the other input terminals of these EXOR gates are connected to the output terminals Q of the flip 70 tubes 511, 512, and 513, respectively.
It is connected to the. These EXOR gates 521-5
Inverting circuits 531 to 53 provided on the output side of 23
3 is already shown in FIG.

Reset input terminals R of RS flip-flops 511-513 are connected to output terminals of AND gates 561-563, respectively. One input terminal of AND gates 561-563 is connected to the output terminal of comparator 44 in FIG. The other input terminals of AND gates 561-563 are connected to the output terminals of EXOR gates 541-543, respectively, via negation circuits 551-553, respectively. The two input terminals of the EXOR gate 541 receive modulation signals u and w, respectively, and the two input terminals of the EXOR gate 542
The two input terminals receive modulation signals w and u, respectively, and EXOR
Modulation signals u and v are introduced to two input terminals of gate 543.

When the overcurrent detection signal is not generated, that is, when the output signal a of the comparator 44 in FIG. , flip-flop 5
Since EXOR gates 11 to 513 are not reset, the signal at the output terminal Q connected to one input terminal of EXOR gates 521 to 523 is kept at "o". Therefore, the output signals of EXOR gates 521 to 523 match the modulation signals u and v2w, respectively. Therefore, the transistor U belonging to the negative side DC input terminal of the inverter 4
, V, W base signals (!) are respectively transmitted with modulation signals u, v, w, and base signals of transistors X, Y, Z belonging to the positive side DC output terminal of the inverter 4 are respectively The modulated signals u, v, w are inverted by the negative circuits 531 to 533 and then transmitted. FIG. 7 shows the modulated signal u for the period A shown in FIG.
, v, w are shown enlarged, and the transistors U, V
, W as well as the output signal a of the comparator 44. From this, it can be seen that when the signal a is not in the state of 1'', which means an overcurrent detection state, the modulation signals U to V are transmitted as they are as the base signals of the transistors U to Z.

For the modulation signals u, v, and w, only U is “1” [mode I], only W is “0” [mode ■], and only ■ is “1#”
For U mode], only U is 'O' [Mode IV], only W is 1'' [Mode ■], and only U is '0'' [Mode ■].

In Fig. 7, the signal a indicates the overcurrent detection state at two locations "1".
'' signal. Immediately before the first overcurrent detection signal is issued, the modulation signal U.

For v and w, only U is at 1'', so mode ■
is in a state of In this mode (2), the transistors of the inverter 4 are U as shown in FIG. 5A.

An ON command is given to Y and Z, and current flows in the direction of the arrow shown. In this mode (2), only the output signal of the NOT circuit 551 among the three NOT circuits 551 to 553 becomes II II II. Therefore, as soon as the signal a changes from "0" to "1", the AND gate 561 resets the 7-lip-flop 511, and the signal at the output terminal Q is inverted from "0" to "1". Accordingly, the output signal of the EXoR gate 521 changes from 1'' to II.
Flip to On. That is, as can be seen from FIG. 7, the transistor U is given an OFF command at an inopportune time. Instead, an on command is given to the transistor X, and as shown in FIG. 5B, an operating state is established in which the load current circulates without passing through the DC input circuit. This cuts off the energy supply from the DC input circuit to the load, and prevents the current from increasing from the set level 5. This setting level
5 is the setting level for average value current limit■ 5 is set higher than 2, and the average value current limit is not in time and the current exceeds the set level 5.
The current rise is instantaneously blocked as soon as it exceeds the current limit.

This blocking of the current increase due to the circulation operation is continued in the trench when a change occurs in any of the modulation signals u, v, and w. Here, when the modulation signal W is inverted from '0' to '1', the signal at the output terminal Q is changed by the '1' signal input from the monostable circuit 503 to the set terminal S of the flip-flop 511 via the OR gate 504. is °゛0 again
”, transistor U.

In response to the command of the modulation signal U at this time, X is turned on,
X is turned off. Therefore, now the transistor U
, 'W, Z are given an ON command and the operation mode is set■
Move to. At this time, since the overcurrent detection signal has already disappeared, the transition to the free circulation mode is not performed. If the overcurrent detection signal still persists, in this mode ■, the flip-flop 512 is reset, transistor ■ is turned on, and transistor Y is turned off, so that When U, V, and W are on, the circulation mode is activated. Regarding the operation when the overcurrent detection signal continues for a relatively long time, please refer to the difference between the modulation signal uw and the base signals U to Z in the second "1" state transition period of the signal a in FIG.

As a result, the EXOR gates 541 to 543 and the inverting circuits 551 to 553 are connected to the transistors to which only one on-command is given at each DC input terminal side from the control signals uw, that is, the DC human power current. This constitutes means for determining which transistors are flowing the same current. AND gates 561-563, flip-flops 511-513 and EXOR gate 52
1 to 523 turn on/off the transistor determined by the means and the transistors belonging to the same AC output terminal from when the overcurrent detection signal is issued until the next change in any of the control signals. It constitutes means for maintaining the command in an inverted relationship with respect to the command according to the regular control signal.

By adding such means to the impark control circuit according to the present invention, it is possible to centrifugally prevent the load current from increasing and prevent the inverter current from exceeding the overcurrent limit level. In addition, compared to the -simultaneous pulse-off method, there is no rise in DC voltage due to reverse current to the DC input side of the inverter, so there is no negative effect when using an average current limiting loop. Also, no current fluctuation occurs. Therefore, the present invention is very effective when applied to overcurrent limiting of an inverter used in a vehicle auxiliary power supply device that has an AC motor that is directly started as a load.

[Brief explanation of drawings]

FIG. 1 is a circuit connection diagram showing the main circuit section of an embodiment of the present invention;
Fig. 2 is a block diagram showing the control device part of one embodiment of the present invention, Fig. 3 is a block diagram showing a detailed configuration example of the main part in Fig. 5A and 5B are circuit diagrams for explaining the overcurrent limiting operation according to the present invention, and FIG. 6 is an example of a control signal. A time chart showing
Figure 7 shows one dog □ for period A shown in Figure 6. 3 is a time chart showing an example of the progression of a control signal and a transistor base signal. DESCRIPTION OF SYMBOLS 1... Input filter, 2... DC-DC converter device, 3... Intermediate filter, 4... Inverter, 5
... Output filter, 21 ... Inverter DC input voltage detector, 22 ... Voltage regulator, 23 ... Voltage setting device, 24 ... Duty ratio control circuit, 25 ... Inverter output current Detector, 26... Current regulator, 27... Current limit value setter, 28... Inverter input current detector, 41... Voltage/frequency converter, 42... Control circuit, 43. ...Logic circuit, 44...Comparator, 45...
Overcurrent limit level setter, 501-503... Monostable circuit, 504... OR gate, 511-513 ・
...RS flip-flop, 521~523,541~
543...EXOR gate, 531-533, 55
1 to 553... Inverting circuit, u-w... Control signal (modulation signal), U-Z... l transistor (or its base signal). Sai 3 Figure O 4 Figure

Claims (1)

[Claims] l) Consisting of a three-phase bridge of controllable semiconductor switches each having a diode in antiparallel, when one of the two controllable semiconductor switches belonging to the same AC output terminal is given an OFF command, the other is given an ON command. is,
In addition, on each DC input terminal side, the controllable semiconductor switches are turned on and off so that a state in which an on command is given to two controllable semiconductor switches and a state in which an on command is given to only one controllable semiconductor switch occur alternately. In an industrial computer equipped with a control circuit that generates a control signal that gives a command, there is a controllable semiconductor switch in which only one turn-on command is given to any DC input terminal from the control signal of the controllable semiconductor switch. a first means for determining a semiconductor switch; and a first means for determining a semiconductor switch; and a first means for identifying a semiconductor switch; A second means is provided for controlling the controllable semiconductor switch determined by the means and the controllable semiconductor switch belonging to the same AC output terminal with a signal obtained by inverting the regular control signal. Current limiting method for inverter.