JPS5967740A - Code error compensating device - Google Patents

Abstract

PURPOSE:To attain a stable operation, even if a titled device is incorporated in a large-scale integrated circuit, by eliminating the delay between shift pulses so that a gate circuit is eliminated from a clock line. CONSTITUTION:Shift register circuits 11, 12, 13, 15 and 18 consist of L3, R2, L2, R1, and L1 and the outputs are denoted as l3, r2, l2, r1 and l1. For example, if the L3 is correct and the L2 is wrong, an error discriminating circuit 21 gives a signal so that a selector circuit 19 selects and outputs the output l3, a selector circuit 14 gives a signal so as to select outputs l3+l1, a shift register circuit 15 receives the content of l3+l1 and it is outputted in parallel. A signal is given from a discriminating circuit 21 so that a selector circuit outputs its parallel output so as to be outputted with a shift by one bit to the LSB side. Thus, an output of (l3+l1)/2 is latched in a latch circuit 17 and it is an output of the compensator.

Description

Detailed Description of the Invention Industrial Field of Application The present invention t-1, e.g. d, Digitalized audio signal transmission in digital audio production Ten code error sleeves I
There are 1"eζ1 series in one device.

dl, any t]￥FJ4 riga in the audio signal transmission of the digital au r'io! Even if you say sled, j11F
I do.

-1: , F
IT student/Ffl Hibiki Shinkyu makes a 4-1 sound that feels like a 1st sound, and it's a 1st that doesn't exist. For this reason, the scoop is compensated for errors.

= 1rJ1 with the digitized signal of the general Kokyo Isho,
Because of the continuous line (', '1'' value between 3 points and the quality of 1/1, such as the strong Honshu line), the Kinuta of a certain Sakuraji Mokugyo may be missing, or the MfI may be missing.゛[′
Unicorn candy'? Use r, or Q'1, f) fll's (
1 "Complement the value of Mokugyo by its '-1 Knee 1 Ho 4'-)" FT &:I is valid and commonly used -7+ +5'J is average value interpolation, the latter The structure of seven conventional examples in which the previous value is held and the problems thereof Below, an example of a conventional code error compensator will be described with reference to FIG. 1 (l-j, Onosenotobina 1,1
The first Zogital Shinkyu shown by fi-FT) Nbisoto (hereinafter referred to as L
Shift register circuit which inputs serially from SB), 2 is the shift register circuit 1.7)/shift register circuit which takes the output as input, 3d, shift register circuit 2
A selector circuit selects the output of the adder 5 and the output of the adder 5, 4 is a shift register circuit whose input is the output of the selector ji':il path 5, and 6 is a 1-/ft register. Select the output of circuit 1 and the output of 7-foot register circuit 4 1. 5 is an adder that completely adds the output of the selector circuit 6 and the output of the -1- mark / throat register circuit 4; 7 is a /ft register circuit 1. 1TE of digital signals stored in shift register circuit 2
8. 8. Outputs a signal to switch the outputs of the two selector circuits 3 and 6. 1, 8 is an error judgment circuit that generates a pulse that shifts the digital E signal by 1 bit in order to increase the addition result by 1/, -. Input the soft clock pulse that outputs the contents of .3 and the pulse that outputs the 1 bit extra bit output from circuit 7 and [7. be.

The conventional t! configured as shown in 1- below. J-Z error correction (1 device Z-(, its operation will be explained below. Here,
For the convenience of explanation 1, in ft register #l, 2.4, the contents of ``jbo et ir'' are respectively A, B, C, ::,
7, -'), and their outputs as Iq-a, b, and c, respectively.
(!l: Do.

Now, when the content B is 11, the error judgment circuit 7 sends a signal so that the selector circuit 3 selects b, and the content of t;1], b enters the 7 note register circuit 4. 1 is output in parallel, content B is incorrect, content A
F11-[, if, error Ull>? l+il
K 7 iJ', -L l/ Lid circuit 6 selects d, IR output 2, further V (selector circuit 3 adds 'r'):
't! :'r I don't trust the output arc of 5 as I usually do. At this time, the extra shift pulse is detected by the error judgment circuit 7.
For games, circuit 4 &'('l is added to the content C of /ft register circuit 4, and j is shifted to the LsB side by 1 bit. and f'i t゛17 uniform f1/1 somoma is performed. Also, if both contents A and B are 11!'i-cC, then the error judgment circuit 7 selects C and outputs the selector circuit 6. Then, the selector circuit 3 selects the output CTC of the adder 6 u-1
Give a signal to force. At this time, an extra shift pulse is added from the error judgment circuit 7 to the OR gate circuit 4 l') i
%, the contents C of the shift register circuit 4 are toggled, and (C
-C)7/'2=C, and pre-holding is performed.

However, this conventional device U: When configured with 11-scale integrated circuits such as normal TTL, it operates without problems, but when large-scale integrated circuits are included for further integration, The OR gate circuit 8 is included in the taro clock line of the shift register circuit 1.2.4/-1 There is a possibility that uJ' may malfunction due to the delay of the crossin there, and it is said that the system lacks stability. J4]. To explain this in detail, in general, the OR gate circuit 8 causes the force on the shift register circuit 4 side to lag behind the noft pulse Q': shift register circuit 4 side by 7 feet [/raster 11) j path 2 side. If there is no ;l"N t'l, the mouth, the pig is
As shown in b), it moves normally within the sifrugister, but
ft register 41III 4Q)/ftbalus is iI
? When the shift register circuits 2 and 4 are rll, due to the phase difference between the first /ft pulse, the Before latching the data, the /shift register circuit 2 outputs the following data:
) There was a problem in that the first bit of the data in the 7-foot register 1 route 2 was received without being received. In addition, the 21st
jXi(a) shows the hidden data (77 foot clocks and sending data).

OBJECTS OF THE INVENTION The present invention solves the problems of l:; (1) The system of the present invention with 11 components゛The first noft register 1i-1 to which 7 real inputs of 1 digital signal are input, and its first shift 1
A second shift resistor circuit inputs the output of the / register lr, l path, a third 77 register circuit that outputs the output of the second soft register circuit, and an output of the third 7 register circuit. a first selector circuit that selects and outputs the output of the pit full adder; a fourth shift register circuit that receives the output of the first selector circuit;
A second selector circuit selects either the parallel output of the fourth soft register circuit or the output obtained by shifting the parallel output by one bit to the least significant bit side and outputs the parallel fj:f; a latch circuit that latches the parallel output of the second selector circuit; a sixth shift register circuit that uses the parallel output of the latch circuit as a parallel input; and the seventh real output of the sixth shift register circuit and the first knot. The third selector 1m selects and outputs either one of the serial outputs of the register circuit, and the correctness of the digital signals stored in the first and third register circuits determines whether the first... ;lr! 2.
Error in controlling the output of the third selector circuit 'I! Il constant circuit, and the whole egg leopard circuit←41, the third
The output of the selector circuit and the output of the fifth /ft register circuit are completely added together.

Explanation of Examples Below A(?; Bright Example will be explained with reference to Figure 3.
This is a case where the digital number 43 of the channel channel is sent serially alternately (r, In Figure 3, 11 is a shift register circuit where the digital signal in offset binary display is input to 7 rear A, and 12 is a note not register. a soft register circuit that receives the output of the circuit 11; 13;
*rI:Mr: Shifu t-shi) star lr-i1M, 1
4. A selector circuit that selects and outputs the output of the adder 20 and the output of the shift register circuit 13 in the rear and l ho, 1
5f, I input the output of the selector circuit 14, input the output of the register/store register l111, 16r, I, the parallel output of the soft register circuit 16 manually, and input the output as follows:
17 is a latch circuit that latches the parallel output of the selector circuit 16; 18t/;l; 7' shift register circuit that inputs the output of the latch circuit 17 in parallel;
21 i, J
, the correctness or incorrectness of the I/U stored in the shift I/J registers 11, 12, 13, and the above-mentioned three selector circuits 14, 1, etc.

This is an error determination circuit that outputs a signal for switching the output of No. 19.

Next, the operation of this embodiment will be explained. For convenience of explanation -
'2, Soft register circuit 11, 12, 13゜1 et al., 1
The internal milk stored in 8 is transferred to the 3rd degree R2 and the second
, R1, Ll, and the output of Sowa, et al. is Le3.
+ ”21 G t rll 61 and 'nor 0
Now, when the second one is available, the error judgment circuit 21t]-heritor circuit 14 outputs a signal to select R2'r, and the /ftresk circuit 15 receives Q'', which enters the inner ear of R2, part 1.
1, this II;'j, -1
ζ rectifier circuit 16 (l-4, the parallel output of the soft register circuit 15 is connected to the inner ear of R2 to the wrap circuit 17, and the inner ear of R2 is latched to the wrap circuit 17, and the parallel output of the soft register circuit 15 is this ♀!]>-j
The output of the error compensator is 0, 1, and market (i'
r'r) 2nd i-) J multiple outputs. Too bad, this output t, 11,7 full register circuit 18, the next 7 nodes!・Just before the pulse is sent, the parallel 01. A signal>3- is output so that the selector circuit 14 selects the output e3+11 of the addition N'l I"r 2 o, and a signal is outputted to the register circuit 15, e3-' The contents of -el are entered and the contents are displayed in parallel.
path 16m, /ft register I7] L S B f+! A signal is sent from the error determination circuit 21 so that the output is shifted by one bit to +1 (IL).

frY, )-(, near,/te circuit 17Kk1.I
C31el)/2 The output J is the latch, which becomes the output of this labor-saving error compensator 1'σ, 1', and linear 1' equal f direct interpolation is performed.71! ] becomes t. IThis output t'' is before the next shift pulse t/(2,
The register l':' is input to the circuit 18 in parallel.

Next, L3. Both L2 (/C6g4
．． ', wrong f+J', J ball circuit 21i, 11, selector circuit 19 selects and outputs output e1 of 7-foot register circuit 18 (signal is sent, and selector circuit 14 outputs output from adder 20) This is the same as when a1+g1 is selected and output (send the i number. In the following, only L2 is incorrect), and the selector circuit 16 shifts the output by 1 bit to the LSB side (61+n1)/2 cuff notch C
(i path 17pc is latched, and by outputting it, prefix 1'-?/'' is performed.

Effects of the Invention As described above, in the present invention, unlike the conventional example, a gate circuit is not included in the chronocline, so there is no delay between shift pulses, and digital 4 signals can be transmitted stably. Therefore, even if the 1['1 circuit is incorporated into a large-scale integrated circuit, the excellent effect that the system operates stably can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional co-sign error correction fA device, and FIG. 2 shows the conventional 2'1 bow n! FIG. 3 is a timing diagram of the data reception of the error compensation device 1-1, and FIG. . 3 11. 12, 13, 16.18...7 foot register X circuit, 14, 16.19...・Additional 9 devices, 21...2; Kure'rll 't: L circuit 1,

Claims (3)

[Claims] (1) A first 7-note register circuit that serially inputs a digital binary signal, and a second shift register circuit that receives the output of the first register circuit as an input;
A third circuit whose input is the output of the second shift register circuit.
notregister II)] path and the third /atregister 11
a first selector circuit that selects and outputs the output of the j1 path and the output of the 1-bit whole egg 9, and a fourth 7-nt register circuit that receives the output of the first -[ selector circuit as an input. ,
) ξ parallel output of the fourth shift register circuit and its parallel output are connected to the 1-bit J1μ position via 1- (t
Select one of the outputs shifted to ill, and -
a second selector circuit that outputs one parallel output;
a latch circuit that wraps the parallel output of the selector circuit of 4, a fifth /)1''' / star circuit that uses the parallel output of the latch 1111 as a parallel input; a third selector circuit that selects and outputs either the serial output of the 77 register circuit or the serial output of the first shift register circuit;
Mf, depending on the correctness of the digital signals stored in the first and third 7-foot register circuits, the first. Second.
An error determination circuit for controlling the output of the third selector circuit is provided, and the full adder circuit is configured to fully add the output of the third selector circuit and the output of the sixth shift register circuit. 91 characterized by being configured in
signal error compensation device. (2) The digital signal input is an offset input, and the Q! J'n'
: Claim No. (1) Ji-1, Section 11, No. 91 error compensation device. (3) As error compensation 2, previous U6 protection 4';'+ and 1
1 uniform length 4 The signal value during operation is multiplied by 1.6 depending on the error state of the signal.
The sign error 'r jFf;