JPS596569A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPS596569A JPS596569A JP11652982A JP11652982A JPS596569A JP S596569 A JPS596569 A JP S596569A JP 11652982 A JP11652982 A JP 11652982A JP 11652982 A JP11652982 A JP 11652982A JP S596569 A JPS596569 A JP S596569A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- substrate
- thermocompression bonding
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 8
- 229910000679 solder Inorganic materials 0.000 claims abstract description 8
- 239000010409 thin film Substances 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 4
- 239000011347 resin Substances 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000007598 dipping method Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 230000004907 flux Effects 0.000 abstract 1
- 230000004927 fusion Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000003825 pressing Methods 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010953 base metal Substances 0.000 description 3
- 238000002788 crimping Methods 0.000 description 3
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は混成集積回路に係り、外部引出用端子として安
価な金属を使用し、且つ信頼性の優れた調造方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit, and relates to a manufacturing method that uses inexpensive metal as an external lead-out terminal and has excellent reliability.
一般に混成集積回路装置等の製造に際し、薄膜基板上電
子部品の端子を接続する場合、熱圧着法が用いられる。In general, when manufacturing hybrid integrated circuit devices and the like, a thermocompression bonding method is used when connecting terminals of electronic components on a thin film substrate.
第１図（ａ）〜（Ｃ）は従来の混成集積回路装置におけ
る製造方法の一例を説明するための断面図である。FIGS. 1A to 1C are cross-sectional views for explaining an example of a manufacturing method for a conventional hybrid integrated circuit device.
まず、第１図（ａ）のように公知の方法により薄膜回路
を形成した基板１と第１図（ｂ）のコパールあるいは銅
から成る端子基体２０表面の全面に１例えば金の如く熱
圧着に適し六接合用金属層３を付着させた端子４とを重
ね合せた後、加熱された圧着工具５を端子４の接合しよ
うとする部分に押しあて端子４を前記基板１の導電層６
上に接合する。First, a substrate 1 with a thin film circuit formed thereon by a known method as shown in FIG. 1(a) and a terminal base 20 made of copper or copper as shown in FIG. After overlapping the terminals 4 to which the metal layer 3 for bonding is attached, a heated crimping tool 5 is pressed against the part of the terminals 4 to be bonded, and the terminals 4 are bonded to the conductive layer 6 of the substrate 1.
Join on top.
次に、第１図（Ｃ）のように前記端子４の接合部及び基
板ｌの表面を樹脂７でコートする。従って、熱圧着法に
よシ基板に電子部品の端子を接合する場合の備えるべき
性状としては、まず端子母材金属が塑性変形を生じ易い
ことが要件となっており、且つ、該端子がプリン。ト板
等に安定して接続され得る為に一般には銅の母材金属を
用い、この母材金属の表面の全面に金などの金属層を被
着した端子を用いている。しかるに、金は高価な金属で
あるためにこれを基板との接合用金属層及びプリント板
との接続用金属層として用いた端子は高価なものとなり
、低価格の集積回路装置を製造するうえて大きな障害と
な“っていた。また比較的安価な銅を用いることも可能
であるが、銅は表面酸化を受は易いため、熱圧着の際の
所望の接合強度１得ることが難しいこと、及びプリント
板等への半田接続が不安定であることから種々の問題を
生ずる。Next, as shown in FIG. 1(C), the joint portion of the terminal 4 and the surface of the substrate 1 are coated with a resin 7. Therefore, when bonding electronic component terminals to a board using thermocompression bonding, the required properties are that the base metal of the terminal is susceptible to plastic deformation, and that the terminal is . In order to be able to stably connect to a board or the like, a base metal of copper is generally used, and a terminal is used in which a metal layer such as gold is coated on the entire surface of the base metal. However, since gold is an expensive metal, terminals using it as the metal layer for bonding to the substrate and the metal layer for connecting to the printed circuit board are expensive, making it difficult to manufacture low-cost integrated circuit devices. It was also possible to use relatively inexpensive copper, but since copper is susceptible to surface oxidation, it was difficult to obtain the desired bonding strength 1 during thermocompression bonding. Various problems arise due to unstable solder connections to printed boards and the like.
本発明は経済性の優れた且つ信頼性の安定し念混成集積
回路の製造方法を提供するものである。The present invention provides a method for manufacturing a hybrid integrated circuit which is highly economical and has stable reliability.
本発明の特徴は、薄膜回路を形成し九基板上に外部引出
用端子を熱圧着により接続する工程と、この基板上及び
圧着部を樹脂コートする工程と。The features of the present invention include a step of forming a thin film circuit and connecting an external lead-out terminal on a substrate by thermocompression bonding, and a step of coating the substrate and the crimped portion with resin.
この外部引出用端子を半゛田ディップする工程を少なく
とも含む混成集積回路の製造方法にある。The method of manufacturing a hybrid integrated circuit includes at least the step of solder-dipping this external lead-out terminal.
以下、本発明を実施例により説明する。第２図（ａ）に
おいて、端子基体２を例えば０．２５ｍｍ厚さの銅の板
材を工、チング又は打抜きによって所望の形状に成形し
、しかる後、前記により得た端子基体２の熱圧着接合部
のみに柔軟かつ延展性のある金属、例えば金の如き金属
層３に０．５〜２．０μｍ の厚さに形成する。The present invention will be explained below using examples. In FIG. 2(a), the terminal base 2 is formed by forming a copper plate material with a thickness of, for example, 0.25 mm into a desired shape by machining, chiming, or punching, and then thermocompression bonding of the terminal base 2 obtained in the above manner. The metal layer 3 is made of a flexible and ductile metal, such as gold, and has a thickness of 0.5 to 2.0 μm.
次に、第２図（ｂ）のように公知の方法により薄膜回路
を形成した基板１の導電層６の表面に、前記端子の熱圧
着接合部とを重ね合せた後、加熱された圧着工具５ｔ一
端子４の接合しようとする部分に押しあて、端子４を前
記基板１に接合させる。Next, as shown in FIG. 2(b), the thermocompression bonding portion of the terminal is superimposed on the surface of the conductive layer 6 of the substrate 1 on which a thin film circuit is formed by a known method, and then a heated crimping tool is applied. 5t - press against the part of the terminal 4 to be bonded to bond the terminal 4 to the substrate 1.
次に第２図（Ｃ）のように前記端子４の接合部及び基板
１の表面を、例えばシリコン樹脂ＫＥ１２１２ＡＢＣ（
信越シリコン（株）製）７ｔ−コートした後、１５０℃
の恒温槽で３０分乾燥する。続いて第２図（ｄ）のよう
に端子全体に７ラツクスを塗布し、１００°Ｃのホヤド
ブレート上で１分根度予備加熱を行りた後、２３０℃の
半田溶融槽に、端子が接続された基板全体を浸し、端子
に半田８を付着させる。次に、基板全体を３０℃程度の
温水で洗浄した後、７０℃の恒温槽で３０分乾燥する。Next, as shown in FIG. 2(C), the joint portion of the terminal 4 and the surface of the substrate 1 are coated with silicone resin KE1212ABC (
After coating with 7t (manufactured by Shin-Etsu Silicon Co., Ltd.), 150℃
Dry in a constant temperature bath for 30 minutes. Next, as shown in Figure 2(d), 7lux was applied to the entire terminal, preheated for 1 minute on a hot plate at 100°C, and then the terminal was connected to a solder melting tank at 230°C. The entire board is soaked and solder 8 is applied to the terminals. Next, the entire substrate is washed with warm water at about 30° C., and then dried in a constant temperature bath at 70° C. for 30 minutes.
このようにして、本発明による、混成集積回路を得るこ
とができる。In this way, a hybrid integrated circuit according to the invention can be obtained.
本発明によれば、端子の熱圧着接合部は延展性の優れた
金を用いることにより、端子と基板との接合強度は従来
の端子基体の表面全面に金を形成したものと同等であり
、その他は半田で覆われることにより、プリント板との
接続も安定したものとなル、経済性の非常に優れた、且
つ、信頼性の安定した混成集積回路を得ることが可能と
なる。According to the present invention, the thermocompression bonding portion of the terminal uses gold with excellent ductility, so that the bonding strength between the terminal and the substrate is equivalent to that of a conventional terminal base body in which gold is formed on the entire surface. By covering the other parts with solder, the connection with the printed circuit board becomes stable, making it possible to obtain a hybrid integrated circuit that is extremely economical and has stable reliability.
第１図（ａ）〜（Ｃ）は従来の混成集積回路の製造方法
を工程順に説明するための断面図、第２図（ａ）〜（ｄ
）は本発明による製造方法の工程順の断面図である。
なお図において。
１・・・・・・基板、２・・・・・・端子基体、３・・
・・・・接合用金属層、４・・・・・・端子、５・・・
・・・圧着工具、６・・・・・・導電層、７・・・・・
・シリコン樹脂、８・・・・・・半田、である。FIGS. 1(a) to (C) are cross-sectional views for explaining a conventional method for manufacturing a hybrid integrated circuit in the order of steps, and FIGS. 2(a) to (d)
) is a cross-sectional view of the process order of the manufacturing method according to the present invention. In addition, in the figure. 1... Board, 2... Terminal base, 3...
...Metal layer for joining, 4...Terminal, 5...
... Crimping tool, 6 ... Conductive layer, 7 ...
・Silicone resin, 8...Solder.
Claims (1)
より接続する工程と、前記基板上及び前記圧着部を樹脂
コートする工程と、前記外部引出用端子を半田ディツプ
する工程を少なくとも含むことを特徴とする混成集積回
路の製造方法。The method includes at least the steps of: connecting an external lead terminal to a substrate on which a thin film circuit is formed by thermocompression bonding; coating the board and the crimp portion with a resin; and dipping the external lead terminal with solder. A method for manufacturing a featured hybrid integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11652982A JPS596569A (en) | 1982-07-05 | 1982-07-05 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11652982A JPS596569A (en) | 1982-07-05 | 1982-07-05 | Manufacture of hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS596569A true JPS596569A (en) | 1984-01-13 |
| JPS6347348B2 JPS6347348B2 (en) | 1988-09-21 |
Family
ID=14689377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11652982A Granted JPS596569A (en) | 1982-07-05 | 1982-07-05 | Manufacture of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596569A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54140167A (en) * | 1978-04-24 | 1979-10-31 | Nippon Electric Co | Method of producing integrated circuit device |
| JPS56124254A (en) * | 1980-03-05 | 1981-09-29 | Nec Corp | Indication device |
| JPS5776775A (en) * | 1980-10-30 | 1982-05-13 | Suwa Seikosha Kk | Method of soldering lead wire |
-
1982
- 1982-07-05 JP JP11652982A patent/JPS596569A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54140167A (en) * | 1978-04-24 | 1979-10-31 | Nippon Electric Co | Method of producing integrated circuit device |
| JPS56124254A (en) * | 1980-03-05 | 1981-09-29 | Nec Corp | Indication device |
| JPS5776775A (en) * | 1980-10-30 | 1982-05-13 | Suwa Seikosha Kk | Method of soldering lead wire |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6347348B2 (en) | 1988-09-21 |
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