KR100250140B1 - Method for manufacturing semiconductor part - Google Patents
Method for manufacturing semiconductor part Download PDFInfo
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- KR100250140B1 KR100250140B1 KR1019970018332A KR19970018332A KR100250140B1 KR 100250140 B1 KR100250140 B1 KR 100250140B1 KR 1019970018332 A KR1019970018332 A KR 1019970018332A KR 19970018332 A KR19970018332 A KR 19970018332A KR 100250140 B1 KR100250140 B1 KR 100250140B1
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- plating layer
- solder
- eutectic
- layer
- lead
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title abstract description 39
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 229910000679 solder Inorganic materials 0.000 claims abstract description 41
- 238000007747 plating Methods 0.000 claims abstract description 28
- 230000005496 eutectics Effects 0.000 claims abstract description 24
- 229910052709 silver Inorganic materials 0.000 claims abstract description 17
- 239000004332 silver Substances 0.000 claims abstract description 17
- 229910052745 lead Inorganic materials 0.000 claims abstract description 6
- 229910052718 tin Inorganic materials 0.000 claims abstract description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 15
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 230000008018 melting Effects 0.000 abstract description 10
- 238000002844 melting Methods 0.000 abstract description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 239000010931 gold Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 229910020816 Sn Pb Inorganic materials 0.000 description 3
- 229910020922 Sn-Pb Inorganic materials 0.000 description 3
- 229910008783 Sn—Pb Inorganic materials 0.000 description 3
- LAXBNTIAOJWAOP-UHFFFAOYSA-N 2-chlorobiphenyl Chemical compound ClC1=CC=CC=C1C1=CC=CC=C1 LAXBNTIAOJWAOP-UHFFFAOYSA-N 0.000 description 2
- 101710149812 Pyruvate carboxylase 1 Proteins 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- NMWSKOLWZZWHPL-UHFFFAOYSA-N 3-chlorobiphenyl Chemical compound ClC1=CC=CC(C=2C=CC=CC=2)=C1 NMWSKOLWZZWHPL-UHFFFAOYSA-N 0.000 description 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 101001082832 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) Pyruvate carboxylase 2 Proteins 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
본 발명은 표면에 솔더 도금층이 형성된 리이드부를 포함하는 리이드 프레임, 표면에 은 또는 금 도금층이 형성된 패턴접속부를 포함하는 인쇄회로기판 및 상기 리이드부 및 패턴 접속부를 접합하기 위해 그 사이에 형성된 은과 솔더의 공융점 접합층을 포함하는 반도체 부품에 있어서, 상기 솔더 도금층의 Sn과 Pb의 조성비가 20:80-27:73원자%인 반도체 부품 및 그 제조방법에 관한 것으로서, 솔더 도금층의 조성비를 상기 범위로 하면 200℃ 이상의 용융점을 갖는 솔더 도금층을 얻을 수 있다. 따라서 공융점 접합후에 이어지는 경화공정, 와이어 본딩 공정 등 180-200℃ 범위의 고온에서 실시되는 후속 공정에서도 공융점 접합층이 안정하게 견딜 수 있기 때문에 공정이 안정하게 진행될 수 있을 뿐 아니라 제품의 불량도 막을 수 있는 효과를 얻게 된다.The present invention provides a printed circuit board including a lead frame including a lead part having a solder plating layer formed on a surface thereof, a pattern connection part having a silver or gold plating layer formed on the surface thereof, and silver and solder formed therebetween to join the lead part and the pattern connection part. A semiconductor component comprising a eutectic junction layer, wherein the composition ratio of Sn and Pb in the solder plating layer is 20: 80-27: 73 atomic%, and a method for manufacturing the same, wherein the composition ratio of the solder plating layer is in the above range. In this case, a solder plating layer having a melting point of 200 ° C. or more can be obtained. Therefore, since the eutectic point bonding layer can stably withstand the subsequent processes carried out at a high temperature in the range of 180-200 ° C., such as the curing process and the wire bonding process following the eutectic point bonding, the process can not only proceed stably but also the defect of the product. You will get an effect that can be prevented.
Description
본 발명의 반도체 부품의 제조방법에 관한 것으로서, 보다 상세하게는 리이드 프레임과 인쇄회로기판 (PCB)의 공융점 접합 온도를 높여줌으로써 경화 공정, 와이어 본딩 공정 등과 같은 후속의 고온 공정에서도 양호한 접합 상태가 유지될 수 있는 반도체 부품 및 그 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor component of the present invention, and more particularly, by increasing the eutectic point junction temperature of a lead frame and a printed circuit board (PCB), a good bonding state is achieved in subsequent high temperature processes such as a curing process and a wire bonding process. A semiconductor component that can be retained and a method of manufacturing the same.
본 발명에 따른 반도체 부품의 제조 방법은 멀티 칩 패키지 (multi chip package: MCP)에 관련된 기술로서 리이드 프레임 가공 기술과 PCB 가공 기술을 복합 적용한 것이다. 즉, 전자 제품의 경박단소화 및 그에 따른 반도체 부품의 고집적화에 따라 본딩 패드 피치가 점차 줄어들고 있다. 따라서 파인 피치 (fine pitch)가 요구되는 이너 리이드 (inner lead)부를 PCB 가공기법으로 제조하고 외각 부분을 리이드 프레임 가공 기술로 제조한 다음, 각각을 접합하는 방법에 대한 연구가 진행되고 있다.The method for manufacturing a semiconductor component according to the present invention is a technique related to a multi chip package (MCP), which is a combination of a lead frame processing technique and a PCB processing technique. In other words, the bonding pad pitch is gradually decreasing due to light and short and small integration of electronic products and high integration of semiconductor components. Therefore, research has been made on a method of fabricating an inner lead portion requiring a fine pitch by a PCB processing technique, an outer portion of the lead frame processing technique, and then joining each of them.
접합 방법의 일예로서 리이드 프레임의 리이드를 구부려 클립 형태로 만들어 인쇄회로기판에 끼워 고정한 후 솔더 (solder)를 도포하고 가열 압축하여 용융시켜서 접합하는 방법이 있는데, 이 방법에 의하면 리이드 프레임을 클립 형태로 가공하기가 어려울 뿐 아니라 가공된 클립 형태의 리이드 프레임의 부착성 역시 불량하다는 문제점이 있다.An example of the joining method is a method of bending a lead of a lead frame into a clip shape, fixing the lead frame to a printed circuit board, and then attaching the solder by applying a solder, heating and compressing the melt to join the lead frame. Not only is it difficult to process, there is a problem that the adhesion of the lead frame in the form of a processed clip is also poor.
다른 접합 방법으로서 리플로우 (reflow) 솔더링 기법이 많이 사용되어 왔다. 리플로우 솔더링 기법이란 접합될 양쪽 표면에 솔더 (Sn/Pb)를 도금하고 솔더가 용융될 때까지 두 표면을 함께 가열한 다음, 온도를 솔더의 용융점 이하로 낮추어 접합 위치를 경화시킴으로써 접합하는 방법이다.As other joining methods, reflow soldering techniques have been widely used. Reflow soldering is a method of bonding by plating solder (Sn / Pb) on both surfaces to be joined, heating both surfaces together until the solder melts, and then lowering the temperature below the melting point of the solder to harden the joint location. .
그러나, 리플로우 솔더링 기법의 경우에는 인쇄회로기판의 패턴 접속부에 솔더층을 추가로 형성하여야 하므로 공정이 복잡해질 뿐 아니라 솔더를 다량 도포하여 접합하여야 하므로 미세 피치 제작시 리이드와 리이드 간에 단락이 발생할 수 있고 회로기판의 표면이 솔더로 오염될 가능성도 배제할 수 없다는 문제점이 있다.However, in the case of the reflow soldering technique, the solder layer must be additionally formed in the pattern connection part of the printed circuit board, which not only complicates the process but also requires the application of a large amount of solder to bond, so that a short circuit may occur between the lead and the lead when manufacturing a fine pitch. And there is a problem that can not exclude the possibility that the surface of the circuit board is contaminated with solder.
이러한 솔더링 기법의 문제점들을 극복할 수 있는 방법으로서 인쇄회로기판의 패턴 접속부와 리이드 프레임중 한쪽에는 금 또는 은 도금층을 형성하고 다른 한쪽에는 솔더 도금층을 형성한 다음, 이 두층간을 공융점 접합함으로써 반도체 부품을 제조하는 방법이 제안된 바 있다.As a method of overcoming the problems of the soldering technique, a gold or silver plating layer is formed on one side of the pattern connection part and the lead frame of the printed circuit board, and a solder plating layer is formed on the other side, and then the semiconductor layer is formed by eutectic bonding between the two layers. A method of manufacturing a part has been proposed.
도 1은 전술한 바와 같은 공융점 접합의 일예를 설명하기 위한 도면이다.1 is a view for explaining an example of the eutectic point junction as described above.
도 1을 참조하면, 표면의 패턴 접속부에 은 도금층 (6)이 형성된 이너 PCB (1)가 있고, 상기 이너 PCB (1) 상의 패턴 접속부에 표면에 솔더 도금층 (3)이 형성된 리이드 프레임 (2)이, 다이 패드 상에 칩이 놓여 있으며, 상기 칩과 패턴 접속부는 금 와이어 (5)에 의해 연결되어 있다.Referring to FIG. 1, there is an
상기 은 도금층 (6)과 솔더 도금층은 공융점 접합되는데 접합 온도는 솔더의 용융 온도에 따라 좌우되며, 이 용융 온도는 Sn과 Pb의 함량에 따라 달라진다.The silver plated layer 6 and the solder plated layer are eutectic point-bonded. The junction temperature depends on the melting temperature of the solder, and this melting temperature depends on the content of Sn and Pb.
통상은 Sn:Pb의 조성비가 28.1:72.9-98.7:1.3원자%인 솔더가 주로 사용된다.Usually, the solder whose composition ratio of Sn: Pb is 28.1: 72.9-98.7: 1.3 atomic% is mainly used.
도 2는 Sn-Pb 상태도인데, 이 상태도로부터 상기와 같은 Sn/Pb 조성을 갖는 솔더의 용융점을 찾아보면 약 183-220℃에서 결정되며, 이에 따라 은 도금층과 솔더 도금층의 공융점 온도는 약 183℃에서 결정된다.2 is a Sn-Pb state diagram. From this state diagram, when the melting point of the solder having the Sn / Pb composition is found, it is determined at about 183-220 ° C. Thus, the eutectic melting point temperature of the silver plating layer and the solder plating layer is about 183 ° C. Is determined.
그러나, 공융점이 약 183℃인 솔더 도금층의 경우에는 약 190℃ 이상의 고온에서 실시되는 후속의 경화 공정이나 와이어 본딩 공정시에 공융점 접합이 떨어져 불량을 초래하게 된다는 문제점이 있었다.However, in the case of a solder plating layer having a eutectic point of about 183 ° C., there is a problem that the eutectic point bonding is dropped during the subsequent curing or wire bonding process performed at a high temperature of about 190 ° C. or more, resulting in a defect.
본 발명이 이루고자 하는 기술적 과제는 리이드 프레임과 인쇄회로기판 (PCB)의 공융점 접합 온도를 높여서 경화 공정, 와이어 본딩 공정 등과 같은 후속의 고온 공정에서도 양호한 접합 상태가 유지되는 반도체 부품의 제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a semiconductor component in which a good bonding state is maintained even in a subsequent high temperature process such as a curing process and a wire bonding process by increasing the eutectic point junction temperature of the lead frame and the printed circuit board (PCB). It is.
본 발명이 이루고자 하는 다른 기술적 과제는 후속의 고온 공정에서도 양호한 접합 상태를 유지할 수 있는 반도체 부품의 제조방법을 제공하는 것이다.Another object of the present invention is to provide a method for manufacturing a semiconductor component capable of maintaining a good bonding state even in a subsequent high temperature process.
도 1은 이너 PCB부와 리이드 프레임이 접합된 상태를 도시한 단면도이다.1 is a cross-sectional view showing a state in which the inner PCB portion and the lead frame are bonded.
도 2는 Pb-Sn 공정계 (共晶系상) 상태도이다.2 is a Pb-Sn eutectic state diagram.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1... 이너 PCB 2... 리이드 프레임1 ... Inner PCB 2 ... Lead Frame
3... 솔더 (Sn/Pb) 도금층 4... 칩3 ... solder (Sn / Pb)
5... 골드 와이어 6... 은 도금층5 ... gold wire 6 ... silver plated layer
본 발명의 기술적 과제는 표면에 솔더 도금층이 형성된 리이드부를 포함하는 리이드 프레임, 표면에 은 도금층이 형성된 패턴접속부를 포함하는 인쇄회로기판 및 상기 리이드부 및 패턴 접속부를 접합하기 위해 그 사이에 형성된 은과 솔더의 공융점 접합층을 포함하는 반도체 부품에 있어서, 상기 솔더 도금층의 Sn과 Pb의 조성비가 20:80-27:73원자%인 반도체 부품에 의하여 이루어질 수 있다.The technical problem of the present invention is a lead frame including a lead part having a solder plating layer formed on a surface thereof, a printed circuit board including a pattern connection part having a silver plating layer formed on the surface thereof, and silver formed therebetween to join the lead part and the pattern connection part; In a semiconductor component including a eutectic junction layer of solder, the composition ratio of Sn and Pb of the solder plating layer may be 20: 80-27: 73 atomic%.
상기 본 발명의 반도체 부품에 있어서, 상기 은 도금층의 두께는 0.3-0.8㎛이고, 솔더 도금층의 두께는 10-20㎛이다.In the semiconductor component of the present invention, the silver plating layer has a thickness of 0.3-0.8 μm, and the solder plating layer has a thickness of 10-20 μm.
본 발명의 다른 기술적 과제는 인쇄회로기판의 패턴부 상에 은 도금층을 형성하는 단계; 상기 패턴부와의 접착면을 포함하는 리이드 프레임의 리이드부의 적어도 일면에 Sn과 Pb의 조성비가 20:80-27:73원자%인 솔더층을 형성하는 단계; 및 상기 패턴부와 리이드부를 200-350℃에서 공융점 접합하여 공융점 접합층을 형성하는 단계를 포함하는 반도체 부품의 제조방법에 의하여 이루어질 수 있다.Another technical problem of the present invention is to form a silver plating layer on a pattern portion of a printed circuit board; Forming a solder layer having a composition ratio of Sn: Pb of 20: 80-27: 73 atomic% on at least one surface of the lead portion of the lead frame including the adhesive surface with the pattern portion; And forming the eutectic junction layer by eutecting the pattern portion and the lead portion at 200-350 ° C. to form a eutectic junction layer.
본 발명에 따른 반도체 부품의 제조방법에 있어서는 솔더 도금층의 용융 온도가 200℃ 이상이기 때문에 공융점 접합층이 후속의 고온 공정에서도 견딜 수 있는 내열특성을 갖게 된다.In the manufacturing method of the semiconductor component which concerns on this invention, since the melting temperature of a solder plating layer is 200 degreeC or more, a eutectic point bonding layer will have the heat-resistant characteristic which can be tolerated in a subsequent high temperature process.
도 2의 Sn-Pb 상태도를 참조하여 보면, 200℃에서 Sn:Pb의 조성비가 27:73이면 솔더는 용융이 시작되고, 200℃보다 높아지면 솔더는 고상의 Pb와 액상의 Sn-Pb가 혼합된 반용융 상태가 되고, 300℃에서 Sn:Pb의 조성비가 20:80이면 솔더는 Pb와 Sn이 모두 액상인 완전 용융 상태이다.Referring to the Sn-Pb state diagram of FIG. 2, when the composition ratio of Sn: Pb at 200 ° C. is 27:73, the solder starts melting, and when the temperature is higher than 200 ° C., the solder mixes solid Pb and liquid Sn-Pb. If the composition ratio of Sn: Pb is 20:80 at 300 ° C, the solder is in a completely molten state in which both Pb and Sn are liquid.
즉, 솔더 도금층이 200-300℃의 용융점 범위를 유지하도록 Sn/Pb의 조성을 변화시켜 공융점 접합이 고온에서 실시될 수 있도록 하면 후속의 고온 공정에서도 은과 솔더의 공융점 접합층이 안정한 상태를 유지할 수 있게 된다.In other words, by changing the composition of Sn / Pb so that the solder plating layer maintains the melting point range of 200-300 ° C. so that the eutectic junction can be carried out at a high temperature, the eutectic junction layer of silver and solder is stable in the subsequent high temperature process. It can be maintained.
본 발명에서 따르면, 솔더의 용융점 온도를 높여서 은과 솔더의 공융점 접합이 고온에서 실시될 수 있도록 솔더의 Sn과 Pb의 조성비를 제어한다. 이렇게 하면 공융점 접합후에 이어지는 경화공정, 와이어 본딩 공정 등 고온의 후속 공정에서도 공융점 접합층이 안정하게 견딜 수 있기 때문에 공정이 안정하게 진행될 수 있을 뿐 아니라 제품의 불량도 막을 수 있는 효과를 얻게 된다.According to the present invention, the composition ratio of Sn and Pb of the solder is controlled to increase the melting point temperature of the solder so that the eutectic junction of silver and the solder can be carried out at a high temperature. In this way, since the eutectic point bonding layer can stably withstand the subsequent high temperature processes such as curing process and wire bonding process after eutectic point bonding, the process not only proceeds stably but also prevents product defects. .
Claims (4)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970018332A KR100250140B1 (en) | 1997-05-12 | 1997-05-12 | Method for manufacturing semiconductor part |
| JP34619797A JPH10189855A (en) | 1996-12-17 | 1997-12-16 | Lead frame for multi-chip package and its manufacture |
| CN97107274A CN1209655A (en) | 1996-12-17 | 1997-12-17 | Lead frame for multiple chips packing and mfg. method therefor |
| TW86119117A TW388092B (en) | 1996-12-17 | 1997-12-17 | Lead frame for multi-chip package and manufacturing method therefor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970018332A KR100250140B1 (en) | 1997-05-12 | 1997-05-12 | Method for manufacturing semiconductor part |
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| Publication Number | Publication Date |
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| KR19980083164A KR19980083164A (en) | 1998-12-05 |
| KR100250140B1 true KR100250140B1 (en) | 2000-04-01 |
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| KR1019970018332A KR100250140B1 (en) | 1996-12-17 | 1997-05-12 | Method for manufacturing semiconductor part |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100356413B1 (en) * | 1999-11-05 | 2002-10-19 | 사단법인 대학산업기술지원단 | Method of reflow soldering in partial melting zone |
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