JPS5965332A - Ring bus interface circuit - Google Patents

Abstract

PURPOSE:To realize a suitable circuit for control of data transfer among plural ring buses, and to improve the universality for a ring bus interface circuit, by providing a means which sets the priority on transfer ring request signals among plural sets of signals to select a pair of the request signals, and delivering a selection control signal. CONSTITUTION:A logical deciding circuit part, etc. are provided to have the priority on the transfer request signals among plural sets of signals and select one pair of the request signals to deliver a selection control signal. For instance, three sets of signals 11, 12 and 13 are supplied to a gate circuit part 1001, and at the same time the transfer request signal of each paired signals and a transfer destination disignating signal to a logical deciding circuit 1000 by signals 19, 20 and 21. Then the circuit 1000 delivers a selection signal 22 on the basis of a combination logic between the transfer destination designating signal of the paired signals selected by the priority on the transfer request signal, and the control signal of a signal 23. Then one of set signals 11, 12 and 13 is delivered to a set signal 17 by a gate circuit part 1001 and on the basis of the signal 22. Then the transfer acknowledge signal supplied from a signal 18 is delivered to one of signals 14, 15 and 16.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to data transfer between a plurality of rings in an information processing device when data transfer is performed by connecting a plurality of arithmetic units arranged in a ring with a unidirectional transfer ring bus. This relates to a circuit that controls the

Conventionally, when a plurality of arithmetic units are combined to perform arithmetic processing, there is a method using a ring bus as a method for transferring data from an arbitrary arithmetic unit to an arbitrary arithmetic unit. The ring bus method has the disadvantage that the delay increases in proportion to the distance between the transfer modules, but it is easy to implement because it only requires the preparation of transfer paths between adjacent computing modules, and the control system can also be localized. It is a method.

However, in a single ring, when the number of processing modules increases, the transfer delay time is generally ignored and the transfer capacity becomes insufficient. Therefore, the ring is divided into smaller rings to create a hierarchical ring configuration. It will be done. In this case, in order to transfer data between the divided ring buses, each ring bus has to selectively output the transfer data required for its own ring bus and the transfer data from the standard ring bus. It was designed to suit the needs of people, and was not a general-purpose product.

An object of the present invention is to provide a ring bus interface circuit that is suitable for controlling data transfer between a plurality of ring buses as described above and is versatile against system malfunctions. According to the present invention, it is possible to perform a versatile multi-ring bus connection by using a simple configuration and setting control parameter signals.

According to the present invention, there is provided a plurality of input terminals for a set signal including a transfer signal, a quest signal, a transfer destination designation signal, and a data value signal, a control signal input terminal, and one transfer acknowledge signal input terminal; It has a transfer acknowledge signal output terminal corresponding to each set of the plurality of set signal inputs, and a set/signal output terminal capable of outputting one set of the set signals, and a transfer request signal in the set No. 48 of the plurality of sets. One set is selected with priority, and the selected a! Transfer destination during signal!
a logic determination circuit section designated as Fi, selects one set of input signals from among the plurality of sets of input signals according to the selection control signal described in II, and outputs the selected set to the set signal output terminal 1-; The acknowledge signal input from the transfer acknowledge @ input terminal is transferred to the transfer acknowledge signal corresponding to the selected group signal.
A ring bus including a gate circuit that outputs a signal to a transfer acknowledge signal output terminal corresponding to the selected group signal.
[Interface circuit fr f'J 7] This will be explained here.

Signal 11 is a combination signal of a transfer request signal, a transfer destination designation signal, and a data value signal, and signal 12. 13 is a similar set of signals, and in this example, 3 sets of set signals are sent to the gate circuit 10.
01 is input.

Among the signals 11, 12, and 13, the transfer request signal and the transfer destination designation signal of the set signal selected according to the transfer priority order! In combination with the control signal No. 230 and the control signal No. 230, the logic judgment circuit section 1000 outputs the selection signal 22.

The gate circuit 1001 outputs one of the group signals 11°, 12, and 13 as the group signal 17 in response to the selection signal 22.

Further, the transfer acknowledge signal inputted from the signal 18 is used as the transfer acknowledge signal corresponding to the selected group signal, and the signal 14. Or 15. Or output to one of 16.

The detailed operation of the embodiment shown in FIG. 1 will be explained below with reference to the block diagram shown in FIG. 2 and the timing charts shown in FIGS. 3 and 4.

FIG. 3 shows the input signal of the arithmetic unit used in the present invention, and has negative logic. Although the data is transferred N times (N21) due to the limit on the number of terminals, it is assumed that the transfer destination designation signal is included in the first transfer data. Thereafter, as shown in FIGS. 2 and 3, the receiving side sends back the transfer acknowledge signal 2 in negative logic to the transmitting side. The sender then acknowledges the transfer and turns it off. Thereafter, the second transfer is performed in the same manner, and the transfer of l data is completed.

Figure 2 Nioite, signal 101.102.103 &! These are the transfer motion quest signals of the three sets of input signals, which are hereinafter referred to in order as RA+, R, B+, and 几C-.

Signals 129, 130, and 131 are transfer destination designation signals for each set of signals. For example, if φ is composed of four signal lines, 4
This means that the destination of 16 bits can be specified, and these are hereinafter referred to as (in order) CDA, DB, and DC.

Signals 132 and 133 are control signal inputs, and are sent to the transfer destination.
If INH- is "1", it means that OC is active, that is, becomes "\".

The output signals QC, OB, and OA of PLA501 are output as signals 111, 112, and 113, respectively, and
It is sampled and protected at the rising edge of the clock signal 134 at 02. At this time, the output signal 114,1 of the latch 502
Only one of 1511.6 is on, that is, "\", and only one of the outputs of AND gates 504.505.506 is the BUS BUF to the output group signal 124.
FEILl.

513, 514.515 and transfer acknowledge signal 123
One set of BUS BUFFi 510.511.512 will be turned on.

FIG. 4 shows a timing chart at this time. In the figure, signal 3 is the selection signal 111 output from the PLA.
．． Of 112 and 113, those that are turned on are shown.

Signal 4 is the sampling signal of latch 502. Signal 5 represents the selection signal sampled by latch 502. Signal 6 represents the transfer acknowledge signal of signal 123 in FIG. Signal 7 is BUSBO-FFEII, 510
．． The control signals of 511, 512, 513, 514, and 515 are continuously kept in the ON state, that is, "\" during the two data transfers. Signal 8 is a signal that is inverted at the falling edge of signal 6, and is a signal that is inverted at the falling edge of signal 6.
508 and the selected signal line of the output signals 117, 118, 119 of latch 503 to be in the on "east" state. Signal 7 is signal 5° and signal 6.
It can be obtained by the AND of the signal 8, and corresponds to the AND game (504.505.506 in FIG. 2).

The AND gate 509 turns off the INH- signal to "1" when the signal 127 indicating that the first transfer and the second transfer are in the middle is off "1" and the transfer acknowledge is off "1". to enable operation of the PLA 501.

The inverter 507 inverts the falling edge of the transfer acknowledge signal 123 between the flip-flop 508 and the latch 50.
This signal is used as the rising edge trigger signal 126 of No. 3.

Next, the effects of the present invention will be explained using a block diagram of 151ffl as a system using the embodiment shown in FIG.

Host CPU 601 Hakosen bus 201 bus 2
02 and input/output controller (IOC)
603, bus 203 connects common bus 201 to IU
has been done. The ring bus interface and chair circuits of the present invention include 1 (604), 1t2 (605), and f (60).
6), and the PUI (6) is used as a calculation unit.
08), PO2 (609) PO2 (610), PO
4 (611), and DATA MEMORYL knit 6
There is 07. 604.608.609.610.611
is ring bus 210.211.212.213.205
are cascaded in a ring shape. On the other hand, 60
5, 607 also intersects with the ring by ring buses 206 and 207, and 606 and 603 also intersect with ring buses 208.
．． 204, it forms a multiple ring configuration that similarly intersects the aforementioned rings.

Here, the destination designation number of each calculation unit is I
For OC603, "\J, l'Ul(608),
PO2 (609) PO2 (61\'), PO4 (6
11) for r I J, r 2 J, r3Jr
4 J, DATA kiEfvlORY
"15" for y Toro 07, still ring interface circuit (■ also 1 to R3) 604.605.60
The ring bus interface circuit R1 (604) sets the priority order of each input signal to the ring bus 207.20.
5.204, and similarly, ring bus interface circuit 2 (605) also has ring buses 205.204.209. At the ring bus interface times 1 each h3 (606), the ring bus 207.
205 (in this case, the one with the lowest priority is used). At this time, the above (1) and (2)
Regarding the ring bus interface circuit 1 (1 (604)), the control parameters in equation (3) are P-E, Q
-os X-0, Y-0, +l Ring Bus Interface Nice Circuit Rimo 2 (605) ICBS L
P-E.

For Q-0, X-1, Y-1, ring bus/f interface circuit B, 3 (60G), P-0,
It may be set to -1. Regarding the ring bus interface circuit 1 (t+04), (1)
(2) Substituting into equation (3), we get OC-Imasu・〔』E〕・〔■Suoni〕・IIken■←
(4)0'A-(1(c-) ・PB-・(
L)C4j'S) (D decrease]・INH-(5), and the destination specification is "E" indicating DArA 61Ei'JOY607 or "\" indicating IOC603. It can be seen that data is output to the ring bus 21'Q.

Similarly, ring bus interface R2 (605) rB where the destination designation indicates DATAN island 10R, Y 607,
When the data is J, the data is output to the ring bus 206, and at the ring bus interface R3 (606), when the destination designation is "\" indicating the IOC 603, the data is output to the ring bus 208. According to the present invention, the transfer control method can be changed to the ring bus interface circuits R1, 2 and R3 (604
, 605, 606), it can be used by simply changing the control parameter signal input.

Furthermore, regarding increasing the number of input pairs, for example, FIG. 6 shows the output/signal 306 of the ring bus interface 701.
By entering the Woring bus interface 7020, the number of inputs can be reduced to 301.302.303.304゜30.
5, and the configuration is shown in which the output 307 is obtained. In this case, the control parameter signals may be the same for both ring bus interface circuits 701 and 702.

-t', the 7th a is the l data bus interface 703 and the arithmetic unit 705. The ring bus 30 connects the ring extending from the ring bus interface 704 and the arithmetic unit 706.
0.3]2.313, which is a hierarchical ring-connected configuration.

Note that the signal line 310.314 is the arithmetic unit 705.7.
This is the input signal to 06. As described above, according to the present invention, a large-scale hierarchical galling bus system can be constructed relatively easily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the present invention, and FIG. 2 is a block diagram showing a variant embodiment of the present invention.
FIG. 4 is a timing chart of the input/output control signals of the arithmetic unit used in the embodiment of the ring; FIG. 4 is a timing chart of the internal control B signal in the embodiment of FIG. 2; FIG.
FIGS. 6 and 7 are block diagrams showing examples of system configurations using the present invention. In the figure, 504, 505, 506, 509 are inverters (504, 505, 506, 509), 508 are inverting flip-flops with rising edge locks, and 507 are inverters 510, 511, .
512゜513.514.515 is 3-8'I'ATE
This is the BUSBUFFFt claw of C0NTR0L, and the enable signal is negative logic ◎604, 605.607.7
01.702.703.704 is a ring bus interface circuit, 608.609. (510,611
705 and 70611 are the performance units. 603 is an input/output control circuit, and 601 is a host (CPC). 11-23.101N134.211-屹13.301
N314 indicates a signal line, and 1 to 8 indicate changes in values on the signal line over time.Representative Patent Attorney JJ BA Susumu Figure 1 Figure 2 10 = 0B /24 Figure 3 4th Figure 5 4 leaves 7 sides

Claims (1)

[Scope of Claims] A plurality of sets of signal input terminals each including a transfer request signal, a transfer destination designation signal, and a data value signal, a control signal input terminal, and one transfer acknowledge signal input terminal; It has a transfer acknowledge signal output terminal corresponding to each set of set signal inputs and a set signal terminal capable of outputting one set of the set signals, and prioritizes transfer request signals among the plurality of set signals. a logic determination circuit unit that selects one set, determines whether or not to transfer based on a transfer destination designation signal in the selected set of signals and the control signal, and outputs a selection control signal; Selecting one set from the plurality of sets of input set signals and outputting it to the set signal output terminal, and transmitting the acknowledge signal input from the transfer acknowledge signal input 1 child to the transfer acknowledge signal output terminal corresponding to the selected set signal. A ring bus interface circuit 0 characterized in that it is equipped with a gate circuit that outputs to