JPS60151764A - Channel controlling device - Google Patents

Abstract

PURPOSE:To shorten effective time of transfer by setting the direction of transfer in a transfer direction controlling register that determines the direction of data transfer before starting direct memory access transfer and enabling data transfer of an optional transfer direction. CONSTITUTION:When a direct memory access channel start request is generated, a control logic DMAC8 generates a counter address 12, and releases a bus buffer 10 that makes connection control of an address bus 5 and data bus 6. Synchronizing with the counter address 12 generated by the DMAC8, information of a transfer mode setting register 9 is sent out to a transfer mode control signal circuit 11 as a DMA transfer mode signal 17. A sending signal of data is generated in an inputting/outputting device 3 synchronizing with a transfer mode signal 14 generated from the DMAC8. OUT1 information of the inputting/outputting device 3 is sent out to the data bus 6 and stored in the DMAC8.

Description

[Detailed Description of the Invention] [Field of the Invention for 4U] The present invention relates to a 2-digit 0 direct memory access (iVA) transfer control method for magnetic computing,
1) Before activating the MA transfer, set the transfer direction in the transfer direction +1tlJ cape register that determines the data transfer direction, and make it possible to transfer data in the transfer direction of t and t with - DMA transfers. However, it is better to reduce the effective transfer time and cost for the 41 channel control 11 equipment.

[Back spring of invention]

The data transfer method using the DIS4 A channel in a conventional computer system is a method in which all data is transferred in the same transfer direction.

Also, the data transfer method with arbitrary rotation direction t is PCMA.
Alternatively, there is a method in which activation is performed multiple times each time the transfer direction changes using a DMA method.

Currently, with the diversification of computing systems, effective use of system buses is required.

FIG. 4 shows a reference example U in 2 for switching the transfer direction of the system bus in the multiple activation method using the l'cMA method and the DMA method.

In the PCMA method, the instruction fetch processing cycle is
This depends on the effective transfer time of the system bus, and the effective transfer time of the system bus is less than 2/3 of the processing time.

Furthermore, as the number of transferred words increases, the number of system programs increases and the transfer direction mlj++11 is performed by the program, so the processing time also increases.

In the conventional f) MA method, for each cut # in the transfer direction, 1) M
The tail filling cycle for switching the A channel mode is involved in effective transfer, and the effective system bus transfer time relative to the processing time is drastically reduced by 1@ in proportion to the number of transfer direction switches.

FIG. 5 shows the relationship between the processing time and the number of transfer direction switching in the PCMA method and the conventional DMA method.

This figure shows an example of data transfer between the system bus and local bus.

In the PCMA method, the transfer direction is all designated by a program, so the processing time increases as the transfer switching cycle occurs.

The method of reducing the total processing time using the PCMA method requires an improvement in the program processing speed or the bus transfer speed, and it costs a lot of money to shorten the processing time.

In the conventional DMA system, the processing time increases rapidly due to an increase in the number of transfer errors in the transfer direction.

[Purpose of the invention]

The purpose of the present invention is to access a system bus by continuously specifying an arbitrary transfer direction without depending on the switching cycle of the data transfer direction, thereby shortening the data transfer processing time and shortening the effective system bus transfer time. DMA channel kJ is provided.

[Summary of the invention]

The present invention utilizes the MA transfer method for data transfer to shorten the effective transfer time of the system bus. As a means to solve the problem, J) Add a transfer mode control register and transfer mode control + 1jll logic that can control the transfer direction full pressure point in synchronization with the counter address generated during MA transfer. Regardless of the direction switching cycle, it depends only on the number of words to be transferred, and the effective transfer time of the system bus can be shortened.

[Embodiments of the invention]

FIG. 1 shows an example of a conventional DMA transfer method. The conventional DfA method is a normal DMA? li control logic (
Transfer mode signal +- output from DMAC (hereinafter abbreviated as DMAC)
)14, only the same transfer mode could be generated during one 1) MA transfer time.

FIG. 2 shows one embodiment of the present invention. This embodiment is an example in which f) MA channel control device 4 of the present invention is applied between input/output devices 2 and 3 connected to the same bus 16.

In this configuration, the CPU and DMA channel IttlJ# devices 4 and the input/output devices 2 and 3 are connected to the same bus 16. Also, the OUT of input/output device 1
This information is transferred as INI information of the 1 v** report output device 2, and is transferred using the DMA channel device 4 upon one-time 1) MA activation.

A transfer mode setting register 9 is added to the block diagram shown in FIG. 1, and all transfer mode information corresponding to the master address 12 generated from the DMAC is set.

DMA channel activation activation request Kinishi and 1) MAC8,
Counter address 12f: Generates connection 111J of address bus 5 and data bus 6. Opens bus buffer 1OJt.

The counter address is transmitted onto the address bus 5 and activates 0UTl of the input/output device 3.

At this time, L) Colorizer address 1 generated from MAC8
In synchronization with 2, the transfer mode construction register 9's refresh report is 1.
) As the MA transfer mode signal 17, transfer mode rlII
The signal is sent to the J control No. 1g circuit 11.

1) In synchronization with the transfer mode 1 word 14 generated by the MAC 8, the noter is sent to the input/output device 3 to generate a signal.

The 0UTII blue report from the input/output device 3 is sent to the data bus 6 and stored in 1) MAe8.

Next, the counter address 12 is updated and the input/output device 2
f) stores the transfer information stored in the MAC 8, and completes - times of DMA cycles.

A feature of the invention is that the information in the transfer mode register 9 controls the transfer mode in synchronization with the counter address of the DMAC 8. The present invention provides efficient system bus D.
This enables MA transfer and eliminates the need for transfer mode switching time during DMA transfer processing.

FIG. 3 shows a second embodiment of the invention.

This embodiment is a transfer sequence based on DMA channels of different types of buses.

Transfer mode control circuit 2 is used to access different types of buses r.
0.21 is installed separately to accommodate different types of buses 27.16 and 27.16.

Set transfer mode 1'Vv information in transfer mode setting register 9, and access all lines of bus 16 (yl) or bus 27.
When the information is set in the setting register 23 that accesses the system and a DMA start request is issued, the output register connected to the bus 27 becomes active (1.1).
)Transfer mode signal 4 sent from MAC8 and bus conversion signal 26 and transfer mode 1 of the bus 27 series that received the same JIA money
Transfer mode 100 is set to 1 according to the transfer mode setting register 9 and the transfer mode itj [ll wholesale IN No. 17, all the transfer mode signals 28 are generated, and the transfer information of the input/output device 22 is sent to DM.
Store in AC8.

Next, the counter address 24 is updated, the bus conversion signal 26 changes synchronously, the transfer mode control circuit 20 becomes active, and according to the information in the transfer mode setting register 9, No. 17 is sent in the ridge mode. , transfer mode polarization 14
In synchronization with , payment mode 1 word 7 is sent out. At this time, the bus connection buffer 6 accesses the bus 16 side and goes to the human output theory 1d2.
Forward M-news.

The special feature of this implementation column is that a transmission mode control circuit 21 and a bus conversion register 23i are added to the DMAC 8, the transfer mode setting register 9, the transfer mode +jlJ +1ti1 circuit 20, and the transmission mode control circuit 21 and the bus conversion register 23i for converting different types of buses 27i and 1111. , it is possible to specify the direction of transfer of status between buses for one thing fzD
MA channel 1 same cape is the same transfer as conventional ivi A and processed 4 at the same time! It becomes possible.

1 transfer mode city Ij++14 Lujista and transfer mode city I
As shown in Figure 4, due to the addition of hardware to the +410 switch, the effective transfer time of the system bus can be reduced by only -turn D IM, A transfer excitation, even if the data transfer direction is mixed. 0T capacity and lt), / stem bus effective transfer time... are compared with the PCMk method and the conventional I) MAA method.
It can be shortened to at least 2/3 or less. Tsuma p,
i'CMA fetch cycle FE and conventional DM
The mode set cycle IV S time of method A is reflected in the effective transfer time when accessing the system bus SB21
/z<, I) Only the DMA transfer time other than one mode set tickle of the MA is required in the effective transfer time.

Figure 5 shows, as an example, 2KW, 1 transfer Nykle 2/
u s, i' CtV A method, conventional i) ivl
The effective transfer time and number of transfer direction switching times of the system bus of the A method and the present invention are shown.

2. In the figure, 13 is a DIV AC data bus, and 25 is a data bus.

〔Effect of the invention〕

According to the present invention, compared to the PClJ, i'y method, and DMA method, the effective transfer time τ is less than 1 pe in terms of the number of times the transfer direction is switched.

Car between drawings 1. Example A Figure 1 is a system diagram of the conventional DMA transfer method, with the same system bus of the second gang member, TtIIJ, and transfer between compatible output devices +i! FIG. 3 is a block diagram of another embodiment of the present invention; FIG.
ctnA is a diagram of the operation of a conventional DMA type bus, and FIG. 5 is a diagram showing transfer direction switching and recovery and effective transfer time using the present invention.

Claims (1)

[Claims] 1. In a calculation control system having a central processing unit and a direct memory access channel t, if +jt is transferred to the direct memory access 4, and τ is transferred to the direct memory access cycle door 4d. Channel City υ1 wholesale equipment with all the features of BO. 2. In claim 1, what is the transfer method? A Nayair+ff1J1 wholesale device characterized by being provided with a transfer mode control register that can be arbitrarily determined.