JPS5964980A - Tuning controller for television - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION The present invention uses a counter to measure the information-bearing carrier frequency of an IF signal and thereby correct for the frequency shift of the information-bearing carrier. The present invention relates to a digital automatic fine tuning (AFT) device that generates a tuning control signal.

Digital AFT devices of the type described above are associated with analog AFT devices commonly used in television and radio receivers in that they can dispense with expensive discrete circuitry that must be precisely aligned. This is preferable. Digital AFT devices can also incorporate important parts of the tuning control system of a receiver or receivers (hereinafter collectively referred to as receivers) into the digital signal processing circuitry of other parts of the receiver. It is also preferable from this point of view.

One problem that arises in such digital AFT devices is that when the information-bearing carrier of the received RF signal is overmodulated, the corresponding information-bearing carrier of the IF signal is also overmodulated and has a very small amplitude. The counter used to measure that frequency will no longer be able to reliably respond to it. In television receivers, for example, this results in perturbing disturbances in the tuning process that can lead to corresponding disturbances in the video and audio responsiveness.

SUMMARY OF THE INVENTION According to the principles of the present invention, there is provided a digital AFT device for a television receiver that is capable of measuring the frequency of an information-bearing carrier wave of an IF signal during a retrace interval, such as a portion of a vertical retrace interval. is provided. During this period, the video carrier tends not to be overmodulated and therefore has a suitable amplitude for reliable frequency measurements.

In other embodiments, a single counting device is selectively used to measure the frequency of both the LO and IF signals during each period. More particularly, prior to a first measurement period during which the LO signal frequency is to be measured, a numerical value relating to the desired frequency of the LO signal is provided to the counting device, and a second measurement period during which the frequency is measured. Prior to this, a value associated with the desired frequency of the IF signal is applied to the same counting device. During each measurement period, a respective one of the LO or IF signals is applied to the counting device, so that the counting device can responsively count from the initially provided value. At the end of each measurement period, irrespective of the signal being measured, the count of the counting device is compared with the same predetermined count and the deviation, if any, of the signal being measured from the respective desired frequency is determined. A signal representing the deviation is generated as an error signal.

When the invention is used in a television receiver, the counting device is controlled in response to a deflection synchronization pulse to adjust the frequency of the LO signal during the retrace period during which the frequency of the video carrier of the IF signal is measured. It is advisable to take measurements repeatedly, excluding certain parts.

The video carrier has less tendency to be overmodulated during the retrace period;
On the other hand, since there is a tendency for overmodulation during the video period between retrace periods, the frequency of the IF signal can be relatively reliably measured during the retrace period.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

<Description of Embodiments> In the drawings, hatched areas on lines connecting blocks indicate the presence of a large number of signal lines.

In FIG. 1, an RF signal source 1 supplies a plurality of RF television signals to a television receiver corresponding to each channel. Each RF signal includes modulated video, color, and audio carriers. The RF signal provided by the RF signal source 1 is fed to an RF amplifier 3, which
The amplifier is tuned in response to a tuning voltage (TV) to select one of the RF signals corresponding to the channel selected by the user. The selected RF signal is supplied to mixer 5. The mixer 5 is also supplied with a local oscillation signal generated by a local oscillator 7.

Local oscillator 7 is responsive to the tuning voltage to control the frequency of the local oscillator signal according to the selected channel. The mixer 5 heterodynes the RF signal selected by the RF amplifier 3 and the local oscillation signal generated by the local oscillator 7 to produce modulated video, color, and color signals corresponding to the video, color, and audio carriers of the selected RF signal. and generates an IF signal including an audio carrier. In the United States, the nominal frequency of the video carrier is 45.75 MHz. The color carrier has a nominal frequency of 42.17 MHz and the audio carrier has a nominal frequency of 41.25 MHz.

RF amplifier 3 and local oscillator 7 each include a tuning circuit for determining its frequency response. Each tuned circuit includes an inductor and a voltage controlled capacitance diode, commonly referred to as a varactor diode. The varactor diode is reverse biased by the tuning voltage so that it exhibits capacitive reactance. The magnitude of the tuning voltage determines the magnitude of the capacitive reactance and thus the frequency response of the tuned circuit. Since a single varactor-controlled tuning circuit arrangement cannot tune over the entire television range, separate tuning circuit arrangements are selectively tuned in response to band-select control signals generated according to the frequency band of the selected channel. is energized by

The IF signal generated by the mixer 5 is supplied to an IF filter 9 for filtering the received IF signal. The filtered IF signal is amplified by an IF amplifier 11 and supplied to a video detector 13.

Video detector 13 demodulates the filtered and amplified IF signal to generate a baseband video signal representing luminance, chrominance, and synchronization information. The baseband video signal is supplied to a video processing unit 15 and a synchronization signal separator 17. The IF signal is also used by the audio processing unit 1
9, and extracts audio information from the IF signal to generate an audio signal.

The audio signal is amplified by audio processing unit 19 and supplied to speaker 21 .

The video processing unit 15 separates the baseband video signal into signals representing luminance and chrominance information, and processes the separated luminance and chrominance signals into R, G, and B signals representing red, green, and blue information, respectively. generate. The R, G, and B signals are supplied to each electron gun of the picture tube 23, and the picture tube 23 generates an electron beam in response to these signals.

The sync separator 17 extracts a composite video sync signal (5a) containing horizontal and vertical sync pulses from the baseband video signal.
(shown in the figure). The composite synchronization signal is fed to a deflection unit 25 which generates horizontal and vertical deflection signals. The deflection signal is supplied to a deflection coil 27 attached to the picture tube 23, which deflects the electron beam generated by the electron gun of the picture tube 23 in a conventional raster pattern. More specifically, the horizontal and vertical deflection signals cause the electron beam generated by the electron gun of the picture tube 23 to scan horizontally in successive scan lines. After each scan line, the electron beam is retraced to the starting point of the next adjacent scan line below. At the end of a complete field of scanlines (525 in the US)
In this case, the electron beam is returned to the top of the next field during the vertical retrace period.

Planking unit 29 is responsive to horizontal and vertical deflection signals generated within deflection unit 25 to generate horizontal and vertical planking signals during horizontal and vertical retrace periods, respectively. A planking pulse is provided to the video processing unit 15 to inhibit the video from appearing during the retrace period.

The above-mentioned parts of the television receiver shown in FIG. 1 are ordinary parts and do not require further explanation. The remaining portion of the television receiver shown in FIG. 1 consists of a tuning control system for supplying tuning voltage and band switching signals to the RF amplifier 3 and local oscillator 7.

Basically, the tuning control system includes two frequency locked loops (FLL). When a new channel is selected, the first FLL is energized into operation. 1st FL
L measures the frequency of the local oscillator (LO) signal and generates a control signal that controls the magnitude of the tuning voltage until the frequency of the LO signal is within a predetermined range of nominal values for the selected channel. Once the operation of the first FLL is complete, the second FLL is energized and activated. The second FLL measures the frequency of the video carrier of the IF signal and generates a control signal that controls the magnitude of the tuning voltage until the frequency of the video carrier is within a predetermined range of its nominal value.

The first FLL is the nominal LO for the selected channel.
Combine frequencies. The nominal LO frequency is the frequency required to tune the broadcast RF signal serving each channel. In the United States, broadcast RF signals are required by the Federal Communications Commission to have highly accurate standard frequencies. The second FLL is capable of automatically fine-tuning the receiver of RF signals that are offset in frequency with respect to each broadcast RF signal. Such non-standard frequency RF carrier waves are provided by potential RF signal sources 1 such as cable or mask antenna television equipment, video tapes, disc players, video games, home computers, etc.

According to a feature of the invention, the first and second FLLs share a common frequency sampler 30;
0 measures the frequency of the LO signal during operation in the composite mode, and measures the frequency of the video carrier of the IF signal during operation in the automatic fine tuning (AFT) mode. Frequency sampler 30 responds to a high logic level "Synthesis Enable" control signal to
It measures the frequency of the signal and is selectively activated to measure the frequency of the IF signal in response to a high logic level "AFT Activate" signal. The "composite energization" and "AFT energization" control signals are generated by the tuning control unit 45 in the manner described below.

A first frequency divider or prescaler 33 of the LO signal is provided. The prescaler 33 divides the frequency of the LO signal and generates a frequency-divided version of the LO signal that is supplied to the frequency sampler 30. The IF signal is provided to a second frequency divider or prescaler 65.

The prescaler 65 divides the frequency of the IF signal by a second frequency division coefficient, and generates a frequency-divided version of the ①F signal that is supplied to the frequency sampler 30. Since the primary carrier in the IF signal is the video carrier, prescaler 65 will be responsive to the video carrier rather than other carriers in the IF signal. Therefore, the output of the prescaler 65 is actually the frequency-divided image carrier wave of the IF signal. The first and second frequency division coefficients of the prescalers 33 and 65 are:
Each frequency-divided signal supplied to the frequency sampler 30 is
The frequency is selected to have a frequency within the operating frequency range of the frequency sampler 30. The first suitable for use in the United States
and the second frequency division coefficient is 256 and 8 as shown in FIG. Using such a division factor, prescaler 33 generates one pulse every 256 cycles of the LO signal, and prescaler 65 generates one pulse every 8 cycles of the video carrier of the IF signal.

Since the video carrier of the received RF signal is overmodulated, the video carrier of the IF signal is correspondingly overmodulated.

Therefore, the amplitude of the video carrier of the IF signal may be so low that prescaler 65, and therefore frequency sampler 30, cannot reliably respond to it.

Reliable frequency measurements of the video carrier of the IF signal are obtained by the frequency sampler 30, so that the video carrier is less likely to be overmodulated and therefore has a relatively high amplitude vertical In the AFT mode of operation during only a portion of the retrace interval, frequency sampler 30 is selectively activated to make frequency measurements of the IF signal. For this purpose, the composite synchronization signal generated by the synchronization separator 17 is fed to a vertical pulse detector 71. At the beginning of a vertical retrace period, vertical pulse detector 71 generates a vertical pulse that is provided to LO1 frequency sampler 30. The vertical pulse is applied to the IF during a predetermined period of the vertical retrace period, as shown in FIG. 5a.
Start measuring the frequency of the video carrier of the signal.

In FIG. 5a, waveform A shows a typical baseband video signal with particular emphasis on the vertical blanking period. The amplitude of the video signal between successive horizontal sync pulses (separated by horizontal scanning periods H) can be very low according to the modulation of the video carrier. However, during the vertical blanking period, the amplitude of the video signal is relatively high. As shown in waveform B, the vertical pulse occurs immediately after the end of the first vertical sync pulse of the vertical retrace period. As shown in waveform E,
The LO frequency measurement period begins a short time after the occurrence of the vertical pulse and ends just before the portion of the vertical retrace interval allocated to teletext and test signal information. This means that
Desirably, the video carrier wave is overmodulated by the teletext and test signal as shown by the phantom lines in the teletext and test signal period of waveform A.

As will be described in more detail with reference to FIGS. 2 and 3, the frequency sampler 30 receives pulses of either a frequency-divided version of the LO signal or a frequency-divided version of the IF signal during each measurement period. Selectively energized for counting. The measurement period is from the reference counter 35 to the frequency sampler 30.
is set by a timing signal supplied to the Reference counter 35 generates a timing signal by continuously dividing the frequency of the reference frequency signal generated by crystal controlled oscillator 37. As an example, the first
As shown in the figure, the crystal controlled oscillator 37 has a frequency of 4MHz.
The reference frequency signal is configured to generate a reference frequency signal. The lowest frequency timing signal generated by reference counter 35 has a frequency of 488.3 Hz (4 MHz ÷ 213), or a period of 2048 microseconds, which is R
is shown. Other timing signals used in the illustrated configuration are designated 2R, 4R, 64R, 256R, where the coefficients of R represent the reciprocal relationship to the period of R of the period of the specific timing [5]. It is. for example,
2R has a period of 1024 microseconds and 4R has a period of 512 microseconds.
It has a period of microseconds, 64R has a period of 32 microseconds, and 256R has a period of 8 microseconds.

Immediately before the measurement, the counter device is preset to a respective predetermined state corresponding to a number related to the nominal shield frequency of the signal to be measured. Although the nominal frequency of the video carrier of the IF signal is the same for each channel, the LO
The nominal frequency of the signal is different for each channel. Therefore,
To determine the state to which the counter device should be preset just before the LO frequency measurement period, a binary signal representing the channel number and the frequency band of the selected channel is sent to the channel number register 41 and the band decoder 50.
are respectively supplied to the frequency sampler 30.

During the measurement period, the count of the counter device decreases in response to pulses of the divided version of the signal being measured. Immediately after the end of the measurement period, the count of the counter device is examined to determine the frequency error, if any, of the measured signal. If the counter reaches a count value of 0 during the measurement period, the counter wraps around to the initial count value and a higher count value is generated at the end of the measurement period.

If the frequency of the measured signal is low, the count value will be low and a corresponding "low count" error pulse will be generated.

If the frequency of the measured signal is high, the count value will be high and a "high count" error pulse will be generated.

The high count and low count error pulses are provided to the down and up control inputs of up/down counter 55, respectively. The contents of up/down counter 55 decreases in response to high count error pulses. The contents of up/down counter 55 increases in response to low count error pulses. The contents of the counter 55 are the binary rate multiplier (B
RM) 57. The BRM 57 is also supplied with a 4 MHz reference frequency signal from the crystal oscillator 37. The BRM 57 generates a pulse signal having a number of pulses during a predetermined period according to the contents of the up/down counter 55. The pulse signal generated by BRM57 is
It is supplied to a low pass filter (LPF) 59 which filters the received pulse signal and generates a DC signal.

The DC signal is supplied to an amplifier 61, which amplifies the DC signal to generate a tuning voltage.

A channel is selected by a channel selector 43 consisting of a keyboard, such as a calculator, and the two decimal numbers corresponding to the channel selected by this keyboard are entered into a channel number register 41.

The binary number representative of the selected channel number stored in the channel number register 41 is provided to the band decoder 50 as well as the frequency sampler 30. Band decoder 50 generates a binary signal representing the band of the selected channel, which binary signal is provided to RF amplifier 3, local oscillator 7, and frequency sampler 30. For example, for television receivers used in the United States.

Band decoder 50 generates high logic level signals VLL for VHF channels 2, 3, and 4, generates high logic level signals VLH for VHF channels 5, 6, and
High logic level signal V for HF channels 7-13
H and generates a high logic level signal U for UHF channels 14-83.

Each time a new channel is selected, channel selector 43 generates a high level new channel signal and supplies it to control unit 45. In response to control unit 45, the composite enable signal is caused to have a high logic level. This causes frequency sampler 30 to measure the frequency of the LO signal. In response to a high count, low count error pulse generated by frequency sampler 30, the contents of up/down counter 55, and thus the magnitude of the tuning voltage, are adjusted so that the frequency of the LO signal is within a predetermined range of its nominal frequency. It is adjusted until it goes inside. At that point, the tuning control unit 45 causes the composite enable signal to have a low logic level and the AFT enable signal to have a high logic level. This causes the frequency sampler 30 to be deenergized and measure the frequency of the IF signal. however,
The frequency of the IF signal is not actually measured until a vertical pulse is generated by vertical pulse detector 71 during the vertical retrace interval.

The high count and low count error pulses generated according to the frequency measurement of the IF signal are fed to an up/down counter 55 to determine its content, thereby reducing the LO until the frequency of the video carrier is within its nominal value. Determine the magnitude of the tuning voltage to measure the frequency of the signal.

During the AFT operating mode, the frequency sampler 30 detects the LO signal when the AF signal is at a high logic level, except when it is configured to measure the frequency of the video carrier of the F signal during the vertical retrace period. Measure frequency. This is L
It is performed to determine whether the frequency of the O signal is changed by a predetermined deviation, for example ±1.25 MHz, from the set value during the composite mode of operation.

If a predetermined shift in the frequency of the LO signal is detected, frequency sampler 30 generates an offset pulse that is supplied to tuning control unit 45. In response, tuning control unit 45 terminates the high logic level of the AFT activation control signal and again generates a high logic level composite activation control signal. This restarts the composite operation mode.

UP/DOWN COUNTER 55 DURING SYNTHETIC OPERATION MODE
, BRM 57 and LPF 59, are generated by tuning control unit 45 to rapidly synthesize the nominal LO frequency for the selected channel, as described in more detail below with reference to FIG. They are responsive to "coarse tuning,""mediumtuning," and "fine tuning" control signals, respectively. The groups of lower stages of up/down counter 55 are sequentially activated in response to the "high count" and "low count" error pulses. The tuning control unit 45 sequentially generates coarse tuning, intermediate tuning, and fine tuning control signals by sensing when the polarity of the error pulse generated by the frequency sampler 30 changes during the change period of the synthetic operation mode. .

The composite energization signal and the AFT energization signal are also provided to the LPF 59 from the tuning control unit 45. The purpose of this is
It consists in changing the time constant of the low-pass filter for different operating modes. In particular, for a synthesis mode of operation in which the removal of pulse components from the DC signal provided to amplifier 61 is less stringent, the bandwidth of LPF 59 is made relatively wide in response to the high logic level of the synthesis enable signal. . However, a fine tuning voltage is generated and the pulse components appearing in the tuning voltage cause visible interference to the reproduced video.
For FT operation mode, the bandwidth of LPF59 is AF
It is made relatively narrow in response to a high level of the T-energization signal.

Next, a partial configuration of the frequency sampler 30 shown in FIG. 2 will be explained. The counter device shown here is
It includes a counter 201 and an auxiliary down counter 203.

The main multiplexer (MUX) or switch receives a BCD signal (binary coded decimal) representing the channel number of the selected channel, a BCD signal representing the band of the selected channel (for example, in the US, low 89 for low VHF channels 5-6, 93 for high VHF channels 7-13, 1 for high VHF channels 7-13
79, 433 for UHF channels 14-83)
, or a BCD signal representing a number (e.g., 366 in the US) related to the number of cycles of the divided version of the IF signal's video carrier occurring during the IF signal frequency measurement period. "signal,
High logic level “band select” signal, and high logic level “
The maximum number represented by the BCD signal applied to the Nyam input of main down counter 201 is shown in FIG. 3 digit number as shown, so main counter 201 becomes a 3 digit decimal down counter. As previously discussed with respect to FIG. 1, the BCDI signal representing the channel number is stored in channel register 41. A BCD signal representing a number bar related to the band is generated by logic circuitry shown as band number 207 in response to a band selection signal generated by band decoder 50. A BCC signal representing a number related to the IF video carrier frequency is , is generated by a logic circuit shown as main IF number 209.

The “zero count” detector 211 is connected to the main down counter 20
When the count value included in 1 is equal to 0, a high logic level "main count=0" signal is generated. “>5” detector 21
3 means that the count value included in the main down counter 201 is 5.
In this case, a high logic level "main count value>5" signal is generated. The "<maximum-4" detector 215 generates a high logic level "main count <maximum-4" signal when the count contained in the main down counter 201 is less than the maximum count -4.

Main counter 201, main multiplexer 205, logic circuits 207 and 209, and detectors 211.213.2
15 logic circuits are shown in Figure 7a.

Auxiliary multiplexer (AUX MUX) 217 is a "synthesis and shift" used in connection with measuring the LO frequency in the synthesis mode of operation to generate error pulses and in the AFT mode of operation for detecting the shift in the LO frequency. a binary signal representing a first number in the form of a linear binary code, or AF
a binary signal representing in the form of a linear binary code a second number designated as an "auxiliary IF number" (e.g. 4) used in connection with the measurement of the IF video carrier in the T mode of operation;
It is selectively applied to the jam input of auxiliary down counter 203 in response to a control signal designated as "IF Cycle". the control signal "IF Cycle" has a high logic level except during the portion of the vertical retrace period when the IF frequency is measured;
During portions of the vertical retrace interval, the "IF Cycle" control signal is at a low logic level (waveform G in Figure 5a). “I
When the F-CyclePa control signal is at a high logic level, auxiliary multiplexer 217 provides a binary signal representing the "combined and offset" value to the jam input of auxiliary down counter 203. When the “IF Cycle” control signal is at a low logic level, the auxiliary multiplexer 217
An auxiliary down counter 203 outputs a binary signal representing the value of
feeds the jam input. A binary signal representing the "synthesis and offset" value is generated by logic circuit 219.

A binary signal representing the "auxiliary IF number" is generated by logic circuit 221.

The maximum number represented by the binary signal provided to auxiliary down counter 203 in the embodiment shown in FIG. 2 is 28, and auxiliary counter 203 is a five stage down counter as shown.

“1” detector 223 detects a high logic level “auxiliary count value=
The inverter 225 inverts the “auxiliary count value=1” signal and generates the “auxiliary count value=1” signal. The “4” detector 227 is included in the auxiliary counter 203. When the count value is equal to 4, a high logic level "auxiliary count value=4" signal is generated.

The logic circuit configuration of auxiliary counter 203, auxiliary multiplexer 217, logic circuits 219 and 221, and detectors 223 and 227 is shown in FIG. 7b.

Before describing the remaining configuration shown in FIG. 2 and the configuration of FIG. 3, it is useful to explain their general basic operation.

As previously explained, during each frequency measurement operation, the counter circuit of the frequency sampler 30 essentially responds to pulses of the frequency-divided version of the signal being measured during the measurement period to a predetermined value. energized to count down from Immediately before the measurement period, the counter circuit is given a predetermined value and set to that value (hereinafter this will simply be referred to as "loaded"). After the end of the measurement period, the count of the counter circuit is examined to determine the one frequency error, if any.

With particular reference to FIG. 2, a predetermined number is used to convert the binary signal applied to the jam input of main down counter 201 into a positive direction "jam up" signal applied to the preset (PR) input of this counter 201. The preset (
PR) by loading the auxiliary down counter 203 from the auxiliary multiplexer 217 with a binary signal applied to the jam input of the auxiliary down counter 203 in response to a positive "jam enable" signal applied to the input. Set. The binary signal then applied to the jam inputs of the counters 201, 203 depends on whether the frequency of the LO signal or the IF signal is to be measured. Thereafter, in response to a high logic level of the "Counter Enable" signal, the divided version of the signal to be measured is passed through a gate circuit to the main down counter 201's clock (
C) supplied to the input. As long as the "Force Counter Enable" signal is at a high logic level, the count of the main down counter 201 decreases by one in response to each pulse of the divided signal being measured. The high level period of the "count enable" signal depends on the signal being measured. Each time the count value of the counter 201 becomes equal to 0, the auxiliary down counter 20
The count of 3 is decremented by 1 and a "jam enable" signal is generated for the main counter.

Auxiliary counter 203 generates a binary signal that is applied to the jam input of main counter 201. At that point, the binary signal provided by the main multiplexer 205 to the jam input of the main counter 201 depends on whether the frequency of the LO signal or the IF signal is being measured, and the It depends on the specific count value of the auxiliary counter 203 when the frequency is being measured.

When the high logic level of the counter enable pulse ends at the end of the measurement period, the divided version of the signal being measured is disconnected from the clock input of the main counter 201. after that,
In response to the sample pulse, the contents of main counter 201 are examined by the arrangement shown in FIG. Main counter 2
Depending on the contents of 01 and whether the frequency of the LO signal or the frequency of the IF signal is being measured, the configuration in Fig. 3 can be changed to “
Generates a high/high teaching value” or “low count value” error pulse or “offset” pulse.

When the frequency of the LO signal is at the nominal value for the selected channel, for example 25
If we use a LO prescaler division factor of 6, the number of cycles of the divided version of the LO signal that occurs during a measurement period that has a duration of 1024 microseconds, for example, is equal to the nominal LO
It is equal to four times the frequency (MHz) of the frequency.

The counter device shown in FIG. 2, which consists of a main counter 201 and an auxiliary counter 203, takes advantage of the fact that the channels in each band of the television area are evenly separated in the frequency band, and calculates the LO for each channel.
Without requiring a relatively large ROM to measure the frequency, the counter device can be energized to determine the nominal LO frequency (
The frequency of the LO signal is measured by counting down from a preset number equal to 4 times MHz). More specifically, L for each channel
The O frequency fLO is expressed by the following equation.

fLO = (channel number) (fractional separation) + band dependent constant (1) Therefore, as an example, using a LO prescaler division factor of 256 and a measurement period of 1024 microseconds, the preset number of each channel is expressed by the following equation.

Preset number = (4) (channel number) (frequency separation) + band-dependent constant (2) As an example, according to equation (2), the nominal frequency of the LO signal for broadcast channels in the United States is as follows: Indicated by

Using the values shown in the table above, equation (2) becomes as follows.

Preset number = (24) (channel number) + (4
) (bandwidth constant) (3) With equation (3) in mind, the operation of the configuration of FIG. 2 for measuring the frequency of the LO signal is as follows.

Just before the LO frequency measurement period, a binary signal representing the channel number provided by channel number register 41 is loaded into main down counter 201, and a binary signal representing 28 (i.e. 24+4) provided by logic circuit 219 is Auxiliary countdown counter 20
Loaded with 3. During measurement of the LO frequency, a divided version of the LO signal is provided to the clock input of the raw down counter 201.

In response to each pulse of the divided version of the LO signal, the count of the king down counter 201 is decremented by one. During the measurement period, the count value of the auxiliary counter 203 decreases each time the count value of the main down counter 201 reaches O until the count value of the auxiliary counter 203 reaches 1. Furthermore, when the count value of the main down counter 201 reaches 0, the binary signal representing the channel number is loaded onto the main down counter 201 again until the count value of the auxiliary counter 203 reaches 4. When the count of the auxiliary down counter reaches 4, a binary signal representing a band dependent constant provided by logic circuit 207 is loaded into the main down counter 201. Thereafter, the count value of the auxiliary counter 203 continues to be decremented until the count value of the auxiliary counter 203 reaches zero, and the count value of the main down counter 201 reaches zero. If the LO frequency is at its nominal value, when the measurement period ends, the count value of the main down counter 201 will be exactly 0 during the period when the count value of the auxiliary counter 203 becomes 1 according to equation (3) above. reach.

Depending on the actual LO frequency, at the end of the measurement period, the logic configuration shown in FIG. Generates an “offset” pulse.

Main down counter 201 and auxiliary down counter 203 are also used to measure the frequency of the IF signal's stock carrier. If the video carrier frequency is nominally 45.75 MHz in the United States, and the IF prescaler division factor is 8, as illustrated with respect to FIG.
For example, the number of cycles of the divided IF signal generated within a measurement period of 256 microseconds is 1464, or (
4) (366).

The operation of the circuit arrangement of FIG. 2 for measuring the frequency of the IF video carrier will be described with a count value of 1464 in mind, which corresponds to the nominal frequency of the IF video carrier. Just before the IF frequency measurement period, the logic circuit 209 represents the numerical value 366.
The binary signal generated by the main down counter 20
A binary signal loaded with a 1 and representing the number 4 generated by logic circuit 221 is loaded into auxiliary down counter 203. During the measurement of the IF frequency, in response to each pulse of the divided IF signal, the main down counter 2
The count value of 01 is decremented by one. Until the count value of the auxiliary down counter 203 reaches 1, when the count value of the main down counter 201 reaches O, the count value of the auxiliary down counter 203 is decreased by 1, and the count value generated by the logic circuit 209 The binary signal representing 366 is again loaded into the main down counter 201. During the period when the count value of the auxiliary down counter 203 is 1, if the frequency of the video carrier of the IF signal is at its nominal value, the count value of the main down counter 201 will be exactly at the end of the IF frequency measurement period. reaches 0. Depending on the actual frequency of the IF video carrier, at the end of the IF frequency measurement period, the configuration shown in FIG. 3 will generate either a "high count" or a "low count" error pulse.

As explained below, the configuration shown in Figure 4 generates the "LO Counter Preset", "LO Counter Enable" and "LO Counter Sample" pulse signals as shown in Figure 4a, and the LO signal counters 201 and 203 are controlled to measure the frequency of . The LO counter preset pulse causes counters 201 and 203 to
Load with a suitable binary signal just before the O frequency measurement period. The high logic level "LO Power Counter Enable" pulse enables a subdivided version of the LO signal to be provided to the clock (C) input of the main down counter 201, thereby sustaining the LO frequency measurement period. Decide on the period. The "LO Counter Zumble" pulse occurs immediately after the end of the LO frequency measurement period, and the circuit configuration of FIG. 3 determines the count value of the main down counter 201 to generate an error pulse. In response to the 4R, 2R, R timing signals generated by the reference counter 35 shown in FIG. 1, the configuration shown in FIG. is generated.

As discussed below, the configuration shown in FIG.
, and “sample” pulses, which are passed to a counter 201 that measures the frequency of the IF video carrier.
, 203 has the same function as its LO counter pulse counterpart. Additionally, the configuration of FIG. 5 also generates an "IF cycle" pulse (waveform G) shown diagrammatically in FIG. sample" has a period that encompasses the pulse. The IF counter pulse is also generated by the reference counter 35 64
Generated in response to the R timing signal. Unlike the LO counter pulses, the IF counter pulses are not generated continuously, but rather selectively in response to "vertical" pulses (waveform B), e.g. starting after the first vertical sync pulse, Occurs only during a portion of the vertical retrace period that ends just before the teletext and test signal (waveform A
and G). The IF counter pulses ensure that any overmodulation of the IF video carrier does not adversely affect the ability of the main down counter 201 to count pulses of the divided version of the IF signal. “IF cycle”
The pulse (waveform G) has the configuration shown in FIGS.
Used to avoid responding to LO counter pulses during F frequency measurement operations.

Next, the operation will be explained mainly with reference to the circuit shown in FIG. “LO counter preset” signal is a set-reset flip-flop (S-RFF) set (S)
input and one input of OR gate 231. The output of OR gate 231 is provided to the reset (R) input of S-RFF 233. A "channel number selection" signal is generated at the Q output of S-RFF 229, and a "band number selection" signal is generated at the Q output of S-RFF 231.

The “auxiliary count=4” signal generated by detector 227 is provided to one input of OR gate 235. The output of OR gate 235 is fed to the reset (R) input of S-RFF 231. The "IF Cycle" signal is provided to the second input of OR gates 231 and 235.

The IF CYCLE signal is at a low logic level except during its frequency determination operation and is at a high logic level during its frequency measurement operation. The high logic level "IF cycle" signal passes through OR gates 231 and 235 to S-RFF2, respectively.
29.233 is fed to the reset (R) input of 233, keeping each of their FFs in reset so that they are at high level “LO Counter Preset” and “Auxiliary Count=
4” so that it cannot respond to the signal.

Assuming a moment when the “IF Cycle” signal is at a low logic level, when the “LO Counter Preset” pulse occurs, i.e. when the “LO Counter Preset” signal is at a high logic level, the S-RFF 229 is set and the
-RFF233 is reset. As a result, the "Channel Number Selection" signal will be at a high logic level and the "Band Number Selection" signal will be at a low logic level. Therefore, in response to the "LO Counter Preset" pulse, the main multiplexer 205 provides a binary signal representing the number of the channel stored in the channel number register 41 to the "jam" input of the main down counter 201.

As mentioned earlier, the “IF cycle” signal, i.e. “
The complementary signal of the “IF cycle” signal is sent to the auxiliary multiplexer 21.
7 control inputs. Assuming that the "IF Cycle" signal is at a low logic level, the "IF Cycle" signal will be at a high logic level.

This provides a binary signal representing a "composite and offset number", for example 28, provided by logic circuit 219 to the "jam" input of auxiliary down counter 203.

The "LO counter preset" signal and the "■F-cycle" signal are supplied to each input of AND gate 237. The output of AND gate 237 is OR gate 239
is fed to the input of The output of OR gate 239 is S-
RFF241 set (S) input and OR gate 2
43 is fed to one input. Q of S-RFF241
The output is the preset (PR) of the main down counter 201
supplied to the input.

The output of OR gate 243 is the output of auxiliary down counter 20
3 preset (PR) input. Therefore, and assuming that the IF Cycle signal is at a high logic level, when the LO Counter Preset Pulse appears, the binary signal representing the channel number to be loaded into the main down counter 201, the Combined and Offset A binary signal representing a numerical value, for example 28, is loaded into an auxiliary down counter 203.

The frequency-divided version of the LO signal (fLO/256), “LO
A counter valid" signal and an "IF cycle" signal are provided to each input of AND gate 245.

The output of AND gate 245 is 1 of OR gate 247.
fed into two inputs. The output of OR gate 247 is coupled to the clock (C) input of main down counter 201. Therefore, again assuming the "IF Cycle" signal is at a low logic level, when the "IF Counter Enable Signal" is at a high logic level, the LO signal divided is the main down signal.
It is supplied to the clock (C) input of counter 201. Thereafter, the count of main down counter 201 is decremented by one in response to each pulse of the divided version of the LO signal.

Zero detector 211 associated with main down counter 201
, one detector 22 associated with an auxiliary down counter 203
The output of inverter 225, which inverts the output signal of 3, is provided to each input of AND gate 249.

The output of AND gate 249 is Urasuke down counter 2
03 and the second input of OR gate 239. AND gate 249 is energized so that “auxiliary count value=1” occurs at the output of inverter 225.
” is at a high logic level, the “main count value = 0” signal at a high level, which is generated at the output of main detector 211, is passed through. As mentioned earlier, the output of OR gate 239 is at a high logic level. When , S-RFF 241 is set to cause the "jam enable signal" generated at the preset (PR) input of main down counter 201 to go to a high logic level.

Therefore, each time the count value of the main down counter 201 becomes equal to 0, the count value of the auxiliary down counter 203 becomes 0.
, the count value of the auxiliary down counter 203 is decremented by 1, and the binary signal supplied from the main multiplexer 205 to the jam input of the main down counter 201 is loaded onto the main down counter 201. Ru.

The output of OR gate 247 is also provided to the input of inverter 251. The output of inverter 251 is S-RFF2
41's reset (R) input.

As a result, for example, when the count value of the main down counter 201 reaches 0, the S-RFF 241 is set in response to a high logic level "main count value=O" signal, and then the main down counter 201 It is reset in approximately 1/2 cycle of the cycle of the frequency-divided signal supplied to the clock (C) input of . This causes the main down counter 2
The “jam enable” signal for 01 is the main down counter 2
The binary signal applied to the jam input of 01 lasts long enough to be loaded into its counter 201, but the next one of the divided ones applied to the clock (C) input of the main down counter It will now end before the pulse is generated. This means that during the measurement period of the frequency of the LO signal, the main down counter 201 presets the channel number between pulses of the frequency-divided version of the LO signal every time the count value of the auxiliary down counter 203 reaches 0. This is important because it must be preset to the band number when the count value of the auxiliary counter 203 reaches 4. The latter case (2) in which the count value of the auxiliary counter 203 reaches 4 will be explained using a specific embodiment shown in FIG.

“Auxiliary count value = 4” signal is S from the output of 4 detector 227
- fed to the set (S) input of RFF 233 and the input of OR gate 235; When the count value of auxiliary counter 203 reaches 4, the high logic level generated at the output of detector 227 is fed to the set (S) input of S-RFF 233 and also via OR gate 235 to S-RFF 229.
is supplied to the reset (R) input of This allows S-
RFF233 is set. As a result, assuming the "IF Cycle" signal is at a low logic level, only the "Number of Bands Select" control signal of main multiplexer 205 will be at a high logic level. This causes main multiplexer 205 to provide a binary signal representing the band number provided by logic circuit 207 to the jam input of raw down counter 201 . When the count value of the main down counter 201 reaches a new count value that causes the count value of the auxiliary counter 203 to be 4, a "jam enable" signal for the main down counter 201 is generated at the Q output of the S-RFF 241. is set to a high logic level, so a binary signal representing the band number is loaded into the main down counter 201. Thereafter, the count of main down counter 201 is decremented by one in response to each pulse of the divided version of the LO signal.

Each time the count value of the main down counter 201 reaches 0, the count value of the auxiliary down counter 203 decreases by 1 until the count value of the auxiliary down counter 203 reaches 1, and a binary signal representing the number of bands is generated. reloads the main down counter 201 in response to a high level “main count value = 0” signal applied to the clock (C) input of the auxiliary counter 203 via the AND gate 249 and to the input of the OR gate 239. be done.

When the count value of the auxiliary down counter 203 reaches 1, the AND gate 249 is deactivated and “Main counter=0
” is the high logic level signal of the auxiliary down counter 203.
clock (C) input and OR gate 239.

Upon termination of the high logic level "LO Counter Enable" signal, the divided version of the LO signal is routed to the main down counter 20.
1's clock (C) input. “LO counter activation” with “LO counter sample” pulse at high level
Occurring immediately after the termination of the signal, the logic arrangement of FIG. 3 examines the count of the main counter 201 and determines whether either the "Attached or Energized" control signal or the "AFT Energized" control signal is at a high logic level. and the counting of main down counter 201 to selectively generate or not generate appropriate error or "offset" pulses. Third
The logical structure of the diagram will be described in detail below.

Returning to the IF "frequency measurement operation," the "IF cycle" signal is sent to the main multiplexer 2 as the "IF numerical selection" control signal.
05. When a high logic level “■F cycle” signal is generated, the S-RFFs 229 and 233 are reset, and the “main channel selection” and “band number selection” control signals supplied to the main multiplexer 205 are set to a low logic level, and the main “IF” supplied to multiplexer 205
``Number Select'' signal to a high logic level. Therefore, the main multiplexer 205 transfers the main IF value, for example 366, provided by the logic circuit 209 to the main down counter 205.
feeds the jam input. When the "IF Cycle" signal is at a high logic level, the "IF Cycle" signal is at a low logic level. Therefore, the auxiliary multiplexer 217 provides a binary signal representing the auxiliary IF value, eg, 4, to the jam input of the auxiliary down counter 203.

When a high logic level "IF Counter Preset" pulse is generated, this pulse is applied to the preset (PR) input of the main down counter 201 via OR gate 239 and to the auxiliary down counter via OR gate 243. It is supplied to the preset (PR) input of counter 203. Therefore, binary values representing the main and auxiliary IF values are loaded into counters 201 and 203, respectively.

The “IF Counter Enable” signal and the divided version of the IF signal (fIF/8) are provided to each input of AND gate 253. The output of AND gate 253 is provided to the second input of OR gate 247.

When a high logic level “IF Enable” signal is generated, the IF
The divided version of the signal is provided to the clock (C) input of main down counter 201 via AND gate 253 and OR gate 247. In response to each divided pulse of the IF signal, the count of main down counter 201 is decremented by one. The count value of the main counter 201 is 0
Whenever the count value of the auxiliary counter 203 reaches 1, the “main count value = 0” signal at a high logic level is ANDed.
through gate 249 to the clock (C) input of auxiliary down counter 203, and also to AND gate 249.
and is supplied to the set (S) input of S-RFF 241 via OR gate 239. As a result, the count value of the auxiliary down counter 203 is decreased by one, and a binary signal representing the band number is loaded onto the main counter 201. Upon termination of the high logic level "IF Counter Enable" signal, AND gate 253 disconnects the divided local oscillator signal from the clock (C) input of main down counter 201. When the IF COUNTER SAMPLE pulse occurs immediately after the high logic level of the IF COUNTER ENABLE signal, the logic configuration of FIG.
Calculate the count value of and generate an appropriate error pulse or not generate both error pulses.

Next, the logical configuration of FIG. 3 will be explained. If the main counter 201 crosses the count value 0 while the count value of the auxiliary counter 203 is 1, the frequency of the determined signal is high; if it does not cross 0, the frequency is low. Therefore, the logic configuration of FIG. 3 is such that when the count value of the auxiliary counter 203 is 0 during the measurement period, a data flip is performed to determine whether the count value of the main counter 201 reaches 0 or not. It includes a flop (DFF) 301.

The DFF 301 applies an OR gate 30 to the straight curve in each measurement period.
3 to the RESET (R) input in response to high logic level LO COUNTER PRESET and IF COUNTER PRESET pulses. DF
The “auxiliary count value = 1” signal is supplied to the data (D) input of F301, and the “main count value = 1” signal is supplied to the clock (C) input of F301.
0" signal is supplied. When the count value of the auxiliary counter 203 is 1, if the main counter 201 does not reach the count value 0,
At the end of the measurement period, the DFF remains in the reset state;
Therefore, the signal generated at the Q output will be at a low logic level,
The signal generated at the Q output will be at a high logic level. When the count value of the auxiliary counter 203 reaches 1 and the count value of the main counter 201 reaches 0, the DFF 301 is activated at the end of the measurement period.
is set, so the signal produced on its Q output will be a high logic level and the signal produced on its Q output will be a low logic level.

AND gates 305 and 307 are used to generate "LO high count" or "LO low count" pulses, respectively, depending on whether the frequency of the LO signal is high or low, during the composite mode of operation. Ru. For this reason,
The "Synthesis Enable" and "LO Counter Sample" signals are provided to the respective inputs of AND gates 305 and 307, the Q output of DFF 301 is provided to the input of AND gate 305, and the Q output of DFF 301 is provided to the input of AND gates 305 and 307. - Supplied to the input of gate 307. and gate 305,
The output of 307 is applied to each first output of OR gates 309 and 311, respectively. “Low count value” and “High count value” for up/down counter 55 in the configuration of FIG.
Error pulses are generated at the outputs of OR gates 309 and 311, respectively.

AND gates 305 and 307 are activated in response to a high logic level "synthesis activated" signal and two other inputs. During the LO measurement period, when the frequency of the LO signal is at a high logic level, DFF 301 is set, its Q output is at a high logic level, and its Q output signal is at a low logic level. Therefore, immediately after the end of the measurement period, the positive “LO”
When the "counter sample" pulse occurs, it passes through AND gate 305 and OR gate 309 to the up/down counter 55 as a "high count value" error pulse.
supplied to If the frequency of the LO signal is low, at the end of the LO measurement period, the DFF 301 remains in the reset state;
Its Q output signal will be at a low logic level and its Q output signal will be at a high logic level. Therefore, when a positive going "LO Counter Sample" pulse occurs, it is
and is supplied via OR gate 311 to up/down counter 55 as a "low count" error pulse.

If the LO frequency is correct, DFF 301 is set just before the end of the LO measurement period. As a result, a "high count" error pulse is generated even if the LO frequency is correct. The logic configuration in Figure 3 is intentionally configured to operate in this way, so that either a "low count value" or a "high count value" is always generated during the composite mode of operation. The tuning voltage always overshoots its final value. The purpose of doing this will be explained with reference to the logical configuration of the tuning control unit 45.

AND gates 313 and 315 generate an "IF low count value" error pulse or an "IF high count value" error pulse, respectively, if the frequency of the video carrier wave of the IF signal is low or high during the AFT operation mode. used to generate. Therefore, the "AFT Enable" and "IF Counter Sample" signals are connected to AND gates 313 and 3.
15 inputs, the Q output of DFF301 is coupled to the input of AND gate 313, and the Q output of DFF301 is coupled to the input of AND gate 313.
The output is coupled to the input of AND gate 315.

Furthermore, the output of the inverter 317 used to invert the "main count value = 0" signal is connected to the AND gate 313.
is connected to the input of The outputs of AND gates 313 and 315 are coupled to respective second inputs of OR gates 309 and 311.

AND gates 313 and 315 cooperate with DFF 301 to provide a "low count value" and a "high count value" in substantially the same manner as AND gates 305 and 307, if the frequency of the IF video carrier is low or high. Generates an error pulse. However, due to the presence of inverter 317, if the count value of main counter 210 is 0, AND gate 313 prevents the "LO counter sample" pulse from being provided to OR gate 309, thereby interrupting the IF measurement period. At the end of , "major count=0" has a low logic level. Therefore, if the IF "image carrier frequency" is correct, neither "low count" nor "high count" error pulses will be generated.

The beginning of the measurement period is not synchronized with each divided signal. Therefore, even if the correct number of positive going pulse edges are counted in the main counter 201 during the measurement period, there may be a frequency error equivalent to one cycle of each divided signal. This is ±250KHz for LO frequency measurements.
corresponds to an accuracy of ±31 for IF frequency measurements,
This corresponds to an accuracy of 25KHz. These "accuracies are sufficient to tune a television receiver. The accuracy of frequency measurements is improved by reducing the division factor of each prescaler or by increasing the duration of each measurement period. The former method uses frequency sampler 3
1 is undesirable because it increases the frequency of the signal that must be processed. The latter is also undesirable since, under certain circumstances and for the reasons mentioned above, the ■F measurement period is extended into the teletext and test signal periods during which the IF video carrier may be overmodulated.

AND gates 319, 321 and or gates 32
3 is used in conjunction with the detectors 213 and 215 in the configuration of FIG. For example, being varied from the set point by ±1.25 MHz will generate an "offset" pulse. During the L0 frequency measurement period, as pointed out earlier,
Each count value of the main down counter 201 is 0.250MH
Corresponds to an increase in z.

Therefore, detection of a frequency deviation of ±1.25 MHz or more requires detection of a count value within ±5 count values of 0.

As mentioned earlier, if the count value of the main down counter 201 is greater than or equal to 5 at the end of the LO frequency measurement period,
5'' detector 213 generates a high logic level ``Main Count >5'' output signal. The output signal of ``>5'' detector 215 is fed to one input of AND gate 319. The various inputs of 319 also include the "AFT Enable" signal, the "IF Cycle" signal, the signal generated at the Q output of DFF 301, and the "LO Counter Sample" signal.
A signal is also provided. When activated by a high logic level “AFT Enable” signal and a high logic level “IF Cycle” signal, if the main down counter count is greater than or equal to 5 at the end of the LO frequency measurement period, the AND - Gate 319 generates a positive going pulse in response to the positive going "LO Counter Sample" pulse. After the main down counter 201 counts down to 0, it continues counting down from the maximum count value, so the DF
By feeding the Q output signal of F301 to the input of AND gate 319, if the count value is actually 5 or more greater than 0, in response to the "LO Counter Sample" pulse, the AND gate 319 outputs a signal in the positive direction. No pulse is generated, nor is the forward pulse generated in response to a large count being detected at the end of a measurement period due to the count passing through zero.

Also, as mentioned earlier, the "max-4" detector 215 is
After reaching the 0 count value, if the main down counter 201 reaches its maximum count value, it will generate a high logic level "main count value < maximum - 4" output, and the detector 215 will It operates by detecting when the count value of is lower than the maximum count value -4. Detector 21
The output signal of 5 is fed to one input of AND gate 321.

The other inputs of AND gate 321 are also provided with the "AFT ENABLE" signal, the "IF CYCLE signal," the signal generated at the Q output of DFF 301, and the "LO COUNTER SAMPLE" signal. When activated by a high logic level "AFT Activate" signal and a high logic level "IF Cycle" signal, this AND gate 321 indicates that the count value of the main down counter 201 at the end of the LO frequency measurement period is , less than the maximum count value -4, generates a positive going pulse in response to the positive going "LO Counter Sample" pulse.The frequency measurement operation energizes the main down counter 201 to We start by counting down from the number, so DF
By feeding the Q output signal of F301 to the input of AND gate 321, if the count value does not previously cross 0, and therefore is actually no greater than 5 less than O (5 below zero), then " AND gate 321 ensures that no positive going pulses are generated in response to the LO counter sample'' pulse.

The outputs of AND gates 319 and 321 are provided to respective inputs of OR gate 323. and gate 321
and 319 causes a positive going "offset" pulse to occur at the output of OR gate 323.

LO counter “preset” and “activation” shown in Figure 4a
, "sample" pulses is shown in FIG. In particular, the inverter 401 and the AND gate 403 combine the R and 2R timing signals to generate “L”.
Generates “O counter preset” pulse.2048
The R timing signal with a microsecond duration is used as the "LO Counter Enable" signal. Inverter 401
, inverter 405, and AND gate 407 are R
, 2R, and 4R timing signals to generate the "LO Counter Sample" pulse.

IF counter “preset” and “energizing” shown in Figure 5a
, “sample” pulse, and “IF cycle”, “I
The logic circuit configuration for generating the “F cycle” signal is the fifth one.
As shown in the figure. In explaining the following figure 5,
Figure a and Figure 1 are also referred to at the same time.

As previously mentioned, the "vertical pulse" detector 71 in the configuration of FIG. 1 generates a positive going "vertical" pulse (waveform B) after the first vertical sync pulse during the vertical retrace period. A "vertical" pulse is provided to the data (D) input of DFF 501. A 64R timing signal (waveform C) with a period of 32 microseconds is supplied to the clock (C) input of DFF 501. DFF 501 is set in response to the first positive edge of the 64R timing signal that occurs after the occurrence of the "vertical" pulse (waveform B) and its Q output goes to a high logic level.

The Q output of DFF501 is supplied to the D input of DFF503. The 64R timing signal is supplied to the C input of DFF501. DFF 50 in response to the second positive edge of the reference signal that occurs after the occurrence of the "vertical" pulse (waveform B).
3 is set and a low logic level signal is generated on its Q output. The Q output of DFF 501 and the Q output of DFF 503 are coupled to the input of NAND gate 505. Therefore, a negative going pulse D with a width equal to the width of one cycle of the 64R timing signal is applied to the NAND gate after the first positive going edge of the 64R timing signal that occurs after the occurrence of the "vertical" pulse (waveform B). 505 output. The output of NAND gate 505 is provided to inverter 507, which generates a positive-going "IF counter preset" pulse (waveform D) in response to negative-going pulse D.

The "IF Counter Preset" pulse is provided to the set (S) input of DFF 509. An "IF cycle" signal (waveform G) is generated at the Q output of DFF 509, and an "IF cycle" signal is generated at the Q output of DFF 509. D in response to a positive “IF counter preset” pulse.
FF 509 is set so that the "IF Cycle" signal has a high logic level and the "IF Cycle" signal has a low logic level.

Negative direction pulse D is supplied to the clock (C) input of DFF511. A high logic level (“1”) is provided to the D input of DFF 511. The “IF counter activation” signal (waveform E) is generated at the Q output of DFF 511.

DFF 511 is set in response to the positive edge of negative-going pulse D, causing the "IF counter enable" signal generated at the Q output of DFF 511 to be at a high logic level and the signal generated at its Q output to be at a low logic level. .

The period of high logic level of the “IF counter enable” signal, that is, the duration of the IF measurement period is determined by the four-stage binary counter 513.
determined by An "IF counter preset" pulse is applied to the reset (R) input of counter 513 to reset it to a zero counting state prior to the measurement period. The counter 513 then counts the pulses of the 641 (timing signal) supplied to its clock (C) input. When the 64R timing signal has been counted for 8 periods, the 4
A high logic level appears at the stage (Q4) output. counter 5
The Q4 output of No. 13 is supplied to the reset (R) input of DFF511. In response to the high logic level signal generated at the Q4 output of counter 513, DFF 511 is reset to bring the "IF Counter Enable" signal generated at its Q output to a low logic level which terminates the IF measurement period. . 6
Since each period of the 4R timing signal is 32 microseconds long, the IF measurement period is 8x32 or 256 microseconds long. An "IF counter preset" pulse is applied to the reset (R) input of counter 513 to reset this counter 513 to a zero counting state prior to measurement.

“IF counter sample” pulse (waveform F) is DFF
515, AND gate 517, and inverter 51
Generated by 9. Q output signal of DFF511 (E
) is supplied to the clock (C) input of DFF515.

A high logic level (“1”) signal is provided to the data (D) input of DFF 515. The Q output of DFF 515 is provided to one input of AND gate 517. The 64R timing signal is inverted by inverter 519 and the generated signal is provided to the other input of AND gate 517. At the end of the measurement period, in response to a positive edge occurring at the Q output of DFF 511, the Q of DFF 515
A high logic level signal is generated which activates AND gate 517 at the output. The output of the first stage of the counter 513 (Q
The signal generated at 1) is fed to the reset (R) input of DFF 515. Therefore, DFF 515 is reset, thereby terminating the high logic level signal generated at its Q output and disabling AND gate 517 one cycle of the 64R timing signal after the end of the IF measurement period. Thus, after the IF measurement period ends, AND gate 517 is activated to pass one pulse of the 64R timing signal to the output of AND gate 517 as an "IF counter sample" pulse.

“IF counter sample” pulse is inverter 521
supplied to A low logic level (“0”) signal is supplied to the data (D) input of the DFF 509.

Therefore, in response to the negative edge of the IF COUNTER SAMPLE pulse, the DFF 509 is reset, thereby causing the IF CYCLE signal present at the Q output to be at a low logic level, and the IF CYCLE signal present at the Q output to be at a low logic level. “Bring the signal to a high logic level.

A "synthetic enable" signal is provided to the reset (R) inputs of DFFs 501 and 509. A high logic level “Synthesizing Enable” signal prevents the generation of IF counter “Preset,” “energizing,” and “Sample” pulses during the synthetic mode of operation, and the “IF Cycle” signal is high. Make it at a logical level.

The logic circuit of vertical synchronization pulse detector 71 shown as a block in FIGS. 1 and 5 is shown in FIG.

The operation of the logic circuit of FIG. 6 will be explained with reference to the waveforms shown in FIG. 6a.

One configuration of the vertical sync pulse detector shown in FIG. 6 includes two two-stage resettable binary counters 601 and 603. The 256R timing signal, which has a period of 8 microseconds, is used as the clock for counters 601 and 603 (C
) is supplied to the input. A composite sync signal, including horizontal and vertical sync pulses and equalization pulses, is provided to the reset (R) input of counter 601 and to the input of inverter 605. The output of inverter 605 is supplied to the reset (R) input of counter 603.

The period between consecutive relatively narrow positive going pulses of the output signal of inverter 605 corresponds to the duration of the relatively wide positive going vertical sync pulses that occur during the vertical retrace interval. As can be seen from Figure 6a, the duration of one vertical sync pulse corresponds to the duration of three approximately consecutive cycles of the 256R timing signal. Counter 603 is held in a reset state in response to the high logic level of each positive going pulse of the output signal of inverter 605. Therefore, 3
The presence of a vertical sync pulse is indicated when positive clock pulses are counted by counter 603 between successive positive reset pulses. To detect this occurrence, the outputs Q of the first and second stages of counter 603
1 and Q2 are provided to the inputs of AND gate 607. When the signals appearing at the Q1 and Q2 outputs of counter 603 are both at high logic levels, AND gate 60
7 produces a high logic level output at its output. The output of the AND gate 607 is the set of S-RFF 609 (S
) is supplied to the input. A high logic level signal generated at the output of AND gate 607 sets SRFF 609 and its Q output becomes a high logic level. S-RF
The Q output of F' 609 is coupled to one input of AND gate 613. The output of "sync validity" detector 615 is coupled to the other input of AND gate 613. As described below, when S-RFF 609 is set and a high logic level signal is generated at the output of "sync validity" detector 615, "
A “vertical” pulse is generated.

As can be seen from FIG. 6a, the period between successive relatively narrow positive-going post-equalization pulses is similar to the period between successive relatively narrow positive-going pre-equalization pulses.
Approximately corresponds to the duration of three consecutive cycles of the 6R timing signal. Counter 601 and AND gate 611 are similar to counter 603 and AND gate 60.
7 and generates a high logic level signal when three pulses are counted between two successive positive going post-pulses, thereby starting the post-equalizing pulse period. Detect. Output S- of AND gate 611
Reset(R) to reset RFF609
input and thereby S-RFF609
Terminates the high logic level condition that was occurring on the Q output of .

Some RF television signal sources, such as video games, do not generate pre- and post-equalization pulses. However, the circuit configuration shown in FIG.
It can operate in substantially the same way except that S-RFF 609 is reset when three clock pulses are counted by 01.

Sync validity detector 615 generates a high logic level output signal that energizes AND gate 613 in response to the composite sync signal when the composite sync signal is correct and relatively free of noise; 613 generates a "vertical" pulse. Therefore, the synchronization validity detector 615 can be configured by a simple average detector. Other suitable types of synchronization validity detectors 615 that examine the frequency and period of the composite synchronization signal to determine its validity include:
U.S. Patent Application No. 261,449, filed in the United States on May 8, 1981, and assigned to the applicant and GRA Corporation.
No. 042, corresponding to Japanese Patent Application Laid-Open No. 57194683). In a relatively noise-free environment,
Detector 615 and AND gate 613 can be omitted. In this case, the “vertical” pulse is directly connected to the S-RFF
609's Q output.

Next, referring to FIG. 8, the binary rate multiplier (BRM
) 57, low-pass filter 59 and up-down filter
An example of a configuration including the counter 55 will be described.

The number of stages of the BRM 57 is selected such that the number of tuning voltage stages does not create LO frequency stages that cause visible interference in the reproduced video.

As an example, 14 stages have been found to be suitable for this purpose. The frequency of the clock signal for BRM57 is AFT
During the operating mode, the selection is made to allow sufficient time for the BRM 57 to complete its operating cycle and for the tuning voltage to change between the error pulses that occur for each field during the AFT operating mode. As shown by way of example in FIG. 1, 4 MHz has been found to be suitable for this purpose. As shown above, the composite operating mode is divided into a coarse tuning period, an intermediate tuning period, and a fine tuning period, and the number of states of the BRM that can change in each of them is 4 MHz clock signal, tuning voltage error, It is limited to allow enough time to change between pulses. Furthermore, by selecting a 4 MHz clock for the BRM 57, practical values can be used for the resistors and capacitors constituting the low pass filter (LPF) 59, as shown in FIG. This also means that the worst-case ribble of the tuning voltage can cause perturbations (e.g. 50
This is consistent with the fact that the LO frequency oscillation is much smaller than the LO frequency oscillation (KH oscillation).

BRM57 is a CD40 manufactured by RCIA Corporation located in Somerville, USA.
It is constructed in a similar manner to the 89 bond collection circuit binary rate multiplier.

Reference is made to the embodiment of the low pass filter shown in FIG. B
The output signal of RM57 is connected to AND gates 801 and 80.
3 is fed to the first input. The “composite activation” control signal is provided to the second input of AND gate 801, and the “AF
The "T Enable" signal is provided to the second input of AND gate 803. During the composite mode of operation, the "Synthesis Enable" signal is at a high logic level, thereby causing AND gate 80 to
1 is energized and transfers the output signal of the DRM 57 to the resistor 805.
and a capacitor 807. During the AFT mode of operation, the “AFT Enable” signal goes to a high logic level, energizing AND gate 803 to route the output signal of BRM 57 to low pass filter 59 consisting of resistor 809 and capacitor 807. A second low-pass filter section is supplied. Resistors 805, 809 and capacitor 807
is fed to the input of an amplifier 61 which amplifies the DC voltage produced by the low-pass filter 59, as described with respect to FIG.

Because the low-pass filter 59 is a relatively simple structure consisting of just two resistors and a capacitor, it eliminates the cost of more complex active low-pass filter systems commonly used in phase-locked loop tuning control systems. Sufficient cost savings are achieved to offset the

The embodiment of the up/down counter 55 shown in FIG. 8 has a 14-stage counter configuration, and has two stages of up/down counters.
Counter 55a, 4-stage up/down counter 55b
, a four-stage up/down counter 55C, and a four-stage up/down counter 55d are connected in cascade.

And up/down counters 55a, 55b, 5
Each carry-out (CO) output of 5c goes up/down through OR gates 811a, 811b, and 811c, respectively.
Down counters 55b, 55c, . 55d's carry-in (CI) input. counter 55a
55d to 55d are CD4516 integrated circuit binary up/down circuits sold by RCA Corporation.
It is configured in a similar form to a counter.

The "low count value" or "high count value" error pulse from frequency sampler 30 is fed directly to the clock (C) input of up/down counter 55d via NOR gate 813, and also to the clock (C) input of up/down counter 55d. - selectively fed to clock inputs of up/down counters 55c, 55b, 55a via gates 815c, 815b and 815a; "Coarse tuning", "intermediate tuning" and "fine tuning" control signals are provided by inverters 817c and 817b.
and 817a, and the signals generated by the inversion are inverted by AND gates 815c and 815b, respectively.
, 815a. Therefore, the AND gates 815c, 815b, 815a are connected to the tuning control unit 4.
In response to high logic level "Coarse Tune", "Medium Tune", and "Full Tune" control signals generated by the Flock 5, the error pulses are selectively inhibited from being applied to each Flock input.

When the “Coarse Tuning” control signal is at a high logic level, the AND
Gates 815c, 815b, 815a are deactivated and the error pulse is provided only to the clock input of counter 55d. When the "Intermediate Tuning" control signal is at a high logic level, AND gates 815b and 815a are disabled and error pulses are provided only to the clock inputs of counters 55d and 55c. When the "fine tune" control pulse is at a high logic level, AND gate 815a is disabled and the error pulse is provided only to the clock inputs of counters 55d, 55c, and 55b. When none of the "coarse tuning", "intermediate tuning", and "fine tuning" control signals are at a high logic level, the error pulse is applied to all counters 55d, 55c, 55b,
55a's clock input. The “coarse tune”, “medium tune”, and “fine tune” control signals are also provided by the OR gate 81.
1c, 811b, and 811a, and when at a high logic level, provides a high logic level carry-in signal to the respective carry-in inputs of counters 55d, 55c, and 55b. As shown in more detail with respect to the configuration of FIG. 9, the configuration of the tuning control unit 43 is "coarse tuning".
, "medium tune" and "fine tune" control signals have a high logic level during successive periods as shown in FIG. 9a. During the AFT mode of operation, all control signals are forced to have a low logic level so that the full 14 bits of resolution of counter 55 are available.

A “high count value” error pulse is supplied to the set (S) input of S-RFF819, a “low count value” error pulse is supplied to its reset (R) input, and its Q output is supplied to the counter 5.
5a through 55d are coupled to one "up/down" control input. When a “high count value” error pulse is generated,
S-RFF 819 is set and its Q output goes to a high logic level. When a “low count value” error pulse is generated,
S-RFF 819 is reset and its Q output goes to a low logic level.

When a high logic level appears at the Q output of S-RFF 819, counters 55a-55d are incremented in response to the error pulse. When a low logic level appears at the Q output of S-RFF 819, counters 55a-55d are decremented in response to the error pulse.

Tuning control logic unit 45 shown in block form in FIG.
An example of the logical configuration of is shown in FIG.

The operation of the logic configuration shown in FIG. 9 will be explained with reference to the waveforms shown in FIG. 9a.

In the configuration of FIG. 9, AND gate 901, DFF
The logic configuration consisting of 903 and 905 selects one of the "LO Counter Preset" pulses and generates a "Start" pulse after a high logic level "New Channel" signal is generated when a new channel is selected. .AND gate 901 connects the Q output of DFF 903 and DF
In response to a signal developed at the Q output of F905, the output is applied for a sufficient period of time so that exactly one "preset" pulse is applied from its input to its output as a "start" pulse as shown in Figure 9a. Forced.

The “start” pulse is one set of S-RFF907 (S
) input, and the S-RFF 907 receives its “start” input.
It generates a high logic level "synthesis enable" signal at its Q output in response to a pulse. The “start” pulse is also S-RFF
Also fed to each set (S) input of 909 and 911, these S-RFFs cooperate with AND gate 913 to spread across one "LO Counter Sample" pulse as shown in Figure 9a. Generates a positive “reset” pulse.

The purpose of this is discussed below.

S-RFF 915, DFF 917, and DFF 919 cooperate with NOR gate 921, exclusive-OR gate 923, and NOR gate 925 to provide "coarse tuning,""intermediatetuning," and Generates a “fine tuning” control signal. In particular, the "coarse tune" control signal is made to have a high logic level in response to the "new channel" signal, and thereafter the "intermediate tune" control signal is made to have a high logic level in response to the "new channel" signal, and then in response to each change in the shape of the frequency error detected by the LO frequency sampler 31. ” and “fine tuning” control signals are made to have a high logic level once in the operating sequence. The frequency error mentioned above is now represented by the corresponding alternating occurrence of "low count" and "high count" pulses.

Next, reference will be made to the configuration shown in FIG. Frequency sampler 30
The "high count" and "low count" error pulses generated by are fed to the set (S) and reset (R) inputs of S-RFF 915, respectively. S-RFF91
The Q and Q outputs of DFFs 917 and 919 are supplied to the clock (C) inputs of DFFs 917 and 919, respectively. The Q outputs and D inputs of DFFs 917 and 919 are coupled, and the D
FFs 917 and 919 are arranged as a toggle flip-flop. “Reset” pulse is DFF91
7 and 919 reset inputs. S-RF
The “AFT activation” signal generated at the Q output of F907 is DF
Supplied to set inputs of F917 and 919. DF
The output signal A produced at the Q output of F917 is fed to the first input of NOR gate 921 and the first input of exclusive OR (XOH) gate 923, and the signal A produced at the Q output of DFF 917 is fed to the first input of NOR gate 921 and the first input of exclusive OR (XOH) gate 923. A first input of gate 925 is provided. The signal B generated at the Q output of DFF 919 is provided to the second input of NOR gate 921 and the second input of exclusive OR gate 923, and is also applied to the Q output of DFF 919.
The signal B generated at the output is provided to the second input of exclusive-OR gate 925. The “AFT Enable” signal is provided to the third input of NOR gate 925.

During the AFT operating mode, when the "AFT Enable" signal is at a high logic level, the NOR gate 925 responds to the high logic level "AFT Enable" signal so that its output is always at a low logic level. , A and B signals. During synthesis mode operation, when the “AFT Enable” signal is at a low logic level, the NOR gate 925
becomes responsive to the levels of the A and B signals. A "coarse tune" signal is generated at the output of NOR gate 921. “
A "medium tune" signal is generated at the output of exclusive OR gate 923. A "fine tune" signal is generated at the output of NOR gate 925.

A positive going "reset" pulse generated in response to a high logic level "new channel" signal resets both DFFs 917 and 919. As a result, signals A and B are both at a low logic level in response to the positive going "reset" pulse, resulting in a high logic level of the "coarse tune" signal produced at the output of NOR gate 921. At the same time, the "medium tune" signal produced at the output of exclusive OR gate 923 goes to a low logic level, and the "fine tune" signal produced at the output of OR gate 925 goes to a low logic level.

During coarse tuning, the frequency of the local oscillator signal is either higher or lower than it should be, and either a "low count" or a "high count" error pulse is generated continuously. As an example, after a new channel is selected, assuming the LO frequency is lower than its original frequency, a "low count" error pulse is generated as shown in Figure 9a. LO frequency sample 31 then operates in conjunction with up/down counter 55, DRM 57, LPF 59 and amplifier 61 to determine the tuning voltage and thus L
Increase O frequency. If the frequency of the LO signal overshoots its final or correct value, a “low count value”
An error pulse with a "higher count value" than the error pulse is generated. This resets S-RFF 915, thereby generating a positive going pulse on its Q output. This is DFF
917 so that signal A has a high logic level and signal A has a low logic level. At this point, B is still at a low logic level and B is at a high logic level. As a result, the "coarse tune" signal has a low logic level, the "medium tune" signal has a high logic level, and the "fine tune" signal has a low logic level.

In response to a "high count" error pulse, the LO frequency is decreased. When the frequency of the LO signal again overshoots its final value, a "low count" error pulse is again generated instead of a "high count" error pulse. This again sets S-RFF 915 and DFF 919, causing signals A and B to both go to a high logic level and signals A and D to both to a low logic level. As a result, “coarse tuning”
and the "medium tune" signal goes to a low logic level, and the "fine tune" signal goes to a high logic level.

As previously mentioned, the logic circuit including logic components 901-913 ensures that the "reset" pulse straddles the first "sample" pulse, so that the first "high count value"
A "low count" error pulse is generated after the occurrence of a high logic level new channel signal. As a result, under normal operating conditions, the states of FFs 917 and 919 do not change until the direction of frequency correction changes.

If the "reset" pulse does not extend across the first error pulse, the change from one type of error pulse to the other will occur immediately upon selection of a new channel due to the initial uncertain operating conditions. This is S-RFF9
15 and the state of one of DFFs 917 and 919, thereby disrupting the proper generation order of the "coarse tune,""mediumtune," and "fine tune" control signals.

The output of NOR gate 925 is provided to the set input of S-RFF 927. The Q output of S-RFF 927 is provided to one input of AND gate 925.

The output of NOR gate 925 is also coupled to the input of inverter 931, and the output of inverter 931 is
Coupled to a second input of gate 929.

The output of AND gate 929 is coupled to the reset input of S-RFF 907. As mentioned earlier, the “synthetic activation” signal is generated at the Q output of the S-RFF907 and is
The "T energize" signal is generated at the Q output of S-RFF 907.

S-RFF9 in response to a high logic level “hui tune” signal.
27 is set and its Q output goes to a high logic level;
This energizes AND gate 929. When the "fine tune" signal is caused to have a low logic level, a corresponding high logic level signal is generated by inverter 931 which is connected to the activated AND gate 92.
9 and is supplied to the reset input of S-RFF907. Resetting S-RFF 907 causes the "AFT Enable" signal generated at its Q output to go to a high logic level. A "start" pulse is provided to the reset input of S-RFF 927 and resets S-RFF 927. This disables AND gate 929 and the occurrence of a low logic level at the output of NOR gate 925 resets S-RFF 907 during the composite mode of operation until after a high logic level "fine tuning" signal is generated. to prevent it from happening.

The high logic level "AFT Enable" signal maintains DFFs 917 and 919 set during the AFT mode of operation. Therefore, during the AFT operation mode, the signal A
, B at a high logic level and signals A, B at a low logic level. As mentioned earlier, high logic level “AFT energization”
The signal also prevents NOR gate 925 from responding to signals A and B, causing its output to be a low logic level. As a result, during the AFT operating mode, "coarse tuning"
"Intermediate tuning" and "fine tuning" all go to low logic levels.

The "offset" signal is provided to the second set (S) input of S-RFF 907. S-RFF907 is forward direction
Offset" pulse, which causes the "Synthetic Enable" signal to have a high logic level and the "AFT Enable" signal to have a low logic level. This causes the AFT mode of operation to be terminated. , resumes the synthesis mode of operation. In response to the low logic level "AFT Activate" signal, NOR gate 925 is activated so that signals A and B (high logic level) is in this state in response to a signal).

As a result, the "fine tuning" control signal is forced to a high logic level. Then, when the LO frequency overshoots its final value, one of DFFs 917 and 919 is reset. This causes the "fine tuning" signal to go to a low logic level. As a result, the high logic level "fine tuning" signal is terminated, the S-RFF 907 is reset, and the "AF
The "T energize" signal will be at a high logic level and the "composite energize" signal will be at a low logic level.

Although the invention has been described with respect to a frequency-locked loop tuning system, it is described, for example, in the document ``Dual Mode Frequency Synthesizer for Television Tuning Systems (-Dua
l Mode Frequency Synthese
zer for a, Television Tuni
It may also be applied to phase-locked loop tuning devices of the type shown in U.S. Pat. Furthermore, although in the particular embodiment described above, the frequency of the IF video is measured during the vertical retrace synchronization period, the frequency measurement could also be performed during the horizontal retrace synchronization period. Although the particular embodiment described above uses a single common split time multiplexed counter arrangement for local oscillator and IF frequency measurements, it is possible to use separate counters for each of these functions. You can also use It goes without saying that other modifications including these modifications are also included within the scope of the claims of the present application.

[Brief explanation of the drawing]

FIG. 1 schematically shows, in block diagram form, a tuning device in which the invention is implemented. FIGS. 2, 3, 4, 5 and 6 are schematic diagrams illustrating portions of a preferred embodiment of the invention in the form of logic circuits. Figures 4a, 5a, and 6a are similar to Figures 2, 3, and 4.
FIG. 6 is a diagram showing various signal waveforms useful for understanding the operation of the configuration shown in FIGS. 7a and 7b are diagrams illustrating a particular example of a portion of the structure of FIG. 2, shown in block form and in logic circuit form. 8 and 9 are diagrams showing each part of the structure of FIG. 1 shown in block form in the form of logic circuits. FIG. 9a is a diagram showing signal waveforms useful for understanding the operation of the configuration shown in FIG. 3...RF amplifier, 5...mixer, 7...local oscillator, {13
...Video detector 15...Video processing unit 23...Video tube}Video processing means 30...Frequency sampler (fine tuning control means), {55...Up/down counter 57...Binary rate multiplier 59...Low pass filter} Tuning control signal generating means, 61
... Amplifier {17 ... Tuning separator 25 ... Deflection circuit 27 ... Deflection coil 29 ... Blanking unit} Tuning processing means, 71 ... Vertical pulse detector (fine tuning energizing means). ? 3 Figure 74 Figure 48 Days Procedure Sleeve J1: Written (Spontaneous) October 24, 1981 1, Indication of the Case Ii, Application 1 Li-458161183 No. 2, Name of the Invention Television Tuning f! i! IM device 3, person making amendment Relation to the case Patent applicant address 30 New York Rockefeller Plaza, New York, United States of America 10020 Name (757) R Ciney Corporation 4, "Scope of Patent Requested" in the attorney's specification, " Total invention 1#1
6 packs with 1 explanation. 6. Contents of the amendment: Separate the scope of claims by <It: h” Corrected 1
vinegar. (2) On page 21, lines 16 to 20 of the coffin between Showa 1 [
By the group 1 control unit 45...the 11 units of the I stage are sequentially 1\" eJt "The up/down counter 55 is generated by the synchronized control 1i11 unit 45",
In response to each system f′lI of “outgoing tone”, “intermediate tone”, and “fine tone”, “high side number” and “low count l”! Correct this to "energize the lower stage groups sequentially in response to the J1 difference pulse". - Error pulse or "[Logic in Figure 3 above, 1 dilute acid generates an appropriate 1 μ! difference pulse,
Or,” 14” corrects. (-I) In the same page δ47, line 11 to line m12, "may or may not occur." is corrected to "may or may not occur." (5) Ibid., p. 79, lines 19 to 20 of the same book, "in response to a positive "reset"pulse" has been deleted;
. (6) Correct the clear rqn mark to the following regular table. Errata Who did what harm? Patent 5) °j Claims: (1) Television tuning control 1 having an input to which an RF television signal corresponding to each channel is supplied 1, wherein each HJ="signal has a video carrier modulated by video information containing video information during a video period occurring between vertical blanking periods and between vertical blanking periods,
an RF" stage for processing the I signal, and a local deoscillation a for producing a local oscillator signal having a frequency associated with the selected channel in response to the tuning control signal;
); a mixer for generating a LL+' signal having a video carrier modulated in the same manner as the video carrier; a video processing means for generating a signal; a synchronization processing means for generating a synchronization signal; is fired/1
゜means, and coupled to the tuning control signal generating means.''
1" fine tuning control means for controlling the tuning control signal described in 1U so that, when energized, the video carrier wave has its nominal frequency; and the fine tuning control means; selectively energizes said fine tuning control means to selectively energize said fine tuning control means during respective predetermined portions of said retrace interval in response to a coupled signal! kiiE'(
1. A tuning control device for a television, comprising: a fine tuning/energizing means responsive to 1, υ;

Claims (1)

[Claims] (1) A television tuning control device having an input to which an RF television signal corresponding to each channel is supplied, which includes video information during a video period occurring between the horizontal retrace periods of each RF signal. a video carrier modulated by video information, the horizontal retrace period itself occurring between multiple straight retrace periods, and one of the RF signals corresponding to a selected channel in response to a tuning control signal. a local oscillator for generating a local oscillator signal having a frequency associated with the selected channel in response to the tuning control signal; the local oscillator signal and the selected RF signal; a mixer for generating an IF signal having a video carrier modulated in the same manner as the video carrier of the selected RF signal, and the video included in the video period in response to the IF signal; video processing means for generating a video signal representing information; synchronization processing means for generating horizontal and vertical synchronization signals representing the occurrence of the horizontal and vertical retrace periods in response to the IF signal; and generating the tuning control signal. a tuning control signal generating means coupled to said tuning control signal generating means and responsive to said IF signal and, when energized, controlling said tuning control signal such that said IF video carrier has its nominal frequency; fine tuning control means coupled to said fine tuning control means and responsive to a synchronization signal to selectively energize said fine tuning control means during respective predetermined portions of said retrace period; and fine tuning energizing means for making the fine tuning energizing means respond to the IF signal.