NZ193794A

NZ193794A - Channel identification in multiband sweep tuning system

Info

Publication number: NZ193794A
Application number: NZ193794A
Authority: NZ
Inventors: J G N Henderson; C M Wine; R J Maturo
Original assignee: Rca Corp
Priority date: 1979-05-30
Filing date: 1980-05-21
Publication date: 1984-03-30
Also published as: KR830003982A; FR2458189A1; FI801674A; AU532355B2; AU5872180A; DE3020663A1; PL224632A1; KR830002299B1; SE8003855L; GB2052903A; ES491963A0; IT1131190B; ES8103524A1; PL130381B1; GB2052903B; IT8022326A0

Description

<div class="application article clearfix" id="description"> • 1 937 Patents Form No. 5 NEW ZEALAND PATENTS ACT 195 3 COMPLETE SPECIFICATION CHANNEL IDENTIFICATION APPARATUS USEFUL IN A SWEEP TYPE TUNING SYSTEM 2/WE RCA CORPORATION, A corporation organized under the laws of the State of Delaware, United States of AmericA, of 30 Rockefeller Plaza, New York City, New York 10020, United States of America, hereby declare the invention, for which J/we pray that a patent may be granted to M8/us, and the method by which it is to be performed, to be particularly described in and by the following statement (felJowed fey pag« I A - 1 - %a9 4 -lft— ItCA 731 CHANNEL IDENTIFICATION APPARATUS USEFUL IN A SWEEP TYPE TUNING SYSTEM The present invention relates to the field of digital tuning systems. A number of digital tuning systems for controlling voltage controlled oscillator to generate a local oscillator signal for tuning a radio or television receiver are known. These digital tuning systems may be generally categorized as being either of the frequency synthesizer, voltage synthesizer or voltage sweep type. 15 Frequency synthesizers are typically closed loop. One type of frequency synthesizer includes a phase or frequency comparator for generating the control voltage for a local oscillator signal by comparing the phase and/or frequency of a variable frequency signal derived by the 2qfrequency division of the local oscillator signal and a relatively stable reference frequency signal. The frequency of the loop and thereby the frequency of the local oscillator signal is determined by division factors of fixed and programmable frequency dividers in the loop. The programmable 25 divider is controlled in response to binary signals representing the number of a selected channel to determine the particular local oscillator frequency. Another type of frequency synthesizer includes a counter for counting in cycles of a voltage controlled local oscillator signal and 2Qa count comparator for comparing the number accumulated by the counter with a number derived from binary signals representing the channel number of a selected channel to develop a local oscillator control voltage. In either system channel numbers of selected channels can be readily displayed 35 in response to the binary signals representing the number of the selected channels. Although such frequency synthesizers are advantageous in that the frequencies of the local oscillator signal are relatively accurate because of the closed loop nature of the systems, such systems are relatively 4Qexpensive due to the cost of the high speed dividers and 1937 9 4 1 -2- RCA 73145/73145A counters they necessarily employ. Voltage synthesizers are typically open loop 5systems.and generally include a memory having a plurality of tuning voltage memory locations for storing binary signals representing the tuning voltages for each of the channels that a user may select. The channel numbers of selected channels can be readily displayed, for example, in response 10to binary signals representing the channel numbers and utilized to address corresponding tuning voltage memory locations. Although such voltage synthesizers are advantageous in that they are relatively inexpensive compared with frequency synthesizers because they do not require high 15speed frequency dividers and counters, they tend to be less accurate because the required precision and resolution in converting the binary signals stored in the tuning voltage memory locations to the corresponding tuning voltages is not readily attainable in open loop systems. 20 Many tuning systems of the voltage sweep type are known. Basically, they all generate a. ramp-like tuning voltage which is utilized to sweep the frequency of the local oscillator signal. In its simplest form, the magnitude of the tuning voltage is increased or decreased under user 25control by means of a potentiometer or the like until the user determines that an acceptable station has been reached. Signal sweeping systems are also known in which the magnitude of a tuning voltage is changed until a carrier is automatically detected. Such sweep systems are advantageous in 30that they are relatively accurate compared to voltage synthesizers since the tuning voltage is continuously adjusted until an acceptable channel is located and are relatively inexpensive compared to frequency synthesizers since they do not require high speed frequency dividers and 35counters. However, since the tuning voltage is not derived as part of an operation involving the use of binary signals representing the number of a selected channel, additional apparatus must be provided for channel identification. While it is possible to employ high speed counters 40 to determine the frequency of the local oscillator signal and 1 -3- 1937 9 4 RCA 73145/73145A from the frequency derive the number of the selected channel, the use of high speed counters is to be avoided to maintain 5 the cost effectiveness of sweep type systems. Apparatus are also known for monitoring the channel to which a receiver is tuned by examining the tuning voltage. In these systems the tuning voltage for a selected channel to which the receiver is already tuned is compared with voltages 10 having magnitudes corresponding to the magnitudes of the tuning voltage to tune respective channels stored in memory locations of a memory. The memory locations are successively addressed until there is at least an approximate equality between the tuning voltage and one of the stored voltages. 15 The number of the selected channel is derived from the address of the memory location at which the approximate equality existed. Such systems may be used by television rating services to identify a limited number of channels in a particular viewing area. However, they are not particularly well 20 suited for television receivers to identify all of the channels in the television tuning range because of the need for greater resolution* in accurately distinguishing between closely spaced channels in the latter application. Moreover, such monitoring systems are not particularly well suited for 25 sweep type systems to display the channel numbers of channels passed before an acceptable channel is located since the tuning voltage changes until an acceptable channel is located. In sweep systems, it may be desirable to display the channel number of channels passed to reach the acceptable channel so 30 that users have a visible indication that the system is operating and are therefore not annoyed by apparent lack of operation as an acceptable channel is sought. A system for tuning a receiver to various channels 35 includes a local oscillator means for generating a local oscillator signal appropriate for tuning the receiver to various channels in response to the magnitudes of a tuning voltage. The tuning voltage may be generated by apparatus including signal seeking means for changing the magnitude of 40 the tuning voltage to automatically locate an acceptable 1 9379 1 -4- RCA 7 3145/73145A ' channel or manual means for changing the magnitude of the tuning voltage until an acceptable channel is located by a 5user. To display the channel numbers, the tuning system includes memory means, e.g., a PROM (Programmable Read Only Memory), including a plurality of memory locations each for storing binary signals representing a respective boundary voltage substantially equal to the tuning voltage at a fre-lOquency between the tuning voltage ranges of adjacent channels. Address means is provided for addressing the memory locations. As the memory locations are addressed, comparison means compares the tuning voltage to the boundary voltages. Control means causes the address means to address the memory location 15 corresponding to the boundary voltage for the next channel until the magnitude of a predetermined one of the tuning voltage and the boundary voltage associated with an addressed memory exceeds the magnitude of the other one. Channel number display means displays the channel number of the 20channel associated with a presently addressed memory location. By additional means, where it is desired to display channel numbers as the magnitude of the tuning voltage is being changed, the addressing of memory locations in sequence may occur during the interval in which the magnitude of the 25 tuning voltage is being changed. IN THE DRAWINGS: FIGURES 1, la, lb and lc, which should be referred to concurrently, show partially in block diagram form and partially in schematic diagram form an embodiment of the 30 present tuning system as it is employed in a television receiver. FIGURE 2 shows tuning voltage characteristics of a voltage controlled tuner that may be employed in the present tuning system useful in facilitating an under-35 standing of the present tuning system. FIGURE 3 shows the allocation of memory locations 1937^ 1 -5- -RCA 73145/73] 45A of a boundary voltage memory employed in the present tuning system. 5 FIGURES 4a, 4b and 4c show a flow chart indicating the operation of the arrangement shown in FIGURES 1, la, lb and lc. FIGURES 5 and 6 show in block diagram form apparatus for programming of a boundary voltage memory employed in 10 the present invention. FIGURES 7 and 8 show in logic diagram form .implementations of portions of the present tuning system. The color television receiver shown in FIGURE 1 15 includes an antenna 1, an RF processing unit 3, a mixer 5 and a voltage controlled local oscillator 7 arranged to generate an IF signal. The IF signal is processed by an IF processing unit 9 and coupled to a sound processing unit 11, a picture processing unit 13 and a synchronization unit 20 15. An audio response is generated by a speaker 17 in response to audio signals derived from the IF signal by sound processing unit 11. Electron beams representing red, green and blue information are generated by a picture tube 19 in response to picture signals derived from the IF signal 25 by picture processing unit 13. The electron beams are deflected in a raster portion to form an image in response to horizontal and vertical sycnhronization signals generated by a deflection unit 21 in response to horizontal and vertical synchronization pulses derived from the IF signal 30 by synchronization unit 15. Local oscillator 7 includes tuned circuit configurations (not shown) for each of a low VHF band covering channels 2 through 6, a high VHF band covering channels 7 through 13 and a UHF band covering channels 14 through 83. 35 The tuned circuits are selectively activated in response to VL (VHF Low), VH (VHF High) and U (UHF) band selection signals generated by a tuning system 23 which is constructed in accordance with the present invention. Each of the tuned circuit configurations includes an inductor and varactor 40 diode (not shown). The varactor diode is reverse biased by 1C3794 - 6 - RCA 73145/73145A a tuning voltage generated by tuning system 2 3 to exhibit a capacitance. The magnitude of the tuning voltage determines the capacitance of the tuned circuit and thereby the frequency of local oscillator 23. The band selection signals and the tuning voltage are also coupled to RF unit 3 to control selectively enabled tuned circuit configurations similar to the ones in local oscillator 7 so as to track the tuning of local oscillator 7. A portion of the IF signal is coupled to an automatic fine tuning (AFT) discriminator 25 which generates an AFT signal having a magnitude representing the magnitude of the deviation of the frequency of a picture carrier component of the IF signal from its nominal value,such as 45.75 MHz in the United States of America. The AFT signal is utilized by tuning system 23 as will be described below to develop the tuning voltage. The IF signal is also coupled to an automatic gain control (AGC) unit 27 which generates RF and IF AGC signals for controlling the gains of the RF and IF stages, respectively, in accordance with the RF signal strength as manifested by the amplitude of the IF signal. The portions of the receiver shown in FIGURE 1, with the exception of tuning system 23, are conventional and may therefore comprise corresponding portions of a CTC-93 television chassis manufactured by RCA Corporation and described in detail in "RCA" Service Data, File 197 8 C-7"^ « Tuning system 23 is of the sweep/signal seeking type described above and includes a ramp voltage generator 29 and automatic channel detection circuits 31. When a user depresses either an up push button (UPPB) 33 or a down push button (DNPB) 35, ramp voltage generator 29 generates a ramp voltage which increases or decreases, respectively, as a function of time until automatic channel detection circuits 31 detect the presence of a channel acceptable for viewing. A channel identification arrangement 36 displays the channel number of the first acceptable channel to which tuning system 23 tunes the receiver after one of UPPB 33 or DNPB 35 are depressed and also the channel numbers of the channels passed to reach the first acceptable channel. In the latter manner, the user is made aware, during periods 5 in which an acceptable channel is sought, that tuning system 23 is operating. This is a desirable feature since acceptable channels, especially in the UHF band, may be considerably separated. Channel identification arrangement 36 includes a 10 tuning voltage boundary memory 37 having memory locations for storing binary signals representing boundary voltages having magnitudes corresponding to the lowest and highest magnitude of a tuning voltage range corresponding to each of channels 2 through 83 to which tuning system 23 may tune 15 the receiver. Tuning voltage boundary memory 37 comprises a PROM (Programmable Read Only Memory) for reasons which will be explained below. A tuning voltage boundary memory address register 39 addresses memory locations of tuning voltage boundary PROM 37 under the control of a microprocessor 20 41. Channel identification arrangement 36 also includes a channel number memory 43, comprising a ROM (Read Only Memory), having memory locations for storing binary signals representing channel numbers 02 through 83 and a channel number address register 45 for addressing the memory locations of memory 43 25 under the control of microprocessor 41. As memory locations of memory 37 are addressed, a digital-to-analog converter 47 generates the boundary voltages in response to the stored binary signals. When the tuning voltage is swept in the direction of increasing 30 magnitudes, the upper boundary voltages are compared to the tuning voltage by an UP voltage comparator 49. As long as an acceptable channel is not detected, whenever the magnitude of the tuning voltage exceeds the magnitude of an upper boundary voltage, an ADD (ADDress) CHANGE signal is generated 35 by UP comparator 49 and coupled through an AND gate 51, enabled by an UP RAMP signal, and an OR gate 5 3 to microprocessor 41. In response, microprocessor 41 causes tuning voltage address register 39 to address the memory location of tuning voltage boundary memory 37 corresponding to the 40 upper boundary voltage for the next higher channel and 1 937Q :A 73^4y7'314!jA 1 -8- RCA 73rL4^y7'3145A causes channel number address register 45 to address the memory location of channel number memory 43 corresponding 5 to the next higher channel. When the tuning voltage is swept in the direction of decreasing magnitudes, the lower boundary voltages are compared to the tuning voltage by a DN voltage comparator 55. As long as an acceptable channel is not detected, whenever the magnitude of the tuning 10 voltage falls below the magnitude of a lower boundary voltage, an ADD CHANGE signal is generated by DN comparator 55 and coupled through an AND gate 57, enabled by a DN RAMP signal, and OR gate 53 to microprocessor 41. In response to the ADD CHANGE signal, microprocessor 41 causes tuning voltage 15 boundary address register 39 to address the memory location of tuning voltage boundary memory 37 corresponding to the lower boundary voltage for the next lower channel and causes channel number address register 4 5 to address the memory location of channel number memory 4 3 corresponding to the 20 channel number for the same next lower channel. As the memory locations of channel number memory 43 are addressed, a two-digit channel number display unit 59, which may include two arrays of seven-segment light-emitting diodes each arranged in a conventional manner to display 25 numbers, displays the corresponding channel number. In addition, a band decoder 61 examines the channel number to determine which of the low VHF, high VHF or UHF bands it is in to generate the VL, VH and U band selection signals. An acceptable channel is detected by examining the 30 magnitude of the AFT signal, the average value of the horizontal synchronization pulses, and the magnitude of the AGC signal coupled to the IF. For this purpose, automatic channel detection circuits 31 (see FIGURE la) includes: an AFT voltage comparator 6 3 for generating an AFT VALID 35 signal when the magnitude of the AFT signal is between predetermined threshold values defining its control range; an average detector 6 5 and average synchronization voltage comparator 67 for generating a SYNC VALID signal when the average voltage of the horizontal synchronization pulses is 40 within a predetermined range of values; and an AGC voltage 19379 4 1 • -9- RCA 73145/73145A comparator 69 for generating an AGC VALID signal when the iF AGC is below a predetermined threshold. 5 The AFT signal is examined to determine the presence of an IF carrier. The carrier detected may be that of the sound component of the IF signal rather than that of the picture carrier. Under these conditions, the average voltage of the synchronization pulses will not be within the pre-10 determined range established by average synchronization voltage comparator 67. Thus, the synchronization pulses are examined to prevent tuning system 2 3 from tuning the receiver to a sound carrier rather than a picture carrier. The IF AGC signal is examined so that the receiver will not 15 be tuned to carriers having insufficient signal strength to produce a picture without an undue amount of interference or "snow" as it is sometimes called in the picture. Since the amount of interference which is tolerable is dependent on the particular user's preferences, AGC comparator 6 9 may 20 include a potentiometer or the like for adjusting the predetermined threshold voltage to which the IF AGC signal is compared. The IF AGC signal rather than the RF AGC signal is utilized since the RF AGC in conventional color television receivers remains substantially constant until the signal 25 strength is appreciable. The AFT VALID signal is coupled to ramp voltage generator 29. The SYNC VALID and AGC VALID signals are combined by an AND gate 71 and coupled to microprocessor 41 but only after a predetermined time delay, determined by 30a delay unit 73, after the generation of the AFT VALID signal. The predetermined time delay is selected to allow synchronization unit 15 and AGC unit 2 7 to have time to settle after a carrier is detected. Ramp voltage generator 29 (see FIGURE lb) includes 35a differential amplifier 75 and a capacitor 77 configured as a voltage integrator. A number of transmission gates have their conduction controlled in response to control signals generated by automatic channel detection circuits 31 and microprocessor 41 to start and stop the generation of the 40 ramp tuning voltage and control the direction in which its magnitude is changed. An UP pulse is generated by microprocessor 41 when: 5 (1) a power up detector 76 detects that the receiver has been turned on by sensing the level of one of the receiver's power supply voltages; (2) UPPB 33 is depressed; (3) an AFT VALID signal has not been generated 10 during an upward search; and (4) an AFT VALID signal has been generated but SYNC VALID and AGC VALID signals have not been generated during an upward search. A DN pulse is generated when: 15 (1) DNPB 35 is depressed; (2) an AFT VALID signal has not been generated during a downward search; and (3) an AFT VALID signal has been generated but SYNC VALID and AGC VALID signals have not been generated 20during a downward search. When either an UP pulse or a DN pulse is generated, a START RAMP pulse is also generated by microprocessor 41. The START RAMP pulse sets a set-reset flip-flop (S-R FF) 78 thereby causing the conduction of a transmission 25gate 79. The UP pulse is coupled through an AND gate 81, enabled by the simultaneous presence of the START RAMP pulse, to the S input of a S-R FF 83. As a result, S-R FF 83 is set and thereby an UP RAMP signal is generated. The UP RAMP signal causes the conduction of a transmission gate 85. By 30virtue of the conduction of transmission gate 79 and 85, a positive voltage V is coupled to the noninverting (+) input of differential amplifier 75 through a resistor 87 and the magnitude of the tuning voltage is caused to increase or ramp up. The DN pulse is coupled through an AND gate 89, 35enabled by the simultaneous presence of the START RAMP pulse, to the R input of S-R FF 83. As a result, S-R FF 83 is reset and a DN RAMP signal is thereby generated. The DN RAMP signal causes the conduction of transmission gate 91. By virtue of the conduction of transmission gates 79 and 91, 40positive voltage V is coupled to the inverting (-) input of 1 -11- r|A differential amplifier 75 through a resistor 93 and the magnitude of the tuning voltage is caused to decrease or 5 ramp down. The UP RAMP and DN RAMP signals are coupled to AND gates 51 and 53, respectively, to enable the appropriate one of UP voltage comparator 49 or DN voltage comparator 55 and to microprocessor 41. 10 The tuning voltage versus frequency characteristics for television receivers employing varactor diodes over the entire VHF and UHF tuning range is not continuous and includes overlapping portions as is indicated in FIGURE 2. That is, the magnitude of the tuning voltage for channel 6 15 is higher than the magnitude of the tuning voltage for channel 7, and the magnitude of the tuning voltage for channel 13 is higher than the magnitude of the tuning voltage for ■ channel 14. Accordingly, it is desirable to cause the magnitude of the tuning voltage to be rapidly changed from ; 20 the magnitude corresponding to the end of one band to the magnitude corresponding to the beginning of the next band in both the upward and downward ramping directions. A fast UP/DN control unit 95 is responsive to signals representing channels 2, 6, 7, 13, 14 and 83, i.e., the channels 25 at the boundaries of the various bands, generated by band decoder 61 to generate a FAST DN signal in the upward ramping direction and a FAST UP signal in the downward ramping direction when the end of a band is reached. Either of the FAST UP or FAST DN signals cause an 30 OR gate 97 to generate a STOP RAMP signal. The STOP RAMP signal resets S-R FF 78 and causes transmission gate 79 to be rendered nonconductive. The FAST DN signal causes a transmission gate 99 to be rendered conductive, thereby coupling positive voltage V to the inverting (-) input of 35 differential amplifier 75 through a resistor 101 having a lower resistance value than resistors 87 and 93 (used for normal ramping). As a result, in the upward ramping direction, the magnitude of the tuning voltage is relatively rapidly decreased between bands. The FAST UP signal causes 40 a transmission gate 103 to be rendered conductive, thereby 1 -12- 1 45/73145A coupling a positive voltage V to the noninverting ( + ) input of differential amplifier 75 through a resistor 105 having a 5 lower resistance than resistors 87 and 93. As a result, in the downward ramping direction, the magnitude of the tuning voltage is relatively rapidly increased between bands. The UP RAMP and DN RAMP signals are coupled to AND gates 51 and 53, respectively, to enable the appropriate one 10of UP voltage comparator 4 9 or DN voltage comparator 55, and to microprocessor 41. When the magnitude of the tuning voltage corresponding to the beginning of the next band is reached by fast ramping in either the downward or upward direction, fast 15UP/DN detector 95 terminates the appropriate one of the FAST UP or FAST DN signals. During the fast ramping intervals, tuning system 2 3 is disabled from responding to either the ADD CHANGE or the AFT VALID signals by means of NOR gate 107, AND gate 109 20 and AND gate 111 since the tuning voltage generated during these intervals changes in the wrong direction. During the normal ramping intervals, if an AFT VALID signal is generated, a STOP RAMP signal is generated by OR gate 97. In response, S-R FF 78 is reset and transmission 25 gate 79 is rendered nonconductive to terminate ramping. In addition, in response to the AFT VALID signal, transmission gates 113 and 115 are rendered conductive, thereby coupling a portion of the positive voltage V to the inverting (-) input of differential amplifier 75 as a reference voltage 30 and a portion of the AFT discriminator signal to the non-inverting (+) input of differential amplifier 75. Since any change in the tuning voltage, such as for example may be caused by the leakage of charge from capacitor 77, causes a corresponding change in the AFT signal applied to differ-35ential amplifier 75, the tuning voltage is maintained substantially constant. Microprocessor 41 controls the operation of tuning system 23 primarily by controlling the addressing of tuning voltage boundary memory 37 and channel number memory 43. 40 Microprocessor 41 (see FIGURE lc) includes input ports for 1 937^ ! -13- RCA 73145/73115A receiving various input signals generated within tuning system 23, a central processing unit (CPU) 119 for evaluating the input signals, and output ports 121 for coupling output signals 5generated by CPU 119 in response to the input signals to various portions of tuning system 23. The output signals generated by CPU 119 are determined by a program permanently stored in memory locations of a RAM (Random Access Memory) 12 3 and addressed by a RAM address register 125 under the control 10of CPU 119 as the program is executed. Before describing the program stored in RAM 123., it will be helpful to examine the arrangement of the memory locations of tuning voltage boundary memory 37 as shown in FIGURE 3. Within a band, the boundary voltages stored in memory 37 15have magnitudes substantially equal to the magnitudes of the tuning voltage at frequencies midway between the nominal frequencies of the picture carriers of adjacent channels. As a result, each of these boundary voltages represents the end of the tuning voltage range for one channel and the beginning of 20 the tuning voltage range for the next channel. Thus, for example, in the low VHF band the boundary voltages indicated + + + + by 2 , 3 , 4 and 5 correspond to the highest magnitude of tuning voltage range for channels 2, 3, 4 and 5, respectively, as well as the lowest magnitude of the tuning voltage range 25 for channels 3, 4, 5 and 6, respectively, and are therefore also identified by 3 , 4 , 5 and 6 , respectively. In addition, a boundary voltage having a magnitude substantially equal to the lowest magnitude of the tuning voltage for the lowest channel in each band, e.g., 2 , and a boundary voltage 30 having a magnitude substantially equal to the highest magnitude of the tuning range for the highest channel in each band, e.g., 6+, are stored in memory locations of memory 37. The boundary voltages and channel numbers are stored in consecutive order in memories 37 and 43, respectively. As indicated 35 in FIGURE 3, the memory locations of memories 37 and 43 are addressed in continuous circular or "wrap around" fashion in both ramping directions. The flow chart of the program stored in RAM 123 for controlling tuning system 23 is indicated in FIGURES 4a, 4b 40 and 4c. Since the program stored in RAM 123 is utilized T937-9 4 1 -14- RCA 7314D/7314LA primarily to control the addressing of memories 37 and 43, the flow chart of FIGURES 4a, 4b and 4c does not indicate certain operations of tuning system 23, such as fast up and 5 down ramping, which are controlled by portions of tuning system 2 3 outside of microprocessor 41. However, where considered helpful in facilitating an understanding in the overall operation of tuning system 23, certain operations of tuning system 23, such as the generation of the STOP RAMP 10 signal, although controlled by portions of tuning system 23 outside of microprocessor 41, are included in the flow chart shown in FIGURES 4a, 4b and 4c. When the receiver is turned on, the memory locations of memory 4 3 corresponding to channel 2 and the 15memory locations of memory 37 corresponding to the highest magnitude in the tuning range for channel 2, i.e., 2+, are addressed and an upward search for the presence of an acceptable picture carrier for channel 2 is initiated (program steps 00 through 10). As soon as any carrier is 20detected, as indicated by the presence of an AFT VALID signal, a STOP RAMP signal is generated. If the carrier is a picture carrier and is of sufficient amplitude, as indicated by the presence of both the SYNC VALID and AGC VALID signals, channel 2 is an acceptable channel and the 25tuning sequence is completed. However, if the carrier is not a picture carrier, as indicated by the absence of a SYNC VALID signal, or the carrier detected has insufficient amplitude, indicated by the absence of an AGC VALID signal, the upward search is reinitiated until a picture carrier 30having a sufficient amplitude is located. As long as no carrier is detected, as indicated by the absence of an AFT VALID signal, the memory locations of memories 4 3 and 37 are successively addressed in the order of increasing channel numbers whenever the magnitude of the tuning voltage exceeds 35the magnitude of a presently generated upper boundary voltage and the magnitude of the tuning voltage is thereafter increased in iterative fashion (program steps 11 through 17). In this operation, whenever the channel number of the first channel in the next band (in the order of increasing channel 40numbers) is reached, the address for tuning voltage boundary 1 -15- 3145/73145A 7 9 memory 3 7 is increased by one so as to skip over the lower boundary voltage for the lowest channel in the next band 5 (program steps 15 and 16). In other words, during upward searches the lower boundary voltage (7 ,14 and 2 for the lowest number channels 7, 14 and 2) in each band is skipped. The operation of addressing successive memory locations of memories 4 3 and 37 and causing the magnitude 10 of the tuning voltage to increase continues until a carrier is detected. When a carrier is detected, if it is a picture carrier and its amplitude is sufficient, the tuning sequence is completed (program steps 18, 19 and 20). If the carrier detected is not a picture carrier or its 15 amplitude is not sufficient, the search for another carrier is continued. an acceptable channel has been located, no action is taken unless UPPB 33 or DNPB 35 is depressed causing microprocessor 20 41 to generate an UP signal or a DN signal, respectively (program step 21). If the UPPB 33 has been depressed and tuning system 2 3 was previously set to ramp in the upward direction, as indicated by the UP RAMP signal (program step 22), an upward search, as described above, is initiated. 25 If UPPB 33 has been depressed and tuning system 23 was previously set to ramp in the downward direction, as indicated by the DN RAMP signal (program step 22), the address for tuning voltage boundary memory 37 is increased by one (program step 23). If the latter were not done, the boundary 30 voltage then generated would be the lower boundary voltage for the presently tuned channel rather than the upper boundary voltage. As a result, the boundary voltages generated during the subsequent upward search would be out of step with the generated channel numbers. 35 If DNPB 35 is depressed, a downward search is initiated. The downward search sequence, indicated by the flow chart shown in FIGURE 4c, is similar to the upward search sequence shown in FIGURES 4a and 4b and will not be described in detail. However, it should be noted if a 40 downward search is initiated after the termination of an Once a tuning sequence has been completed, i.e., 1 937 fM 1 - 16 - RCA 73145/73145A upward search, the address for tuning voltage boundary memory 37 is decreased by one so as to coordinate the boundary voltages and channel numbers generated during the subsequent 5 search (program steps 24 and 25). In addition, boundary voltages 83+, 13+ and 6+ for channels 83, 13 and 6, respectively, are skipped during a downward search by decreasing the address for tuning voltage boundary memory 31 when the channel number is 83, 13 or 6 (program steps 26 and 10 27) . Since the voltages stored in memory 37 are only utilized for determining the channel numbers to be displayed, they need not be as precise as voltages stored in a memory of a tuning system of the voltage synthesizer type which are 15 utilized for tuning a receiver. Nevertheless, at the present state of the art, it is difficult to specify the tuning voltage characteristics for a large number of varactor controlled tuners within 20 Predetermined limits even for displaying channel numbers. Therefore, it is desirable that the receiver manufacturer program the information in memory 37 so that the stored boundary voltages correspond to the tuning voltage characteristics of the particular local oscillator and RF portion 25 for which they are intended. For this purpose, it is desirable that memory 37 be a PROM. The binary signals representing the boundary voltages may be entered in memory 37 utilizing the arrangement shown in FIGURE 5. In the arrangement of FIGURE 5, the output of D/A converter 47 is 30 coupled to the tuning voltage input of RF unit 3 and local oscillator 7. The appropriate band selection signals are externally generated by a band selection control unit 501. Binary signals representing the address of the memory locations of memory 37 are externally generated by an 35 address register 502. In addition, test equipment including a frequency synthesizer 503, an up/down counter 504, a frequency counter 505 and a write push button 507 is connected to various portions of the receiver as shown in FIGURE 5. With this arrangement, the following setup procedures may be 40 employed to store the binary signals representing the boundary voltages. 1 "9 3 7 1 -17- RCA 73145/73145A (1) Address the memory location in which the boundary voltage is to be stored. 5 (2) Set frequency synthesizer 503 to the frequency corresponding to the boundary voltage. (3) Change the contents of up/down counter 504 until the desired IF (45.75 MHz) is indicated by frequency counter 505. (4) Depress write push button 507 to enter the 10 binary signals generated by up/down counter 504. In this arrangement since D/A converter 4 7 employed during normal operation is employed during setup, th,e errors of D/A converter 4 7 are accounted for by the set-up procedure. Another arrangement for programming memory 47 is 15 shown in FIGURE 6. With this arrangement, the following set-up procedure may be employed by means of address register 601. (1) Address the memory location in which the boundary voltage is to be stored. 20 (2) Set frequency synthesizer 602 to the frequency corresponding to the boundary voltage. (3) Adjust variable voltage source 603 until frequency counter 604 indicates the desired IF (45.75 MHz). (4) Change the contents of up/down counter 604 25 until a comparator 605 indicates a state change by means of, for example, a lamp 606 coupled to its output. (5) Press write push button 607 to enter the binary signals generated by up/down counter 604. If comparators 4 9 and 55 are included within a 30 single integrated circuit, their offset voltage characteristics will tend to be similar. Therefore, it may be desirable to employ one of voltage comparators 49 and 55 as comparator 605 so that their offset voltage characteristics are accounted for during setup. 35 FIGURE 7 shows a logic implementation of fast up/down control unit 95 (shown in block diagram form in FIGURED. During an upward search, whenever binary signals representing the channel number of the last channel in a band, i.e., channel number 06, 13 or 83, are generated by channel 40 number memory 43 (of the arrangement shown in FIGURE 1), 1 -18- 1 9 3 7 o l'.c^7>riy/73i'i5A band decoder 61 (of the arrangement shown in FIGURE 1) generates a signal representing the occurrence. In response, 5 an OR gate 701 couples a high level logic signal to the S (Set) inputs of D (Data) FFs 703 and 705 thereby causing low level logic signals to be developed at their Q outputs. As soon as binary signals representing the channel number of the first channel in the next band, i.e., channel number 10 07, 14 or 02, are generated, a high level FAST DN ENABLE logic signal is generated by the logic configuration including logic gates 707, 709, 711, 713, 715 and 717. At the same time, OR gate 717 generates a high level logic signal which triggers a monostable multivibrator (MSI1V) 719. MSJ1V 719 15generates a positive-going FAST DN TIME pulse which has a duration sufficiently long for the fast down ramping interval to be completed. In response to the UP RAMP signal generated by S-R FF 8 3 (of the arrangement shown in FIGURE lb) and the FAST DN ENABLE and FAST DN TIME signals, an AND gate 721 20generates a high level FAST DN signal. The FAST DN signal terminates when the tuning voltage has a magnitude substantially equal to the lowest magnitude of the tuning voltage range of the lowest channel in the next band. A comparator 72 3 determines when the tuning 25voltage has a magnitude corresponding to the beginning, in the upward direction, of the tuning voltage range for channel 7. When the beginning of the tuning voltage range for channel 7 is reached, a high level logic signal is coupled to the C (Clock) input of D FF 703. As a result, since the 30D input of D FF 703 is coupled to signal ground, D FF 703 is reset causing a high level logic signal to be developed at its Q output. In response, by means of logic gates 707, 709 and 711, the FAST DN ENABLE signal becomes a low logic level, and by means of AND gate 721, the high level FAST DN 35signal is terminated (i.e., becomes a low logic level). Assuming that the magnitudes at the beginnings of the tuning voltage ranges, in the upward scanning direction, for channels 2 and 14 are approximately the same (as shown in FIGURE 2), a single comparator 725 may be used 40to determine when the tuning voltage has a magnitude 1 937<M 1 -19- RCA 73145/73145A corresponding to the beginning of the tuning voltage ranges for channels 2 and 14. When the beginnings of the tuning 5 voltage ranges for channels 2 and 7 are reached, D FF 705 is reset and by means of logic gates 713, 715, 709 and 711 the FAST DN ENABLE signal becomes a low logic level, and by means of AND gate 711 the high level FAST DN signal is terminated (i.e., becomes a low logic level). 10 During a downward search, by means of OR gate 717 a D FF 727 is set when the binary signals representing the lowest channel number, i.e., channel number 02, 07 or 14, in a band are generated. As soon as binary signals representing the first channel number in the next band, i.e., 15channel number 83, 06 or 13, are generated, an AND gate 729 generates a high logic level FAST UP ENABLE signal. At the same time, MSI1V 731 is tirggered by means of OR gate 701 to generate a high logic level FAST UP TIME pulse which has a duration sufficiently long for fast down ramping to be 20completed. An AND gate 7 33, in response to the FAST UP ENABLE signal, FAST UP TIME pulse and DN RAMP signal, generates a high level FAST UP signal. When the tuning voltage has a magnitude corresponding to the beginning of the tuning ranges for the highest channels in the next bands, 25assuming that these magnitudes are approximately the same (as shown in FIGURE 2), a comparator 735 causes D FF 727 to be reset. As a result, the high logic level FAST UP ENABLE and FAST UP signals are terminated. While the threshold voltages for comparators 72 3, 3072 5 and 7 35 of the implementation of control unit 95 shown in FIGURE 7 are derived from a resistive divider 736, it is noted that they may be derived by addressing corresponding memory locations of TV boundary memory 37 during the fast up and fast down ramping intervals. 35 An implementation of AFT comparator 63 shown in block diagram form in FIGURE la is shown in FIGURE 8. AFT comparator 63 includes a comparator 801 for detecting a predetermined voltage corresponding to the positive "hump" of the AFT voltage and a comparator 803 for detecting a pre-^Odetermined voltage corresponding to the negative "hump" of 1 937~ ' 1 - 20 - .RCA 73115/73145A the AFT voltage. The remaining logic portion of AFT comparator 63 detects the sequence of the "humps" of the AFT voltage to determine whether the AFT voltage is in its control 5range, i.e., the portion between the humps, thereby indicating that a carrier has a frequency near enough to the desired IF (45.75 MHz) so that normal ramping may be stopped. For this purpose, the logic portion of AFT comparator 63 is arranged so that 10 when the frequency of the local oscillator is being increased and, as a result, the frequency of the IF signal is being decreased, the negative hump is detected before the positive hump and that when the frequency of the local oscillator signal is being decreased and, as a result, the frequency 15 of the IF signal is being increased, the positive hump is detected before the negative hump. When the second of the two humps is detected, an AFT VALID signal is generated. The logic portion of AFT comparator 63 is arranged so that after a carrier has been detected, the first hump detected 20 thereafter is disregarded in a subsequent sequence detection operation. This is done since, in this situation, when ramping is again initiated, the first hump detected is associated with the previously detected carrier rather than the next one. The logic portion of AFT comparator 6 3 includes four D FFs 805, 807, 809 and 811 which are reset in response to a START RAMP signal. Assuming that the ramping direction is downward, i.e. , the frequency of the IF signal is increasing, i the first hump detected will be the negative hump associated ^ with the previously detected carrier. Accordingly, D FF 805 30 is set and an AND gate 813 is enabled. The next hump detected will be the positive hump associated with the next carrier. Accordingly, D FF 807 is set and AND gate 815 is enabled. In addition, since AND gate 813 was already enabled, D FF 809 is set. However, since an AND gate 817 35 is disabled due to the absence of a high logic level UP RAMP signal, an AFT VALID signal is not generated by an OR gate 819. The next hump detected will be the negative hump associated with the next carrier. Accordingly, since AND gate 815 was already enabled by set D FF 807, D FF 811 is set. 1 -21- 193794 RCA 7314D/73145A Since an AND gate 821 is enabled by a high logic level DN RAMP signal, an AFT VALID signal is generated by OR gate 819. 5 Thus, in the downward ramping direction, the first negative hump is disregarded and an AFT VALID signal is generated after a positive hump—negative hump sequence. In the upward ramping direction, the logic portion of AFT comparator 63 operates in a similar fashion to disregard 10 the first positive hump and generate an AFT VALID signal after a negative hump—positive hump sequence. Since the portions of automatic channel detection circuit 31 for evaluating the synchronization and AGC signals are well known in the signal seeking art, no detailed 15 description of these components of the present system will be provided. While automatic channel detection circuits 31 have been described with reference to the specific arrangement shown in FIGURE la, -it will be appreciated that other 20 arrangements for the same purpose, such as for example, the arrangement disclosed in U.S. Patent Number 3,632,864, may be employed. Furthermore, while the present tuning and channel number identification system has been described in terms of an automatic signal seeking system, the channel 25 identification apparatus may include tuning systems in which a ramp or ramp-like tuning voltage is generated in response to manual control, by means of a potentiometer arrangement or the like, until an acceptable channel is located. These and other modifications are intended to be included within 30 the scope of the present invention as defined by the following claims. 35 40 </div>

Claims

<div class="application article clearfix printTableText" id="claims"> 1C3794 - 22 - RCA 73145/73145A WHAT WE CLAIM IS:-

1. Apparatus for tuning a television receiver to various channels, within separated frequency bands, said channels being bounded by respective upper and lower frequency boundaries, comprising: local oscillator means responsive to a tuning voltage for generating a local oscillator signal having frequencies for tuning said receiver to said channels; tuning control means for generating said tuning voltage; said tuning control means including direction means for selectively causing the frequency of said local oscillator signal to be changed in an increasing or decreasing sense; memory means including a plurality of memory locations for storing binary signals respectively corresponding to said frequency boundaries; address means for addressing said memory locations; comparison means for generating an address change signal when the frequency of said local oscillator signal traverses a frequency corresponding to a boundary stored in an addressed one of said memory locations; control means for causing said address means to address the memory location corresponding to the next consecutive boundary in response to said address change signal; channel number means for generating binary signals representing channel numbers; display means for displaying channel numbers in response to the binary signals generated by said channel number means; said memory means includes a plurality of memory locations associated with each of said bands for tuning said television receiver to various channels within said separated frequency bands; for each of said bands there being a boundary corresponding to the lowest frequency channel in said band, \ /' .■'O J/ 193794 m v // - 23 - RCA 73145/73145A a plurality of boundaries corresponding to adjacent channels within the band, and a boundary corresponding to the highest frequency channel in said band; each of said memory locations having an associated address; said control means causes said address means to address the memory location corresponding to the next consecutive boundary in the order corresponding to the sense of change of the magnitude of said tuning voltage in response to said address change signal as long as the frequency of said local oscillator is changing substantially, causes said address means to skip over the addresses of ones of said memory locations associated with the boundaries corresponding to the lowest frequency channels in said bands when the frequency of said local oscillator signal is being increased, causes said address means to skip over the addresses of ones of memory locations associated with the boundaries corresponding to the highest frequency channels in said bands when the frequency of the local oscillator is being decreased, and causes said channel number means to generate the binary signals representing the channel number next in the order corresponding to the sense of change of frequency of said local oscillator in response to said address change signals as long as the frequency of said local oscillator is changing substantially.

2. The apparatus recited in Claim 1 wherein said memory locations store respective boundary voltages and said comparison means generates said address change signal when a predetermined one of the magnitude of the boundary voltage stored in an addressed one of said memory locations and the magnitude of said tuning voltage exceeds the other.

3. The apparatus recited in Claim 2 wherein: said control means causes said address means to skip over the addresses of memory locations associated with the boundary voltages corresponding to the lower boundaries for the tuning voltage ranges for the lowest frequency channels in said bands when the magnitude of said tuning voltage is being increased and said channel number means generates binary signals representing the channel numbers No- ' ; v J 183794 24 RCA 73145/73145A of the lowest frequency channels in respective ones of said bands and causes said address means to skip over the addresses of memory locations associated with the boundary voltages corresponding to the upper boundaries for the tuning voltage ranges for the highest frequency channels in said bands when the magnitude of said tuning voltage is being decreased and said channel number means generates binary signals representing the channel numbers of the highest frequency channels in respective ones of said bands.

4. The apparatus recited in Claim 3 wherein: magnitudes of said tuning voltage at frequencies between tuning voltage ranges for respective adjacent channels within said bands have magnitudes substantially equal to the magnitudes of said tuning voltage at frequencies midway between the frequencies of picture carriers of said respective adjacent channels.

5. The apparatus recited in Claim 4 wherein: said tuning voltage means includes fast down ramping means for relatively rapidly decreasing the magnitude of said tuning voltage until the magnitude of said tuning voltage at least approximately equals the magnitude of the boundary voltage for the highest voltage range for the lowest frequency channel in the next band after said channel number means generates binary signals representing the channel number of the highest frequency channel in the respective preceding one of said bands during an interval in which the magnitude of said tuning voltage was being increased; and fast up ramping means for relatively rapidly increasing the magnitude of said tuning voltage until said tuning voltage at least approximately equals the boundary voltage for the tuning voltage range for the highest frequency channel in the next band after said channel number means generates binary signals representing the channel number of the lowest frequency channel in the respective preceding one of said bands said boundary voltages corresponding to the 193794 - 25 - RCA 7314 5/73145A during an interval in which the magnitude of said tuning voltage was being decreased.

6. The apparatus recited in Claim 1 wherein: said control means includes automatic channel detection means including at least carrier detection means for determining the presence of carriers associated with said channels; and said tuning voltage means includes stopping means for inhibiting the magnitude of said tuning voltage from changing substantially after one of said carriers is detected.

7. The apparatus recited in Claim 6 wherein: said automatic channel detection means also includes picture carrier detection means for determining when a detected one of said carriers is not a picture carrier; and said tuning voltage means includes starting means for causing the magnitude of said tuning voltage to again change in the same sense it was changing before it was inhibited from substantially changing when said detected carrier is not a picture carrier.

8. The apparatus recited in Claim 7 wherein: said picture carrier detection means includes an automatic fine tuning (AFT) discriminator responsive to an IF signal generated by said receiver for generating an AFT signal having a first portion with a first polarity when one of said carriers has a frequency below a predetermined nominal frequency and a second portion with a second polarity when one of said carriers has a frequency above said predetermined nominal frequency; and sequence detection means for generating an AFT valid signal representing the presence of one of said carriers when said first portion of said AFT signal is generated after said second portion as the magnitude of said tuning voltage is being increased and when said second portion is generated after said first portion as the magnitude of said tuning voltage is being decreased. ■ /. . !U-.' \: \. 193794 - 26 - RCA 73145/73145A

9. The apparatus recited in Claim 8 wherein: said sequence detection means includes means for disregarding said first and second portions of said AFT signal immediately after said starting means causes the magnitude of the tuning voltage to again change.

10. The apparatus recited in Claim 7 wherein: said picture carrier detection means includes means for determining the average value of a synchronization signal generated by said receiver.

11. The apparatus recited in Claim 2 or 4 wherein: said comparison means includes a first comparator means for generating a first output signal when the magnitude of said tuning voltage exceeds the magnitude of the boundary voltage stored in an addressed one of said memory locations and the magnitude of said tuning voltage is being increased; a second comparator means for generating a second output signal when the magnitude of said tuning voltage falls below the magnitude of the boundary voltage and the magnitude of said tuning voltage is. being decreased; and combining means for generating said address change signal in response to either one of said first and second output signals

12. Apparatus for tuning a television receiver to various channels substantially as herein described with reference to the accompanying drawings. x ■tr V * , v.- BALDWIN, SON & CAREY attorneys for the applicants </div>