JPS5963083A - High speed buffer memory device - Google Patents

Abstract

PURPOSE:To test simultaneously a memory cell part in a compartment by switching an operation mode to a test mode by a flip-flop and an OR gate group. CONSTITUTION:A normal operation mode sets a flip-flop 2 to a state ''0'' and designates it. Accordingly, in case of a write operation, one of output signal lines 10-13 from a compartment selecting circuit 1 becomes a state ''1'', therefore, only one signal line of the output signal lines 30-33 from an OR gate group 3 becomes ''1'', and data is written in an address designated by an address signal line 4. In case of a read-out operation, the data is read out of a buffer memory designated by the address signal line 4. The test mode sets the flip- flop 2 to a state ''1'' and designates it. Accordingly, in case of a write operation, the state ''1'' is inputted to a write approval terminal of all buffer memories, and the data is written simultaneously in the address designated by the address signal line 4. In case of a read-out operation, a data on a buffer memory address designated by the address signal line 4 is read out simultaneously, and the state ''1'' is inputted to all output inhibiting terminals S of buffer selecting circuits 70-73.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a high-speed buffer device comprising a plurality of compartments, and more particularly to a high-speed buffer device equipped with a circuit configuration for testing the buffer device in a short time.

(Description of the Prior Art) Conventionally, in order to test a cell portion of a high-speed buffer memory device having a plurality of compartments, it has been necessary to repeatedly write and read data sequentially to each compartment. Therefore, as the capacity of the high-speed buffer memory increases, there is a drawback that the test execution time for the cell portion becomes significantly longer.

(Detailed Description of the Invention) Object of the Invention The present invention is equipped with compartments whose number of seconds can be specified by the σ compartment selection circuit, and is capable of simultaneously testing each compartment consisting of a buffer memory and a buffer memory 4 selection circuit. It is an object of the present invention to provide a high-speed buffer memory device configured as described above to eliminate the above-mentioned drawbacks and to allow testing of the cell portion to be easily performed in a short time.

(Description of structure and operation of the invention) In the present invention, the high-speed buffer memory device includes a compartment selection circuit and a flip-flop.

A group of OR gates and multiple buffer memories.

It is equipped with a plurality of buffer selection circuits and an exclusive OR gate. The compartment selection circuit is a circuit for selecting one of a plurality of compartments. Is the flip-flop in normal operation mode?
This is a circuit for determining whether to enter test mode or not. The OR gate group is an axle circuit that performs the OR of compartment designation and operation mode designation for each compartment. A plurality of buffer memories are provided for each compartment and are circuits for storing data. A plurality of buffer selection circuits are provided for each compartment and select data corresponding to each buffer memory. The exclusive OR gate is for calculating the exclusive OR of outputs from a plurality of buffer selection circuits.

(Explanation of Examples) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a high speed buffer memory device according to the present invention. In FIG. 1, the fixed speed buffer memory device includes a compartment selection circuit 1, a Noritub flop 2, an OR gate group 3, first to fourth buffer memories 60 to 63, and buffer selection circuits 1 to 4. The circuits 70 to 73 and the exclusive OR gate 8? It is equipped with The first buffer memory 60 and the first buffer selection circuit 70 form a first compartment,
Second buffer memory 61 and second buffer selection circuit 7
1 forms a second compartment member If, a third buffer memory 62 and a third buffer selection surface 1 72 and tIi
A third compartment is formed, and a fourth compartment is formed in the fourth buffer memory 63 and the fourth buffer selection circuit 13. That is, the high speed buffer memory device of FIG. 1 includes four compartments i. The compartment selection circuit 1 has all the first to fourth valid indication signal lines 10 to 13 for each compartment, and the first to fourth valid indication signal lines 1 are connected to the sum gate group 3.
Connected by 0-13. The flip-flop 2 specifies the operation mode, and the output tram of the flip-flop 2 is connected to the logical sum gate group 3. The OR gate group 3 is a gate group for calculating the OR of the output of the flip-flop 2 and the output of the compartment selection circuit 1. ~'11~ The fourth buffer memories 60 to 63 are already 1
As explained in , each compartment is provided with the first to fourth output signal lines 30 to 3 of the OR gate group 3.
First to fourth buffer memories 60 corresponding to 3u, respectively
It is connected to the input permission terminal of ~63. This is for selecting output data from the first to fourth buffer selection circuits 70 to 73Hi'tL1 to the fourth buffer memories 60 to 63. The first to fourth output signal lines 30 to 33 from the OR gate group 3 are connected to the first to fourth buffer selection circuits 7
0 to 73 are connected to the output suppression terminals SK. Exclusive OR gate 81d: Silk 1 to 4th buffer selection circuit 70
.about.73 to determine the exclusive OR of the outputs of the first to fourth buffer selection circuits 70 to 73.

Next, the operation of the present invention will be explained in detail separately during normal operation and during testing.

During normal operation, flip-flop 2 is set to state 700, tl. That is, in the normal operation mode, the purpose is determined by setting the two frillafs to state 0. In this state -c, the H OR gate group 3 receives the first to fourth outputs from the compartment selection circuit 1. = No. 10-1
3 is directly output to the first to fourth output signal lines 30 to 33 of the OR gate group 3. Therefore, in a write operation, the first
~ Since one of the fourth output lines 10 to 13 is in state 1, only one signal line among the first to fourth output lines 30 to 33 from the OR gate group 3 is in the state. is 1
It has become. That is, compartment selection circuit 1
Data signal line 5 is connected to the address specified by address signal line 4 for one buffer memory selected by
Data is written through the meeting.

In a read operation, data is read from all buffer memories designated by address signal line 4. Since the first to fourth output signal lines 30 to 33 from the OR gate group 3 are connected to the output suppression terminals S of the first to fourth buffer selection circuits 70 to 73, the compartment selection circuit Only the data from one buffer memory selected by the buffer selection circuit? 0,71.7
2° or 73, and the output state of the other buffer selection circuits is 0. Therefore, the data of the buffer memory selected by the compartment selection circuit 1 is outputted from the exclusive OR gate 8.

Flip-flop 2 is set to state 1 during testing. That is, the test mode is designated by setting flip-flop 2 to state 1. In this state, the first to fourth output signal lines 30 to 33rI'i of the OR gate group 3 are always in state 1, regardless of the value of the output of the compartment selection circuit 1. Therefore, state 1 is input to the write enable terminals of all buffer memories in case of a biting operation, and data is simultaneously written to the address specified by the address signal line 4 via the data signal line 5. In a read operation, the data on all buffer memory addresses specified by the address signal line 4 are simultaneously 'i□q
State 1 is input to all of the output suppression terminals S of .

Therefore, all paramemories 60 of 1 to 4)
63 are output from the first to fourth buffer selection circuits 70 to 73 and input to the exclusive &f+rational sum gate 8. In the exclusive OR gate 8, all the first to fourth buffer memories 60 to 63 to 1jfJi
The data in state 1 are compared with each other, and the data in state 1 is determined from only the mismatched bits in the LH force signal f4i! 9 Complete speech ♂ quality]
I will be treated.

In the actual HA example of the high-speed buffer memory device according to the present invention, by specifying the operation mode, it is possible to operate only the essential buffer memories during normal operation, but by specifying all test modes, all Writing and reading can be done simultaneously to the buffer memory. Therefore, when testing the memory cells constituting the buffer memory, it is possible to test all the memory cells of the buffer memory within the access time required to access the memory cells of one buffer memory.

(Questions regarding the effects of the invention) As explained above, the present invention includes a compartment selection circuit, a flip-flop, and a logical sum 11! f...!
:,? It is equipped with several buffer memories, a plurality of buffer selection circuits, and an exclusive sum gate, and each buffer memory and buffer selection circuit form a conversion member), and the operating mode is all flip-flops and logic. By switching to the test mode using the sum gate group, it is possible to simultaneously test all the memory cell □ portions in all compartments in a short time.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating an embodiment of a high j5 roughness memory device according to the present invention. 1... Compartment selection circuit 2 Ken Flip-flop 3... OR gate group 60-63... Buffer memory 70-13 Buffer selection circuit 8... Exclusive OR gate patent applicant NEC Corporation Representative Patent Attorney Hisashi Inoro

Claims (1)

[Claims] In a high-speed buffer memory device having a plurality of compartments, a compartment selection circuit for selecting one of the plurality of compartments, a flip-flop for determining a normal operation mode or a test mode, and a compartment selection circuit for selecting one of the plurality of compartments; a group of success/fail disjunction gates from a plurality of gates for calculating the logical sum of the designation and the designation of the operation mode in each of the plurality of compartments; a plurality of buffer memories for storing data;
7, each of the plurality of compartments is provided with a plurality of buffer selection circuits for selecting data, and an exclusive OR gate for calculating the exclusive OR of outputs from the buffer selection circuit. It has all features of high speed buffer memory device.