JPS5961950A - Semiconductor device and lead frame used for assembling the same - Google Patents
Semiconductor device and lead frame used for assembling the sameInfo
- Publication number
- JPS5961950A JPS5961950A JP57170886A JP17088682A JPS5961950A JP S5961950 A JPS5961950 A JP S5961950A JP 57170886 A JP57170886 A JP 57170886A JP 17088682 A JP17088682 A JP 17088682A JP S5961950 A JPS5961950 A JP S5961950A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- wire
- connection
- header
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明にレジンパッケージ型半導体装置およびその組立
に用いるリードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin packaged semiconductor device and a lead frame used in its assembly.
レジンパッケージ型半導体装置の一つとして、第１図に
示すようなＴＯ−２２０型のトランジスタが知らｎてｂ
る。このトランジスタｌｉｄ平行に延在する３本のリー
ド２全有してｂる。そして、中央のり−ド２は内端部で
下方に折れ曲がシ、その先端でヘッダ３と呼ぶ幅広の導
板に連結されている。ヘッダ３のリード側内端部上面に
はトランジスタ用のベレット４が固定δれている。また
、ベレット４のエミッタ、ベース、コレクタの各電極は
対応するリード２の内端部にワイヤ５を介して接続され
て込る。また、ヘッダ３の内端部からリード２の内端部
分はレジンモールドによるモールド体６によってパッケ
ージされている。ヘッダ３は下面が露出し、放熱面とな
っている。なお、ヘッダ３は各リード２よシもそのＮ嘔
が厚くなっ−（ｔｎる。そこで、組立に用いるリードフ
レームは、一部が厚い異形材全町ち抜いてパターニング
化した後、中央のリードを一段、階段状に折シ曲げてＩ
Ｊ−）−７レームを形成したシ、あるいは厚いヘッダと
薄いリード列と音別々に形成した後、先端が下方に折シ
曲げら７れた中央リード’ｒ−、ラダに設けた切込部に
カシメによって接続してリードフレームヶ形成している
。As one of the resin packaged semiconductor devices, the TO-220 type transistor shown in Figure 1 is well known.
Ru. This transistor lid has all three leads 2 extending in parallel. The center beam 2 is bent downward at its inner end and is connected to a wide conductive plate called a header 3 at its tip. A transistor pellet 4 is fixedly disposed on the upper surface of the inner end of the header 3 on the lead side. Further, the emitter, base, and collector electrodes of the pellet 4 are connected to the inner ends of the corresponding leads 2 via wires 5. Further, the inner end portion of the header 3 and the inner end portion of the leads 2 are packaged with a molded body 6 made of resin mold. The lower surface of the header 3 is exposed and serves as a heat radiation surface. Note that the header 3 is thicker than each lead 2. Therefore, the lead frame used for assembly is made by cutting out and patterning the entire section of the deformed material that is partially thick. Fold it into a step shape and make I
J-)-7 A frame is formed, or a thick header and a thin lead row are formed separately, and then the tip is bent downward and the center lead 'r- is formed, and a notch is made in the ladder. It is connected by caulking to form a lead frame.
このようなトランジスタでは、中央のリードであるコレ
クタリードにワイヤを接続する際ワイヤはコレクタリー
ドのＨＩ１曲げ部分上に接続さｎ易い。丁なわち、設計
上でに平坦となった部分にワイヤが接続されるようにな
っていても、ワイヤボンディングの接続位置のバラツキ
によってワイヤが曲面上に接続されることもあシ、また
、リードフレームの加工精度のバラツキによって平坦と
なる部分であっても、実際にはまだ平坦とにならない曲
面部分である場合もある。In such a transistor, when connecting a wire to the collector lead, which is the central lead, the wire is likely to be connected onto the HI1 bent portion of the collector lead. In other words, even if the wire is connected to a flat part by design, the wire may be connected on a curved surface due to variations in the connection position of the wire bonding. Even if a portion becomes flat due to variations in the machining accuracy of the frame, it may actually be a curved portion that is not yet flat.
功、在はパンケージの小型化が図ら７Ｌでいるためさら
にワイヤがリードの折れ曲げ部分上に接続され易くなる
。In fact, the size of the pan cage has been reduced to 7L, making it easier to connect the wire to the bent portion of the lead.
この結果、曲面ＨＩ３分に接続さｔ′したワイーヤにそ
の接続強度が弱く接続の侶頼性瀘低くな広 トランジス
タの製造歩留の低下、（ｇ顕性の低下を来たしてしまう
。As a result, the wire connected to the curved surface HI3 has a weak connection strength, and the reliability of the connection is low.This results in a decrease in the manufacturing yield of wide transistors, and a decrease in g sensitivity.
したがって、本発明の［１的は、一部のリードの内端が
下方に折れ曲がってヘッダに連結され、かつこの折れ曲
がったリードの内端部にワイヤ？接続する構造の半導体
装置におけるワイヤの接合強度向上を図ることにある。Therefore, [one object] of the present invention is that the inner ends of some of the leads are bent downward and connected to the header, and that the inner ends of the bent leads are connected to wires. The object of the present invention is to improve the bonding strength of wires in semiconductor devices having a connecting structure.
このような目的音達成するために不発明に、一部のリー
ドの内端が下方に折れ曲がって−・ラダにｌさｎ、〃・
つこのリードの内端部分には該ＩＪ−ドより分岐した平
ｊ旦な接続用突子が設けられてなるリードフレームを用
すて半導体装１腹全製造してなるものでおシ、半導体装
置の状態では６＋１記−ラダ上に固定したべＶットの所
定の電極に接続したワイヤにその一端？前記接続用突子
上に接続してなるものである。In order to achieve this desired sound, the inner ends of some reeds are inventively bent downwards.
The entire semiconductor device is manufactured using a lead frame in which the inner end portion of the lead is provided with a flat connecting protrusion branching from the IJ. In the state of the device, one end of the wire is connected to a predetermined electrode of the 6+1 beam fixed on the ladder. It is connected to the above-mentioned connecting protrusion.
以下、＃／、施列によυ本発明全説明する。Hereinafter, the present invention will be fully explained using #/ and arrangement.
第３図は本発明の一爽ｍ列によるトランジスタ勿示す一
部紮切シ欠いた平面図、第２図は同じく断面図、第５図
は同じくトランジスタ全製造する除用いるリードフレー
ムの斜視図である。FIG. 3 is a partially cutaway plan view of a transistor according to the present invention, FIG. 2 is a cross-sectional view, and FIG. be.
この実施列のトランジスタ１は平行に延在する３本のり
一ド２葡有している。そして、中央のり一ド２は内端部
で二叉に分岐し、一方は下方に折れ曲がシ、その先端で
ヘッダ３と呼ぶ幅広の導板に連結されている。また、分
岐した曲刃は前記折れ曲が９部分の側方に突出して接続
用突子７全形作っている。この接続用突子７は平坦（フ
ラット）となシ、両側のり一ド２の内端部と同様にワイ
ヤ接続領域を形作っている。両側のリード２のワイヤ接
続領域は両側に張出部を有して後述するモールド体から
抜は難いように引掛けるようになっている。The transistors 1 in this implementation column have three lines extending in parallel. The central glue 2 branches into two at its inner end, one of which is bent downward, and its tip is connected to a wide conductive plate called a header 3. Further, the branched curved blade protrudes to the side of the bent portion 9 to form the entire connecting protrusion 7. This connecting protrusion 7 is flat and forms a wire connection area as well as the inner ends of the glue 2 on both sides. The wire connection areas of the leads 2 on both sides have projecting portions on both sides so that they can be hooked so as to be difficult to remove from the molded body, which will be described later.
ヘッダ３のリード側内端部上面にはトランジスタ用のベ
レット４が固定されている。筐之、ペレット４のエミッ
タ、ベース、コレクタの各電極は対応するリード２のワ
イヤ接続領域に接続さｎている。筐た、−ラダ３の内端
部からり一ド２の内端部分はレジンモールドによるモー
ルド体６によってパンケージ芒ｎて込る。ヘッダ３は下
面がモールド体６から露出し、放熱面となっている。１
＾、ヘッダ３は各リード２の厚さよシも厚くなっている
。葦り、ヘッダ３のモールド体６によって被われない左
端中央部にはこのトランジスタ１ケ取付板等に固定する
際使用する取付孔８が設けらｎている。A transistor pellet 4 is fixed to the upper surface of the inner end of the header 3 on the lead side. The emitter, base, and collector electrodes of the housing and pellet 4 are connected to the wire connection areas of the corresponding leads 2. The inner end of the ladder 3 and the inner end of the ladder 2 are inserted into the pan cage awn by a mold body 6 made of resin mold. The lower surface of the header 3 is exposed from the molded body 6 and serves as a heat radiation surface. 1
^, The header 3 is thicker than each lead 2. At the center of the left end of the header 3 which is not covered by the molded body 6, there is provided a mounting hole 8 for use in fixing this transistor to a mounting plate or the like.
このようなトランジスタ１に中央のり一ド２へのワイヤ
５の接続は、従来のようなり一ド２の折ｎ曲がり近傍へ
の接続とは異なり、特別に設りた平坦な接続用突子７へ
の接続となるため、ワイヤ接合に何等不具合が生ぜず、
弥い接合強度を有するワイヤ接続が行なえる。したがっ
て、ワイヤ剥離、ワイヤ接続不良は起きないため、歩留
の向上全図ることができるとともに、ワイヤ接続の１ｇ
頼度、トランジスタとしての信頼度が向上する。The connection of the wire 5 to the center wire 2 of the transistor 1 is different from the conventional connection near the bend of the wire 2 by using a specially provided flat connecting protrusion 7. Since the wire is connected to the
Wire connections with high bonding strength can be made. Therefore, wire peeling and wire connection failures do not occur, so it is possible to improve the yield completely, and the wire connection
reliability and reliability as a transistor is improved.
つぎに、このトランジスタ１の組立ＮＩＱに用いるリー
ドフレームにつ論て第５図７参照しながら説明する。リ
ードフレーム９は埋い部分と薄い部分七有する異形材を
プレスによって所望形状に打ち抜くとともに、一部で階
段状に折り曲げることによって形成される。丁なわち、
異形制の厚肉部はヘッダ３が形作らｎＸ薄肉部は３本の
ＩＪ −ト” ２およびこｎらリード２を連結する枠片
１０．ダム片１１が形作られる。３本のり一ド２のうち
、中央のり一ド２はその内端部は二叉に形成場れ、一方
は折シ曲けられてヘッダ３と連結し、曲刃に折シ曲げ部
分の側方に延在する接続用突子７を形作る。筐た、ヘッ
ダ３の左端中央には取付孔８が、砕片１０にはリードフ
レーム９の取扱時のガイドして用いるガイド孔１２が設
けられている。Next, the lead frame used in the assembly NIQ of this transistor 1 will be explained with reference to FIG. 5. The lead frame 9 is formed by punching out a profiled material having seven buried portions and seven thin portions into a desired shape using a press, and bending some portions into a step shape. Ding, that is,
The thick part of the irregular shape is formed by the header 3, and the thin part is formed by the three IJ-to'' 2 and the frame piece 10 and dam piece 11 that connect the leads 2. Among them, the inner end of the central glue 2 is formed into two forks, one of which is bent to connect with the header 3, and one of which is bent into a curved edge and extends to the side of the bent part for connection. A protrusion 7 is formed.A mounting hole 8 is provided in the center of the left end of the header 3 in the housing, and a guide hole 12 is provided in the fragment 10 to be used as a guide when handling the lead frame 9.
このようなリードフレーム９にあっては、トランジスタ
の組立においては、ヘッダ３の上面所定部にベレット４
を固定した後、このベレット４の電極とリード２の内端
（中央リード２にあっては接続用突子７）とをワイヤ５
で接続する。その後、レジンモールドによって所定部を
被い、不要となったダム片１１および枠片１０會切断除
去して、第３図に示すようなトランジスタｔｒ製造する
。In such a lead frame 9, when assembling a transistor, a pellet 4 is attached to a predetermined portion of the upper surface of the header 3.
After fixing, connect the electrode of this pellet 4 and the inner end of the lead 2 (the connecting protrusion 7 for the center lead 2) with the wire 5.
Connect with. Thereafter, a predetermined portion is covered with a resin mold, and the unnecessary dam piece 11 and frame piece 10 are cut and removed to manufacture a transistor tr as shown in FIG.
なお、本発明は前記実施列に限定されない。丁なわち、
−ラダ３と中央のり一ド２はカシメ等によって連結さｎ
る構造でもより０
１た、本発明はトランジスタ以外の集積回路等にも適用
できる。Note that the present invention is not limited to the above embodiments. Ding, that is,
- The ladder 3 and the center glue 2 are connected by caulking etc.
In addition, the present invention can also be applied to integrated circuits other than transistors.
以上のように、本発明によれば、一部のリードの内端が
下方に折ｎ曲がって−・ラダに連結され、かつこの折ｎ
曲がったリードの内端部にワイヤを接続する構造の半導
体装置におりて、ワイヤの接合強度の向上を図ることが
できる。As described above, according to the present invention, the inner ends of some of the leads are bent downward and connected to the ladder.
In a semiconductor device having a structure in which a wire is connected to the inner end of a bent lead, it is possible to improve the bonding strength of the wire.
第１図は従来のトランジスタ全示す平面図、第２図は同
じく断面図、
第３図は本発明の一実施例によるトランジスタの平面図
、
第４図は同じく断面図、
第５図に同じくリードフレーム全売す斜視図である。
１・・・トランジスタ、２・・・リード、３・・・ヘッ
ダ、４・・・ベレット、５・・・ワイヤ、６・・・モー
ルド体、７・・・接続用突子、９・・・リードフレーム
。
計
！
」
＼ｂFig. 1 is a plan view showing the entire conventional transistor, Fig. 2 is a cross-sectional view, Fig. 3 is a plan view of a transistor according to an embodiment of the present invention, Fig. 4 is a cross-sectional view, and Fig. 5 is a lead-in view. It is a perspective view of the entire frame. DESCRIPTION OF SYMBOLS 1...Transistor, 2...Lead, 3...Header, 4...Bellet, 5...Wire, 6...Mold body, 7...Connecting protrusion, 9... Lead frame. Total! ”\b
Claims (1)
結されるとともに、ハンダ上に固定したベレットの所定
電極に接続されたワイヤの一端をこの折れ曲がＤ ＩＪ
−ドの内端部分に接続してなる半導体装置において、前
記ヘッダに連結嘔れたリードの内端部分には、該リード
よ多分岐した平坦な接続用突子が設けられていることに
％徴とする半導体装置。 ２、一部のリードの内端が下方に折れ曲がりて−・ラダ
に連結さｎてなるリードフレームにおいて、前記ヘッダ
に連結されたリードの内端部分には、該リードよ多分岐
した平坦な接続用突子が設けらｎていること’に’Ｆｔ
徴とするり−ドフレーム。[Scope of Claims] 1. The inner ends of some of the leads are bent downward and connected to the lead, and one end of the wire connected to a predetermined electrode of a pellet fixed on the solder is I.J.
- In the semiconductor device connected to the inner end portion of the lead, the inner end portion of the lead connected to the header is provided with a flat connecting protrusion that is multi-branched from the lead. Semiconductor device with special characteristics. 2. In a lead frame in which the inner ends of some of the leads are bent downward and connected to the ladder, the inner ends of the leads connected to the header have flat connections that branch out from the leads. 'Ft' means that a protrusion is provided.
The sign is a rolled frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57170886A JPS5961950A (en) | 1982-10-01 | 1982-10-01 | Semiconductor device and lead frame used for assembling the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57170886A JPS5961950A (en) | 1982-10-01 | 1982-10-01 | Semiconductor device and lead frame used for assembling the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5961950A true JPS5961950A (en) | 1984-04-09 |
Family
ID=15913134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57170886A Pending JPS5961950A (en) | 1982-10-01 | 1982-10-01 | Semiconductor device and lead frame used for assembling the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961950A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7589399B2 (en) | 2005-08-26 | 2009-09-15 | Sharp Kabushiki Kaisha | Semiconductor device, lead frame used in the semiconductor device and electronic equipment using the semiconductor device |
-
1982
- 1982-10-01 JP JP57170886A patent/JPS5961950A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7589399B2 (en) | 2005-08-26 | 2009-09-15 | Sharp Kabushiki Kaisha | Semiconductor device, lead frame used in the semiconductor device and electronic equipment using the semiconductor device |
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