JPS5961195A - Method of producing printed circuit board - Google Patents

Method of producing printed circuit board

Info

Publication number
JPS5961195A
JPS5961195A JP17166582A JP17166582A JPS5961195A JP S5961195 A JPS5961195 A JP S5961195A JP 17166582 A JP17166582 A JP 17166582A JP 17166582 A JP17166582 A JP 17166582A JP S5961195 A JPS5961195 A JP S5961195A
Authority
JP
Japan
Prior art keywords
board
information
starting
layout
boards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17166582A
Other languages
Japanese (ja)
Other versions
JPH0142516B2 (en
Inventor
亀井 邦明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP17166582A priority Critical patent/JPS5961195A/en
Publication of JPS5961195A publication Critical patent/JPS5961195A/en
Publication of JPH0142516B2 publication Critical patent/JPH0142516B2/ja
Granted legal-status Critical Current

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  • Making Paper Articles (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明はプリント配線板の製造方法に係り、特に、品種
毎にそれぞれの回路設計情報と必要枚数を力見られた多
品種、少量生産のプリント配線板を合理的に製造するこ
とができるプリント配線板の全自動の製造方法に関する
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing printed wiring boards, and in particular, to rationally manufacture printed wiring boards of various types and in small quantities by carefully considering circuit design information and required number of sheets for each type. The present invention relates to a fully automatic manufacturing method for printed wiring boards that can be manufactured.

従来のプリント配線板の製造方法には、銅箔張積層板を
出発基板とし、不要部分の銅箔をエツチング除去して導
体回路パターンを形成するエツチドフォイル法(サブト
ラクティブ法)、絶縁積層板を出発基板とし、必要な箇
所に化学銅メッキあるいはさらにこの上に電気メッキを
して直接導体回路パターンを形成するアディティブ法な
どがある。
Conventional printed wiring board manufacturing methods include the etched foil method (subtractive method), in which a copper foil-clad laminate is used as a starting substrate and unnecessary copper foil is etched away to form a conductive circuit pattern; There is an additive method in which a starting substrate is used and the required areas are chemically plated with copper or electroplated on top of the substrate to directly form a conductive circuit pattern.

従来のとわらの技術を用いたプリント配線板の製造方法
においては、同−品種毎のプリント配線板の複数枚を大
きな出発基板上に多面に配列して製造した後、この出発
基板から所望の単位プリント配線板を切り出していた。
In the conventional printed wiring board manufacturing method using Towara's technology, a plurality of printed wiring boards of the same type are arranged on multiple sides on a large starting board, and then the desired board is manufactured from this starting board. The unit printed wiring board was cut out.

プリント配線板は多品種、少畢生産の必要性が高いが、
上述のような従来の方法でに、この必要性に対する合理
的な対応は十分とはいい灯く、しかも製造原価も低減ぜ
さるを得す、新しい生産形態の開発に対する要望d、非
常に高いものがある。
Printed wiring boards require high-mix, low-volume production.
Although the conventional methods described above are not sufficient to rationally meet this need, there is a very high demand for the development of a new production form that will also reduce manufacturing costs. There is.

本発明は、以上の点に鑑み、多品種、少量のプリント配
線板を合理的に製造する方法を提供することを目的とす
る。
In view of the above points, it is an object of the present invention to provide a method for rationally manufacturing printed wiring boards of various types and in small quantities.

本発明は、この目的を達するだめに、多品種、少量の単
位プリント配線板の異なる品種の複数枚宛を複数枚の出
発基板のそれぞれの上に、CA D(コンピー−ター・
エイデツド・テザイン)技術により、該出発基板の不要
部分が最小となるように合理的に割利けると共に導体回
路パターンの形成には周知のアディティブ法を用い、製
造工程の合理化もはかるようにしたものである。
In order to achieve this objective, the present invention uses a computer-aided computer (CAD) system to print a plurality of high-mix, low-volume unit printed wiring boards of different types onto each of a plurality of starting boards.
Using additive design technology, the unnecessary parts of the starting board can be rationally allocated to a minimum, and the well-known additive method is used to form the conductor circuit pattern, thereby streamlining the manufacturing process. It is.

以下、本発明を第1図に示すフローチャートを用いて詳
細に説明する。
Hereinafter, the present invention will be explained in detail using the flowchart shown in FIG.

〔■〕  下記の諸情報ばあらかしめ与えられているも
のとする。
[■] It is assumed that the following information has been given.

(a)  製造すべき多品種の矩形単位プリント配線板
(以下、単位配線板と呼ぶ)の品種毎の回路役割情報1
と必要枚数情報2゜ (b)  前記単位配線板の複数枚を多面取りするのに
十分な所定大きさの矩形出発基板の寸法情報3゜ (c)  前記単位プリント配線板の製造工程のうちの
所定工程において、前記出発基板を該工程で使用する作
業台上に所定の配置で固定するために該基板の辺縁部(
例えば、矩形の一辺の両端)の所定位置に設けるべき少
なくとも2個の所定の形の基板固定用スルーポール(例
えは、所定径の丸穴)の位置情報4(この場合、前記作
業台上には前記基板固定用スルーホール位置に対応する
位置に該スルーホール中に挿入可能なビンが設けらオ]
でおり、該スルーホール中に該ビンを挿入し、前記出発
基板を該基板の周辺側から押しつけて該基板を前記作業
台に固定する。々お、前記基板固定用スルーホールは必
らすしも必要ではなく、他の方法で前記11.11発基
板を前記ビンのない作業台に固定してもよい。)。
(a) Circuit role information 1 for each type of rectangular unit printed wiring boards (hereinafter referred to as unit wiring boards) of various types to be manufactured
and information on the required number of sheets 2゜(b) Dimensional information on a rectangular starting board of a predetermined size sufficient to make multiple sheets of the unit wiring board 3゜(c) Among the manufacturing processes of the unit printed wiring board In a predetermined step, a peripheral portion of the starting substrate (
For example, position information 4 of at least two board fixing through poles (for example, round holes with a predetermined diameter) of a predetermined shape to be provided at predetermined positions on the workbench (for example, both ends of one side of a rectangle). A bottle that can be inserted into the through hole is provided at a position corresponding to the position of the through hole for fixing the board]
Then, the bottle is inserted into the through hole, and the starting board is pressed from the peripheral side of the board to fix the board to the workbench. However, the through holes for fixing the board are not necessary, and the 11.11 board may be fixed to the workbench without the bin by other methods. ).

(d)  前記作業台上に固定した前記出発基板を該作
業台の互に直角なX、Y方向への移動と回転移動によっ
て所定の加工位置に正確にもたらすために該基板の辺縁
部の前記基板固定用スルーホール位置と異なる位置(例
えば、該基板の一辺の該基板固定用スルーポールに挾ま
れた位置)に設けるべき少なくとも2個の所定の形の基
板位置合ぜ用マーク(例えば、所定寸法の+マーク)の
位置情 幸K 5 。
(d) In order to accurately bring the starting substrate fixed on the workbench to a predetermined processing position by moving and rotating the workbench in mutually perpendicular X and Y directions, At least two substrate alignment marks (for example, Location information of the + mark of the predetermined dimensions.

〔1目 甘ず、前記諸情報をデータ処理装置に入力して
下記の処理を行なう。
[Eye 1: Please enter the above information into the data processing device and perform the following processing.

(d)  前記品種毎の単位配線板の回路設側情報から
該品種毎の単位配線板の回路パターンと共に所定径の回
路接続用スルーホールの位置を求める。
(d) From the circuit design information of the unit wiring board for each type, the circuit pattern of the unit wiring board for each type and the position of the circuit connection through hole of a predetermined diameter are determined.

″(b)  前記laで設計した前記品種毎の単位配線
板の回路パターン情報から、該品種毎の単位配線板の寸
法を求める。
(b) From the circuit pattern information of the unit wiring board for each type designed in la above, determine the dimensions of the unit wiring board for each type.

(C)  前記I1. bで求めた前記品種毎の単位配
線板の寸法と前記■aで与えた前記品種毎の単位配線板
の必要枚数から、複数枚の前記出発基板のそれぞれの上
に前記複数種、複数枚の単位配線板を混合配置して、し
かも該基板毎の不要部分が最小となるように多面に割付
けると同時に該割付けによって異なる割付けとなった該
基板(以下、異種割付は基板と呼ぶ)毎の同−割利けと
なった該基板(以下、同一割付は基板と呼ぶ)の必要枚
数と該異種割付は基板の組数な求め、さらに該異種割付
は基板の間に加工順位をつける。
(C) Said I1. Based on the dimensions of the unit wiring boards for each type obtained in step b and the required number of unit wiring boards for each type given in a, Unit wiring boards are arranged in a mixed manner, and at the same time they are laid out on multiple sides so that the unnecessary parts of each board are minimized.At the same time, each board (hereinafter, different layout is referred to as a board) has a different layout due to the layout. The required number of substrates with the same allocation (hereinafter, the same allocation will be referred to as substrates) and the different allocation are determined by the number of sets of substrates, and furthermore, the different allocation sets the processing order among the boards.

(d)  前記IJaで求めた前記品種毎の単位配線板
の回路パターン、回路接続用スルーホール位置と前記I
I Cで求めた前記異種割付は基板毎の単位配線板の割
付は結果から、該異種割付は基板毎に該基板上に割付け
だ回路パターン(以下、割付け回路パターンと呼ぶ)と
該割付は回路パターンの所定位置に設けるべき回路接続
用スルーホール(以下、開側は回路接続用スルーホール
と呼ぶ)の位置を求める。
(d) The circuit pattern of the unit wiring board for each type determined by the IJa, the position of the circuit connection through-hole, and the IJa.
The above-mentioned heterogeneous layout obtained by I The position of a circuit connection through hole (hereinafter, the open side will be referred to as a circuit connection through hole) to be provided at a predetermined position of the pattern is determined.

[111)  以上のようにしてテーク処理装置で予め
た諸情報を出力して王妃のような情報記録媒体を作成す
る。
[111] As described above, the take processing device outputs various pieces of information in advance to create an information recording medium like a queen.

(a)  前記1dで与えた前記基板位置合せ用マーク
の位置情報、前記1.18で求めた基板固定用スルーポ
ールの位置情報、前記11Cで求めた異種開側は基板毎
の割伺は回路接続用スルーポールの位置情報を前記11
 Cでっけだ前記異種割付は基板の間の加工順位に従っ
て前記テーク処理装置から出力して、NC穴あけ機制御
用情報記録媒体7を作成する。
(a) The positional information of the board alignment mark given in 1d above, the positional information of the through pole for fixing the board obtained in 1.18 above, and the different open side obtained in 11C above are the circuits for each board. The position information of the through pole for connection is shown in 11 above.
The different layouts made by C are outputted from the take processing device according to the processing order between the substrates, and an information recording medium 7 for controlling the NC drilling machine is created.

(1))  前記1(1で与えた前記基板位置合ぜ用マ
ークの位置情報、前記1.1 dで求めた前記異種開側
は基板毎の開側は回路パターン情報と前記JJ、 Cで
求めた異種割付は基板毎の必要枚数情報を前記+1cで
つけた前記異種基板の間の加工順位に従って前記テーク
処理装置から出力して、割付は回路パターン形成用情報
記録媒体8を作成する。
(1)) The position information of the board alignment mark given in 1 (1) above, the different open side obtained in 1.1 d above, the open side of each board, the circuit pattern information and JJ, C above. The obtained heterogeneous layout is outputted from the take processing device according to the processing order of the different types of substrates with information on the required number of sheets for each board added by +1c, and the layout creates the information recording medium 8 for circuit pattern formation.

(C)  前記IJcで求めた前記異種割付は基板毎の
単位配線板割付は情報と必要枚数情報を前記異種割付は
基板の間の加工順位に従って前記テーク処理装置から出
力して、前記異種割付は基板のそれぞれから該基板に割
付けた複数の単位配線板を切り出すだめのNCカッター
制御用情報記録媒体9を作成する。
(C) The heterogeneous layout obtained by the IJc is outputted from the take processing device according to the processing order between the boards, and the unit wiring board layout information and required number information for each board are outputted. An information recording medium 9 for controlling an NC cutter for cutting out a plurality of unit wiring boards allocated to each board from each board is created.

(d)  前記111 bで作成した前記割付は回路形
成用情報記録媒体8から、COM(コ/ピー−ター・ア
ウトプット・マイクロフィルム技術により前記基板位置
合せ用マーク、前記異種割付は基板毎の割付は回路パタ
ーン、該異種割付は基板毎の必要枚数を示す光学読取り
可能な記号(例えば、光学読取り文字又はバーコード)
のネガ又(dポジ像が前記異種割付は基板の加工順位に
従って、所定の縮写率で縮写されたマイクロフィルム1
0ヲ作成する。
(d) The layout created in step 111b is transferred from the circuit forming information recording medium 8 to the board alignment mark using COM (copy/peater output microfilm technology), and the different layout is created for each board. The layout is a circuit pattern, and the different layout is an optically readable symbol (for example, an optically readable character or barcode) indicating the number of sheets required for each board.
The negative or positive image of the microfilm 1 is reduced at a predetermined reduction ratio according to the processing order of the substrate.
Create 0.

〔I■〕  ついで、前記NC穴あけ機制御用情報記録
媒体7、前記マイクロフィルム10 、前記NCカッタ
ー制御用情報記録媒体9を用いて、以下の順序で前記出
発基板の加工を行なう。
[I■] Next, the starting substrate is processed in the following order using the information recording medium 7 for controlling the NC drilling machine, the microfilm 10, and the information recording medium 9 for controlling the NC cutter.

(a)  前記出発基板11をNC穴あけ機12の作業
台上に所定配置で取付け、前記NC穴あけ機制御用情報
記録媒体90指令により該穴あけ機12を駆動し、該出
発基板11に前記基板位置合せ用マーク13を刻印する
と共に前記基板固定用スルーホール14と前記割付は回
路接続用スルーホール15の穴あけを行なう操作を前記
異種側+1け基板の加工順位に従って該異種割付は基板
毎の必要枚数情報返し、前記基板位置合せ用マーク13
、前記固定用スルーホール14、前記割付は回路接続用
スルーホール(図示せず)を有する出発基板15の必要
枚数(前記異種割付は基板毎の必要枚数×該異種割付は
基板の組数)。
(a) The starting board 11 is mounted in a predetermined arrangement on the workbench of the NC drilling machine 12, and the drilling machine 12 is driven by the command of the information recording medium 90 for controlling the NC drilling machine, and the board is aligned with the starting board 11. At the same time, the through-holes 14 for fixing the board and the through-holes 15 for connecting circuits are engraved according to the processing order of the different side + 1 board. Return the board alignment mark 13
, the fixing through hole 14, and the allocation is the required number of starting boards 15 having circuit connection through holes (not shown) (the different allocation is the required number of boards for each board x the different allocation is the number of sets of boards).

(b)  前記IVdで得た出発基板15の前記基板位
置合せ用マーク13が刻印された面と前記基板の割イマ
1け回路接続用スルーホール内面上に、前記基板位置合
せ用マーク16と前記基板固定用スルーホール14のあ
る辺縁部分を除いて、坏ガ又はポジ型の感光剤を塗布、
乾燥し、表面に感光膜16を有する出発基板17を作成
する。
(b) The board alignment mark 16 and the board alignment mark 16 are placed on the surface of the starting board 15 obtained in IVd on which the board alignment mark 13 is engraved and on the inner surface of the through-hole for circuit connection of the single cutter of the board. Coat or apply a positive type photosensitive agent except for the edge part where the through hole 14 for fixing the board is located.
After drying, a starting substrate 17 having a photoresist film 16 on its surface is prepared.

本発明では、導体回路パターンを形成には、必要個所に
のみ選択的に導体金属を析出させて配線回路を得る、い
わゆるアディティブ法を用いる。
In the present invention, a so-called additive method is used to form a conductive circuit pattern, in which a conductive metal is selectively deposited only at necessary locations to obtain a wiring circuit.

以下に、この回路形成技術の代表例について説明する。Representative examples of this circuit formation technology will be described below.

本発明には、これら以外にも他のM(υの技術を用いる
ことかできる。
In addition to these techniques, other M(υ techniques) can be used in the present invention.

(1)  塩化パラジウムと感光性還元剤(例えは塩化
第1錫)との混合液を絶縁基板上に塗布、乾燥し、と・
れに回路パターンのネガ像を用いて紫外線照射し、回路
パターン部分に還元性を付与してパラジウムを析出させ
、これを触媒核として無電解メッキを行ない、導体回路
パターンを形成する(2)  絶縁基板表面を塩化パラ
ジウムで処理し、この表面に感光性樹脂を塗布し、これ
を回路パターンのポジ像を用いて露光、現像処理するこ
とにより一回路パターン以外の部分にレジスト層を形成
し、その後、露出した塩化パラジウムを還元し、その上
に無電解メッキにより導体回路パターンを形成する。
(1) Apply a mixture of palladium chloride and a photosensitive reducing agent (for example, stannous chloride) onto an insulating substrate, dry it, and...
This is then irradiated with ultraviolet light using a negative image of the circuit pattern to impart reducibility to the circuit pattern area and deposit palladium, which is then used as a catalyst nucleus for electroless plating to form a conductor circuit pattern (2) Insulation The surface of the substrate is treated with palladium chloride, a photosensitive resin is applied to this surface, and this is exposed and developed using a positive image of the circuit pattern to form a resist layer in areas other than the one circuit pattern. , the exposed palladium chloride is reduced, and a conductive circuit pattern is formed thereon by electroless plating.

(ろ) 絶縁基板上に感光性樹脂膜を設け、回路パター
ンのポジ像を用いて露光すると、露光部分に(硬化し、
未露光部分は未硬化で残る。この回路パターンに対応す
る未硬化部分の粘着性を利用してこの部分に金属粉末を
固着させた後、全面露光(−で未硬化樹脂を硬化させた
上、金属粉末上に無電解メッキを行ない、導体回路パタ
ーンを形成する。以上の方法においては、無電解メッキ
膜上にさらに電気メッキを施こすこともてきる。
(b) When a photosensitive resin film is provided on an insulating substrate and exposed to light using a positive image of a circuit pattern, the exposed area (hardens,
Unexposed areas remain uncured. After fixing the metal powder to this part using the adhesiveness of the uncured part corresponding to this circuit pattern, the uncured resin is cured by full exposure (-), and then electroless plating is performed on the metal powder. , a conductor circuit pattern is formed.In the above method, electroplating can be further performed on the electroless plating film.

以下の工程は前記(6)の方法によって説明する。The following steps will be explained using the method (6) above.

(C)  前記IVbで得だ前記感光性樹脂膜16を有
する出発基板17を露光機18の前記基板固定用ピノを
もった作業台上に、該ピンを前記基板固定用スルーホー
ル14に挿入した上肢基板17を所定の一辺側から押す
ことによって固定し、前記基板17の固定用スルーホー
ル16と位置合せ用マーク14のある部分を除いて、前
記感光性樹脂膜16の全体を7ヤノターで覆う。一方、
前記マイクロフィルム10を前記露光機18にセットし
、該露光機18の拡大倍率を該マイクロフィルム10の
縮写率の逆数に設定してフィルム送りを開始する。捷ず
、前記マイクロフィルム10上の前記感光性樹脂膜16
を7ヤノターで覆ったt−i該マイクロフィルム10の
所定駒を送り出して露光し、該マイクロフィルム上の基
板位置合せ用マークを前記出発基板17上に投影し、前
記露光機18の作業台を移動させて、前記マイクロフィ
ルム10上の基板位置合せ用マークの投影像と前記作業
台」二の前記出発基板の位置合せ用マークとを目視によ
り一致させた後、前記ンヤノターを移動させて前記感光
樹脂膜上に前記マイクロフィルム上の側倒は回路パター
ンのポジ像を投影し、露光部分を硬化させ、未露光の該
割付は回路パターン部分を未硬化の潜像19(斜線部で
示した)として残した出発基板20を作成する。その後
、前記露光処理をした出発基板20を露光機18から取
り出すこのような操作を前記異種割付は基板の加工順位
に従って該異種割付は基板毎の必要枚数宛繰返し表面に
未硬化樹脂からなる割付は回路パターンの潜像をもった
出発基板20の必要枚数を得る。
(C) The starting substrate 17 having the photosensitive resin film 16 obtained in IVb was placed on a workbench having the substrate fixing pin of the exposure machine 18, and the pin was inserted into the substrate fixing through hole 14. The upper limb substrate 17 is fixed by pushing it from one predetermined side, and the entire photosensitive resin film 16 is covered with a 7-layer coating, except for the portions of the substrate 17 where the fixing through holes 16 and the alignment marks 14 are located. . on the other hand,
The microfilm 10 is set in the exposure device 18, the magnification of the exposure device 18 is set to the reciprocal of the reduction ratio of the microfilm 10, and film feeding is started. The photosensitive resin film 16 on the microfilm 10 is not separated.
A predetermined frame of the microfilm 10 covered with a 7-yen tar is sent out and exposed, the substrate alignment mark on the microfilm is projected onto the starting substrate 17, and the workbench of the exposure machine 18 is After moving the microfilm 10 to visually match the projected image of the substrate alignment mark on the microfilm 10 with the alignment mark of the starting substrate on the workbench, the scanner is moved and the photosensitive A positive image of the circuit pattern is projected onto the resin film by the microfilm, and the exposed portion is cured. A starting substrate 20 that is left as is is created. Thereafter, such an operation of taking out the exposed starting substrate 20 from the exposure machine 18 is performed, and the different types of layout is repeated for the required number of substrates for each substrate according to the processing order of the substrates. The required number of starting boards 20 having a latent image of a circuit pattern is obtained.

ついで、前記出発基板20上に銅等の金属粉を散布、圧
着した上で全面を露光し、未硬化の樹脂を硬化させ、未
接着金属粉を除去、回収し、た後、jlill ”Aの
無電5Mメッキを行なえば、前記割付は回路パターンに
対応する所定の割イ」け導電回路パターン21(斜線部
分で示す)をもった必要枚数の出発基板22が得られる
Next, metal powder such as copper is spread and pressed onto the starting substrate 20, and the entire surface is exposed to light to harden the uncured resin. After removing and collecting the unbonded metal powder, If electroless 5M plating is performed, a required number of starting boards 22 having conductive circuit patterns 21 (indicated by diagonal lines) with predetermined divisions corresponding to the circuit patterns can be obtained.

(d)  前記(C)で得た表面に所定の側倒は導電回
路をもった出発基板22を前記NCカッター26 の作
業台上に^(I記基板固定用スルーホール14によって
固定、位置合せをした後、前記NCカッター制御用情報
記録媒体?により前記NCカックー26を駆動し、前記
割付は導体回路ノシター721をもった出発基板22に
割付けた単位配線の外形に対応する矩形の)・−フカノ
ド24を入れ所定外形のノ・−フカノド、240入つだ
出発基板25 の必要枚を所定の加工順位に従って作成
する。
(d) The starting board 22 with the conductive circuit on the surface obtained in (C) is placed on the workbench of the NC cutter 26 (fixed and aligned using the board fixing through-hole 14 in I). After that, the NC cutter 26 is driven by the NC cutter control information recording medium, and the layout is of a rectangle corresponding to the outline of the unit wiring laid out on the starting board 22 having the conductive circuit nositter 721. The necessary number of starting substrates 25 containing 240 pieces of metal molds having a predetermined external shape are prepared in accordance with a predetermined processing order.

最後に、前記ハーフカット24の入った出発基板25を
前記ハーフカット部で折れば、所定品種毎の単位配線板
が必要枚数だけ得られる。
Finally, by folding the starting board 25 containing the half-cut 24 at the half-cut portion, a required number of unit wiring boards of each predetermined type can be obtained.

以上詳述したところから明らかなように、多品種、少量
の単位プリント配線板を受注して製造する場合に、従来
の方法は1品種毎に甘とめて製造するので出発基板に多
くの無駄がてたり、短納期に対して品種毎の製造を効率
的に配分することがむすかしく、納期が長くなりがちで
あり、コスト高となるきらいがあったが、これに対して
本発明は各品種の納期を考慮し々から、多品種のものを
複数枚の出発基板に混ぜ合せて、基板の不要部分が最小
とかるように側倒けて同時に製造することができるので
、納期の短縮、コストダウンをはかることができる特徴
がある。
As is clear from the detailed explanation above, when manufacturing printed wiring boards of various types and in small quantities upon receiving orders, the conventional method is lenient and manufactures each type individually, resulting in a lot of wasted starting boards. It has been difficult to efficiently allocate manufacturing for each product type for short delivery times, which tends to lengthen delivery times and increase costs.In contrast, the present invention can Considering the delivery time of the product, it is possible to mix a wide variety of products onto multiple starting boards and simultaneously manufacture them sideways to minimize unnecessary parts of the board, reducing delivery time and costs. It has the feature of being able to measure down.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のフローチャートを示す図である。 図において、 1・・・品種毎の回路設計情報 2・・・品種毎の必要枚数情報 6・・・出発基板の寸法情報 4・・出発基板固定用スルーホール位置情報5・・・出
発基板位置合せ用マーク位置情報6・・・データ処理装
置 7・・NC穴あけ機制御用情報記録媒体8・・・回路パ
ターン形成用情報記録媒体9・・・NCカッター制御用
情報記録媒体10・・・マイクロフィルム 11・・・出発基板    12・・NC穴あけ機16
・・・基板位置合せ用マーク 14・・・基板固定用スルーホール 16・・感光膜     18・・・露光機19・・・
金属粉末による回路パターン潜像のある部分 21・・・導体回路パターンのある部分26・・NCカ
ノター
FIG. 1 is a diagram showing a flowchart of the present invention. In the figure, 1...Circuit design information for each product type 2...Required number of sheets information for each product type 6...Dimension information of the starting board 4...Through hole position information for fixing the starting board 5...Starting board position Alignment mark position information 6...Data processing device 7...NC drilling machine control information recording medium 8...Circuit pattern formation information recording medium 9...NC cutter control information recording medium 10...Microfilm 11... Starting board 12... NC drilling machine 16
... Mark for substrate alignment 14 ... Through hole for fixing the board 16 ... Photoresist film 18 ... Exposure machine 19 ...
Portion 21 with circuit pattern latent image formed by metal powder...Portion 26 with conductor circuit pattern...NC canoter

Claims (1)

【特許請求の範囲】[Claims] 1、  (a)  製造すべき多品種の矩形単位プリン
ト配線板(以下、単位配線板と呼ぶ)の品種毎の回路股
引、情報と必要枚数情報、(b)  前記単位配線板の
複数枚を多面増シするのに十分な所定の犬に固定した該
基板を該作業台の互に直角なX、 Y方向の移動と回転
移動によって所定の加工位置に正確にもたらすために該
基板の辺縁部に設けるべき少々くとも2個の所定の形の
基板位置合せ用マークの位置情報はあらかじめ力えられ
ているものとし、前記諸情報をデータ処理装置に入力し
て、(d)  前記(8)で力゛えた品種毎の部位配線
板の回路段組情報から該品種毎の単位配線板の回路パタ
ーンと共に回路接続用スルーホールの位置を求め(e)
  Ail記(d)で求めた品種毎の単位配線板の回(
C)で力えた基板位置合せ用マークの位置情報、前記(
g)で求めた異種開側は基板毎の開側は回路接続用スル
ーホールの位置情報および前記(f)で求めた異種開側
は基板毎の必要枚数情報を前記([)でつけた異種開側
は基板の間の加工順位に従って前記データ処理装置から
出力してNC穴あけ機制御用情報記録媒体を作成し、(
1)  前記(C)で与えた基板位置合せ用マークの位
置情報、前記(g)で求めた異種開側は基板毎の割イ」
け回路パターン情報および前記(f)で求めた異種開側
は基板毎の必要枚数情報を前記(f)でつけた異種開側
は基板の加工順位に従って前記データ処理装置から出力
して割付は回路パターン形成用情報記録媒体を作成し、
(J)  前記(f)で求めた異種割付は基板毎の単位
配線板の割付は情報と該異種開側は基板毎の必要枚数情
報を前記(f)でつけた異種開側は基板の間の加工順位
に従って前記データ処理装置から出力して前記異種開側
は基板のそれぞれから該基板に割イ」けた単位配線板を
切p出すためのNCカッター制御用情報記録媒体を作成
し、さらに、(k)  前記(1)で作成した割付は回
路パターン形成用情報記録媒体から前記基板位置合せ用
マーク、前記異種割付は基板毎の割付は回路パターンお
よび該異種割付は基板毎の必要枚数を示す光学読取り記
号のネガ又はポジ像を所定の縮写率で縮写したマイクロ
フィルムを作成し、ついで、(1)  前記出発基板を
前記NC穴あけ機の作業台上に所定配置で固定し、前記
(1])で作成したNC穴あけ機制御用情報記録媒体に
より該穴あけ機を、駆動し、該基板に前記基板位置合ぜ
用マークを刻印すると共に該基板の割判は回路接続用ス
ルーホールの穴あけを行な5操作を前記異種開側は基板
の加工順位に従って該異種割付は基板毎の必要枚数宛繰
返し、前記基板位置合せ用マークと前記開側は回路接続
用スルーホールを有する必要枚数の出発基板を作成し、
(m)  前記(1)で作成した出発基板の前記基板位
置合せ用マークがある■)上と該基板の割付は回路接続
用スルーホール内面上に該基板位置合せ用マークのある
辺縁部分を除いてネガ又はポジ型の感光膜を設け、(1
))  前記(1η)で得た感光膜をもった出発基板を
互に直角な又、Y方向の移動と回動が可能な露光機の作
業台上に該感光膜側を上にして固定し、該感光膜上をシ
ャッターで覆うと共に該露光機に前記マイクロフィルム
をセットし、該マイクロフィルムの所定像ヲ順次送り出
し、甘ず、該マイクロフィルム上の前記基板位置合せ用
マークの投影像と前記出発基板上の基板位置合せ用マー
クを前記作業台の移動により一致させた後、前記シャッ
ターを移動させて前記感光膜を前記マイクロフィルム上
の割付は回路パターンのネガ又はポジ像で露光し、以後
は周知のアディティブ法により前記出発基板上に所定の
割判は導体回路パターンを形成する操作を前記異種割付
は基板の加工順位に従って該異種開側は基板毎の必要枚
数宛繰返し、表面に所定の割付は導体回路パターンを有
する所定枚数の出発基板を作成し、(0)  前記(n
)で得た割付は導体回路ノζターンをもった出発基板を
前記NCカッターの作業台上に所定配置で固定し、前記
NCカッター制御用情報記録媒体により該NCカッター
を駆動し前記割付は導体回路パターンをもった出発基板
に該基板に割付けた単位配線板の外形に対応する矩形の
ノ・−フカノドを入れる操作を前記異種割付は基板の加
工順位に従って前記異種割付は基板毎の必要枚数宛繰返
すことを特徴とするプリント配線板の製造方法。
1. (a) Circuit division, information and required number information for each type of multi-product rectangular unit printed wiring board (hereinafter referred to as unit wiring board) to be manufactured, (b) Multi-faceted wiring of multiple units of the unit wiring board In order to accurately bring the fixed substrate to a predetermined position sufficient to increase the processing speed by moving the workbench in mutually perpendicular X and Y directions and rotationally moving the edge of the substrate to a predetermined processing position, It is assumed that the positional information of at least two predetermined shapes of substrate alignment marks to be provided in the above is stored in advance, and the various information is inputted into the data processing device, and (d) the above (8) is performed. From the circuit stage information of the unit wiring board for each product type obtained in step 2, determine the circuit pattern of the unit wiring board for each product type as well as the position of the through hole for circuit connection (e)
The unit wiring board times for each product type obtained in Ail (d) (
The position information of the board alignment mark obtained in step C), the above (
The open side of the different type obtained in g) is the open side of each board with the position information of the through hole for circuit connection, and the open side of the different type obtained in above (f) is the information of the required number of sheets for each board. The open side is outputted from the data processing device according to the processing order between the substrates to create an information recording medium for controlling the NC drilling machine.
1) The position information of the board alignment mark given in (C) above, and the different open side obtained in (g) above are divided for each board.
The circuit pattern information and the required number of sheets for each board for the different types of open sides obtained in (f) above are output from the data processing device according to the processing order of the boards, and the layout is determined by the circuits. Create an information recording medium for pattern formation,
(J) The heterogeneous layout obtained in (f) above is the information on the layout of unit wiring boards for each board, and the information on the required number of boards for each board on the heterogeneous open side obtained in (f) above. producing an information recording medium for controlling an NC cutter for outputting from the data processing device according to the processing order, and cutting out a unit wiring board from each of the substrates on the different open side; (k) The layout created in (1) above indicates the board alignment mark from the information recording medium for circuit pattern formation, the different type layout indicates the layout for each board, the circuit pattern, and the different type layout indicates the required number of sheets for each board. A microfilm is created by reducing the negative or positive image of the optical read symbol at a predetermined reduction ratio, and then (1) fixing the starting substrate in a predetermined position on the workbench of the NC drilling machine, and performing the steps described in (1) above. ) The drilling machine is driven by the information recording medium for controlling the NC drilling machine, which stamps the board positioning mark on the board, and also drills through-holes for circuit connection in the board. 5. Repeat this operation for the required number of boards for each board according to the processing order of the boards on the open side of the different types, and create the required number of starting boards having the board alignment marks and the through holes for circuit connection on the open side. death,
(m) The board alignment marks on the starting board created in (1) above (■) and the layout of the board are as follows: A negative or positive photoresist film is provided except for (1
)) The starting substrate with the photoresist film obtained in (1η) above was fixed with the photoresist film side up on the workbench of an exposure machine that can be moved and rotated at right angles to each other and in the Y direction. , the photoresist film is covered with a shutter, the microfilm is set in the exposure machine, and predetermined images of the microfilm are sequentially sent out, and the projected image of the substrate alignment mark on the microfilm and the After aligning the substrate alignment marks on the starting substrate by moving the workbench, the shutter is moved to expose the photoresist film with a negative or positive image of the circuit pattern on the microfilm; The operation of forming a conductor circuit pattern of a predetermined size on the starting board by a well-known additive method is repeated for the required number of sheets of the different type open side for each board according to the processing order of the board. For the layout, a predetermined number of starting boards having conductor circuit patterns are created, and (0) the above (n
) The starting board with conductor circuit ζ turns is fixed in a predetermined arrangement on the workbench of the NC cutter, and the NC cutter is driven by the information recording medium for controlling the NC cutter. The operation of inserting rectangular holes corresponding to the outline of the unit wiring boards allocated to the starting board with the circuit pattern is performed according to the processing order of the board. A method for manufacturing a printed wiring board characterized by repeated steps.
JP17166582A 1982-09-30 1982-09-30 Method of producing printed circuit board Granted JPS5961195A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17166582A JPS5961195A (en) 1982-09-30 1982-09-30 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17166582A JPS5961195A (en) 1982-09-30 1982-09-30 Method of producing printed circuit board

Publications (2)

Publication Number Publication Date
JPS5961195A true JPS5961195A (en) 1984-04-07
JPH0142516B2 JPH0142516B2 (en) 1989-09-13

Family

ID=15927426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17166582A Granted JPS5961195A (en) 1982-09-30 1982-09-30 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS5961195A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6093436A (en) * 1983-10-28 1985-05-25 Hitachi Tobu Semiconductor Ltd Designing and plotting device for wiring board to be packaged with electronic parts

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48110656U (en) * 1972-03-24 1973-12-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48110656U (en) * 1972-03-24 1973-12-19

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6093436A (en) * 1983-10-28 1985-05-25 Hitachi Tobu Semiconductor Ltd Designing and plotting device for wiring board to be packaged with electronic parts
JPH058417B2 (en) * 1983-10-28 1993-02-02 Hitachi Tobu Semiconductor Ltd

Also Published As

Publication number Publication date
JPH0142516B2 (en) 1989-09-13

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