JPS5961033A - Formation of a high melting point metal silicide layer - Google Patents

Abstract

PURPOSE:To facilitate formation of silicide wiring and compensation of it by injecting a high melting point metal with the ion implantation into the impurity doped polycrystalline silicon layer and by annealing such polycrystalline silicon layer. CONSTITUTION:A polycrystalline silicon layer is formed by the CVD method. Impurity is doped to a polycrystalline silicon layer by diffusing an impurity source. A high melting point metal (Mo, W, etc.) M<+> is injected to the polycrystalline silicon layer by ion implantation. Concentration of high melting point metal of a formed high melting point metal silicide film is lowered at the surface and interface. A high melting point silicide film formed is annealed at a high temperature, a grain size of crystal becomes large and resistance is lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to a method for forming wiring in a semiconductor device.
More specifically, the present invention relates to a method of forming a wiring layer made of a silicide of a high melting point metal (hereinafter referred to as silicide).

(2) Background of the Technology It is well known that metals such as aluminum (CAt) have been widely used for wiring in semiconductor devices. However, since the A/- wiring has a low melting point of its material,
It has the disadvantage that it can only be formed after all high temperature treatment steps have been completed. Therefore, many polycrystalline silicon layers are currently used as interconnects when forming multilayer interconnect structures. Layers of polycrystalline silicon are usually used in a highly doped form with impurities (phosphorous, arsenic, chloride, etc.), which, in addition to having a high melting point, has good processability. It has notable advantages such as stability and stability.

(3) Conventional technology and problems polycrystalline silicon wiring f which has many excellent features
C also has one drawback that makes M necessary. That is, the wiring resistance is high. The resistance of polycrystalline silicon wiring is A
It is much higher than that of the t-wire, and therefore causes a delay in access time. Such drawbacks related to wiring resistance have become a problem that must be solved as semiconductor devices become more densely packed.

Molybdenum (Mo) and tungsten (
Attempts have also been made to use single high melting point metals such as Vv'). However, although this wiring has a resistance about two orders of magnitude lower than that of polycrystalline silicon, it has the disadvantage of poor chemical stability. That is, refractory metal wiring, like At wiring, has the drawbacks of being easily contaminated, easily attacked by chemicals, and easily oxidized at high temperatures, and is not compatible with the polycrystalline silicon dirt process. is non-existent.

Recently, silicide films of high-melting metals, such as MoS
A method of using an L2 film or the like instead of a single high-melting point metal is attracting attention. Such a silicide film can sufficiently withstand high-temperature processing, and has a wiring resistance that is about one order of magnitude lower than that of a polycrystalline silicon film. However, such a silicide film also has the disadvantage of being susceptible to contamination, making it unavoidable that additional and complicated processing operations are required for the polycrystalline silicon layer on which the passivation film is formed.

(4) Purpose of the Invention The purpose of the present invention is to focus on the advantages of a polycrystalline silicon wiring layer, to reduce only the resistance of the wiring while taking advantage of the advantages, and to create a method that is similar to the formation of a polycrystalline silicon wiring layer. An object of the present invention is to provide an improved method for forming a wiring layer that can be processed by a method.

(5) Structure of the Invention The unsuccessful applicant has now succeeded in achieving the above-mentioned purpose by simply implanting a high-melting point metal into a conventional polycrystalline silicon film, without making any changes to the polycrystalline silicon substrate process. I discovered that it is possible to achieve. The method of the present invention includes
A method for forming a high melting point metal silicide layer, the method comprising the following steps: forming a polycrystalline silicon layer, doping the polycrystalline silicon layer with an impurity, and implanting ions into the polycrystalline silicon layer doped with the impurity. implanting a high melting point metal; and annealing the polycrystalline silicon layer into which the high melting point metal is implanted.

When carrying out the present invention, Group IV-A of the Periodic Table, Group V-A of the Periodic Table
Refractory metals selected from the metal groups belonging to Groups V and Vl-A can optionally be used for MK implantation of already formed polycrystalline silicon. Specifically, Mo
, W, Ti (titanium).

Ta (tantalum), Nb ('niobium),
Pt (platinum) and the like can be cited as a typical high melting point metal. For such metal implantation, ion implantation can advantageously be utilized, for example applying an implant energy of 100-200 eV and an implantation dose of the order of about 10 ion/Crn.

Silicide formed by implanting high melting point metal is
If the metal is represented by M, MSl2. MSl.

M Sl , MSl3. It can take various forms such as M2813.

An example of an impurity doped into the polycrystalline silicon layer prior to implantation of a high melting point metal is a trivalent element (boron) in the periodic table as a p-type impurity.

gallium, indium, etc.), and pentavalent elements (phosphorus, arsenic, antimony, etc.) as n-type impurities. Preferably, these elements are doped by diffusion from a suitable impurity source, or, if this is not practicable, ionization of the impurities and subsequent doping by ion implantation.

The first step, the formation of a layer of polycrystalline silicon, can be advantageously carried out according to conventional methods, for example by low pressure CVD. - By way of example, it is preferable to grow polycrystalline silicon using N2/(S11i4) gas at a temperature of 625° C. and applying a vacuum of 0.2 Torr to a film thickness of 3000 to 40001. .

The final 7 Neil etching step is performed in an argon atmosphere or a mixed atmosphere of argon and hydrogen.
It can be carried out advantageously by applying a temperature of 100°C. In this case, heating may be carried out using an electric furnace commonly used in this technical field, or, if necessary, heating may be carried out using a laser beam and electron beam annealing system [t]. You may do so. The silicide layer is stable at high temperatures.

(6) Embodiment of the Invention Next, a preferred example of the method of the present invention will be explained with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an example of a semiconductor device having a 2/il A silicon one transistor one capacitor structure obtained by applying the method of the present invention. In this figure, l is a p-type silicon substrate, 2 is a field insulating film made of SiO2, 3 is a first polycrystalline silicon layer, 4 is a second polycrystalline silicon layer, and 5 is 5I02 of the first polycrystalline silicon layer 3.
A thin film, 6 is a 5102 thin film separating the first and second polycrystalline silicon layers 3 and 4, 7 is a PSG interlayer insulating film, 8 is N
+diffusion layer, and 9 is an At layer.

Here, the second polycrystalline silicon layer 4, the SiO2 film 6 and the substrate 1 form a transistor (MO8), while the first polycrystalline silicon layer 3, SiO2? %j film 5 and substrate 1 form a capacitor, and these MOS transistors and capacitors are combined to form l memory cell. This is a so-called one-transistor type memory cell. In addition,
The second polycrystalline silicon layer 4 acts as a word line, and the At
Layer 9 acts as a bit line.

The present invention is applied to the formation of the gate of the second polycrystalline silicon layer 4 and the word line. That is, after growing a polycrystalline silicon layer, it is doped with impurities such as phosphorus, arsenic, etc. in order to reduce its wiring resistance, and then high melting point metals such as Mo, W, etc. are ion-implanted. Drive and finally anneal.

Next, each step in carrying out the invention will be explained in order (see Figures 2a, 2b and 2c).

First, a polycrystalline silicon layer is formed in the process shown in FIG. 2a. This can be done, for example, by applying the low pressure CVD method as described above. Subsequently, doping with impurities as shown in FIG. 2b is carried out. For example, if you want to dope phosphorus, for example, poct3. This can be done by providing an impurity source such as pCz3 and performing the diffusion at a temperature of 1050-1100°C. Of course, ion implantation can be used instead of diffusion.

After the impurity doping is completed to the desired level, implantation of a high melting point metal such as Mo, Wo, etc. is performed. This is MoF6. It can be performed by ion implantation using a source such as wF6 at an energy of 100-200 eV and a dose of 1016. The silicide film formed in this manner has a characteristic that the concentration of the high melting point metal contained therein is distributed so as to be lower on the surface and the boundary, and is therefore less likely to be oxidized. Note that the high melting point metal to be implanted into the polycrystalline silicon layer after doping with impurities is M in FIG. 2c.
Indicated by +. Subsequently, although not shown, the formed silicide film is annealed or oxidized at high temperature. As a result, the crystal grain size of the silicide film increases and its resistance decreases.

Furthermore, the method of the present invention allows ion implantation to be performed through the oxide film (SiO2) even after polycrystalline silicon has been oxidized. In this method, since there is a KSIO2 film on the surface, it is easy to process MO and W films that are easily oxidized, and M and W are not oxidized even during the subsequent growth of PSG (at 400 to 450° C.).

(7) Effects of the Invention According to the present invention, a silicide interconnect that exhibits good workability and stability, which are characteristics of polycrystalline silicon interconnects, can be formed very easily. Of course, the wiring to be formed is about 1% higher than polycrystalline silicon, which is a percentage of silicide.
It has an order of magnitude lower resistance. Further, according to the present invention, since the concentration of the high melting point metal is lowered at the surface, the silicide film is less likely to be oxidized, and therefore, its processing and correction become easier.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of a semiconductor device obtained according to the present invention, and FIGS. 2a, 2b, and 2c are cross-sectional views showing the steps of the present invention in order. It is. In the figure, 1 is a substrate, 2 is a field insulating film, 3 is a first polycrystalline silicon layer, 4 is a second polycrystalline silicon layer, 5 and 6 are SiO2 thin films, 7 is a PSG interlayer insulating film, and 8 is an N+ diffusion layer. , and 9 is an At layer. Patent Attorney Fujitsu Limited Patent Attorney Akira Aoki Kazuyuki Nishidate Patent Attorney 1) Yukio Patent Attorney Akira Yamaguchi

Claims (1)

[Claims] 1. A method for forming a high melting point metal silicide layer,
The following steps include forming a polycrystalline silicon layer, doping the polycrystalline silicon layer with an impurity, implanting a refractory metal into the impurity-doped polycrystalline silicon layer by ion implantation, and adding the refractory metal to the polycrystalline silicon layer. A method of forming a refractory metal silicide layer, comprising: annealing a polycrystalline silicon layer implanted with.