JPS5961033A - Formation of a high melting point metal silicide layer - Google Patents
Formation of a high melting point metal silicide layerInfo
- Publication number
- JPS5961033A JPS5961033A JP16953582A JP16953582A JPS5961033A JP S5961033 A JPS5961033 A JP S5961033A JP 16953582 A JP16953582 A JP 16953582A JP 16953582 A JP16953582 A JP 16953582A JP S5961033 A JPS5961033 A JP S5961033A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- melting point
- high melting
- silicon layer
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 26
- 239000002184 metal Substances 0.000 title claims abstract description 26
- 238000002844 melting Methods 0.000 title claims abstract description 25
- 230000008018 melting Effects 0.000 title claims abstract description 22
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 title abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 20
- 239000003870 refractory metal Substances 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 abstract description 4
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 33
- 239000010408 film Substances 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 101100238652 Drosophila melanogaster msl-2 gene Proteins 0.000 description 1
- 102100037715 E3 ubiquitin-protein ligase MSL2 Human genes 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910015255 MoF6 Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 101100408061 Mycobacterium tuberculosis (strain CDC 1551 / Oshkosh) pks2 gene Proteins 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- RLCOZMCCEKDUPY-UHFFFAOYSA-H molybdenum hexafluoride Chemical compound F[Mo](F)(F)(F)(F)F RLCOZMCCEKDUPY-UHFFFAOYSA-H 0.000 description 1
- 101150107890 msl-3 gene Proteins 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は、半導体装置における配線の形成方法に関し、
さらに詳しく述べると、高融点金属の珪化物（以下、シ
リサイドと記す）からなる配線層を形成する方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to a method for forming wiring in a semiconductor device.
More specifically, the present invention relates to a method of forming a wiring layer made of a silicide of a high melting point metal (hereinafter referred to as silicide).
（２）技術の背景
半導体装置の配線として今までアルミニウムＣＡｔ）等
の金属が多用されてきたことは周知の通シである。しか
しながら、Ａ／−配線は、その材料の融点が低いため、
高温処理工程がすべて完了した後でなければ形成するこ
とができないという欠点を有していた。したがって、現
在、多層配線構造を形成する場合など、多結晶シリコン
の層が多く配線として用いられている。多結晶シリコン
の層は、通常、高濃度に不純物（リン、ヒ素、？ロンな
ど）をドープした形で用いられているけれども、これは
、高融点であることに加えて、加工性が良好である、安
定性がある、等の注目すべき利点を有している。(2) Background of the Technology It is well known that metals such as aluminum (CAt) have been widely used for wiring in semiconductor devices. However, since the A/- wiring has a low melting point of its material,
It has the disadvantage that it can only be formed after all high temperature treatment steps have been completed. Therefore, many polycrystalline silicon layers are currently used as interconnects when forming multilayer interconnect structures. Layers of polycrystalline silicon are usually used in a highly doped form with impurities (phosphorous, arsenic, chloride, etc.), which, in addition to having a high melting point, has good processability. It has notable advantages such as stability and stability.
（３）従来技術と問題点
多くのすぐれた特徴を有している多結晶シリコン配線ｆ
ＣもＭ要な欠点が１つある。すなわち、配線抵抗が大き
いことがそれである。多結晶シリコン配線の抵抗は、Ａ
ｔ配線のそれに比してはるかに高く、シたがって、アク
セスタイムの遅延を生じる。このような配線抵抗に係る
欠点は、半導体装置の高密度化が進むにつれて、ぜひと
も解消しなければならない問題となっている。(3) Conventional technology and problems polycrystalline silicon wiring f which has many excellent features
C also has one drawback that makes M necessary. That is, the wiring resistance is high. The resistance of polycrystalline silicon wiring is A
It is much higher than that of the t-wire, and therefore causes a delay in access time. Such drawbacks related to wiring resistance have become a problem that must be solved as semiconductor devices become more densely packed.
配線材料として、モリブデン（Ｍｏ）やタングステン（
Ｖｖ’ ）などのような高融点金属を単体で使用する試
みもなされている。が、この配線は、多結晶シリコンよ
シも抵抗が約２桁低いというものの、化学的安定性に劣
るという欠点を有している。すなわち、高融点金属配線
は、Ａｔ配線と同様に汚染を受けやすく、化学薬品に侵
されやすく、高温度において酸化されやすいという欠点
を有しておシ、多結晶シリコンダート・プロセスとの互
換性が不存在である。Molybdenum (Mo) and tungsten (
Attempts have also been made to use single high melting point metals such as Vv'). However, although this wiring has a resistance about two orders of magnitude lower than that of polycrystalline silicon, it has the disadvantage of poor chemical stability. That is, refractory metal wiring, like At wiring, has the drawbacks of being easily contaminated, easily attacked by chemicals, and easily oxidized at high temperatures, and is not compatible with the polycrystalline silicon dirt process. is non-existent.
最近は、高融な金属のシリサイド膜、例えばＭｏ Ｓ
ｌ ２膜などを高融点金属単体に代えて用いる方法が注
目されている。かかるシリサイド膜は、高温処理にも十
分に耐えることができ、しかも多結晶シリコン膜に較べ
て約１桁低い配線抵抗を有している。但し、このような
シリサイド膜も汚染に弱いという欠点を有しておシ、パ
シベーション膜を形成したシ多結晶シリコン層をひいた
シの付加的なかつ煩雑な処理作業を不可避としている。Recently, silicide films of high-melting metals, such as MoS
A method of using an L2 film or the like instead of a single high-melting point metal is attracting attention. Such a silicide film can sufficiently withstand high-temperature processing, and has a wiring resistance that is about one order of magnitude lower than that of a polycrystalline silicon film. However, such a silicide film also has the disadvantage of being susceptible to contamination, making it unavoidable that additional and complicated processing operations are required for the polycrystalline silicon layer on which the passivation film is formed.
（４）発明の目的
本発明の目的は、多結晶シリコン配線層の有する良さ圧
着目し、その良さを生かしつつ配線の抵抗だけを下ける
ことができかつ多結晶シリコン配線層の形成に準じた方
法によって処理を行なうことができる改良された配線層
形成方法を提供することにある。(4) Purpose of the Invention The purpose of the present invention is to focus on the advantages of a polycrystalline silicon wiring layer, to reduce only the resistance of the wiring while taking advantage of the advantages, and to create a method that is similar to the formation of a polycrystalline silicon wiring layer. An object of the present invention is to provide an improved method for forming a wiring layer that can be processed by a method.
（５）発明の構成
不発切者は、このたび、多結晶シリコンヶ゛−ト・プロ
セスを殆んど変更しないで、すなわち、従来の多結晶シ
リコン膜に高融点金属を打ち込むだけで、上記した目的
を達成し得るということを見い出した。本発明方法は、
高融点金属シリサイド層を形成する方法であって、下記
の工程：多結晶シリコン層を形成すること、
該多結晶シリコン層に不純物をドープすること、該不純
物をドーグした多結晶シリコン層にイオン注入によシ高
融点金属を注入すること、及び高融点金属が注入された
多結晶シリコン層をアニールすること、
を含んでなることを’ｌとしている。(5) Structure of the Invention The unsuccessful applicant has now succeeded in achieving the above-mentioned purpose by simply implanting a high-melting point metal into a conventional polycrystalline silicon film, without making any changes to the polycrystalline silicon substrate process. I discovered that it is possible to achieve. The method of the present invention includes
A method for forming a high melting point metal silicide layer, the method comprising the following steps: forming a polycrystalline silicon layer, doping the polycrystalline silicon layer with an impurity, and implanting ions into the polycrystalline silicon layer doped with the impurity. implanting a high melting point metal; and annealing the polycrystalline silicon layer into which the high melting point metal is implanted.
本発明を実施する場合、周期律表ＩＶ−Ａ族、第Ｖ−Ａ
族及び第Ｖｌ−Ａ族に属する金属グループから選ばれた
高融点金属を任意に使用して既に形成しである多結晶シ
リインのＭＫ打ち込むことかできる。具体的には、Ｍｏ
、Ｗ、Ｔｉ（チタン）。When carrying out the present invention, Group IV-A of the Periodic Table, Group V-A of the Periodic Table
Refractory metals selected from the metal groups belonging to Groups V and Vl-A can optionally be used for MK implantation of already formed polycrystalline silicon. Specifically, Mo
, W, Ti (titanium).
Ｔａ （タンタル） 、 Ｎｂ （’ニオブ） 、
Ｐｔ （白金）などを代表的な高融点金属としてあげる
ことができる。このよう々金属の打ち込みには、好寸し
くは、イオン注入を、例えば１００〜２００ｅＶの注入
エネルギー及び約１０ イオン／Ｃｒｎ のオー
ダーの注スト〜ズを適用して、利用することができる。Ta (tantalum), Nb ('niobium),
Pt (platinum) and the like can be cited as a typical high melting point metal. For such metal implantation, ion implantation can advantageously be utilized, for example applying an implant energy of 100-200 eV and an implantation dose of the order of about 10 ion/Crn.
高融点金属の打ち込みによシ形成されるシリサイドは、
その金属をＭで表わした場合、ＭＳｌ２．ＭＳｌ。Silicide formed by implanting high melting point metal is
If the metal is represented by M, MSl2. MSl.
Ｍ Ｓｌ 、 ＭＳｌ３． Ｍ２８１３等のいろいろな
形輻をとることができる。M Sl , MSl3. It can take various forms such as M2813.
高融点金属の打ち込みに先がけて多結晶シリコンの層に
ドープする不純物として、例えば、ｐ形不純物としての
周期律表で３価の元素（ボロン。An example of an impurity doped into the polycrystalline silicon layer prior to implantation of a high melting point metal is a trivalent element (boron) in the periodic table as a p-type impurity.
ガリウム、インジウムなど）、そしてｎ形不純物トシて
の５価の元素（リン、ヒ素、アンチモンなど）をあげる
ことができる。これらの元素を適当な不純物源から拡散
によりドープするか、もしくは、それが実施できない場
合、不純物のイオン化を行なって後にイオン注入によシ
ドープするのが好ましい。gallium, indium, etc.), and pentavalent elements (phosphorus, arsenic, antimony, etc.) as n-type impurities. Preferably, these elements are doped by diffusion from a suitable impurity source, or, if this is not practicable, ionization of the impurities and subsequent doping by ion implantation.
最初の工程である多結晶シリコンの層の形成は、常法に
従って、例えば減圧ＣＶＤ法により有利に実施すること
ができる。−例を示すと、ン２／（Ｓ１１ｉ４）ガスを
使用して６２５℃の温度及び０．２トルの減圧を適用し
て膜厚が３０００〜４０００１となるまで多結晶シリコ
ンを成長させるのが好ましい。The first step, the formation of a layer of polycrystalline silicon, can be advantageously carried out according to conventional methods, for example by low pressure CVD. - By way of example, it is preferable to grow polycrystalline silicon using N2/(S11i4) gas at a temperature of 625° C. and applying a vacuum of 0.2 Torr to a film thickness of 3000 to 40001. .
最後の７ニールエ程であるが、これは、アルゴン雰囲気
中又はアルゴン及び水素の混合雰囲気中で１０５０〜１
１００℃の温度を適用して有利に実施することができる
。その際、この技術分野において普通に用いられている
電気炉を使用して加熱を行なってもよく、さもなければ
、必要に応じて、レーザビーム及び電子ビームアニール
装［ｔ［用して加熱を行なってもよい。シリサイド層は
高温下に安定である。The final 7 Neil etching step is performed in an argon atmosphere or a mixed atmosphere of argon and hydrogen.
It can be carried out advantageously by applying a temperature of 100°C. In this case, heating may be carried out using an electric furnace commonly used in this technical field, or, if necessary, heating may be carried out using a laser beam and electron beam annealing system [t]. You may do so. The silicide layer is stable at high temperatures.
（６）発明の実施例
次に、添付の図面を参照しながら本発明方法の好ましい
一例を説明する。(6) Embodiment of the Invention Next, a preferred example of the method of the present invention will be explained with reference to the accompanying drawings.
第１図は、本発明方法を適用して得られる、２／ｉｌ結
Ａシリコン１トランジスタ１キヤパシタ構造を有する半
導体装置の一例を示した断面図である。この図において
、ｌはｐ形シリコン基板、２はＳｉＯ２からなるフィー
ルド絶縁膜、３は第１多結晶シリコン層、４は第２多結
晶シリコン層、５は第１多結晶シリコン層３の５Ｉ０２
薄膜、６は第１及び第２の多結晶シリコン層３及び４を
分離する５１０２薄膜、７はＰＳＧ層間絶縁膜、８はＮ
＋拡散層、そして９はＡｔ層である。FIG. 1 is a sectional view showing an example of a semiconductor device having a 2/il A silicon one transistor one capacitor structure obtained by applying the method of the present invention. In this figure, l is a p-type silicon substrate, 2 is a field insulating film made of SiO2, 3 is a first polycrystalline silicon layer, 4 is a second polycrystalline silicon layer, and 5 is 5I02 of the first polycrystalline silicon layer 3.
A thin film, 6 is a 5102 thin film separating the first and second polycrystalline silicon layers 3 and 4, 7 is a PSG interlayer insulating film, 8 is N
+diffusion layer, and 9 is an At layer.
ここで、第２多結晶シリコン層４．５１０２池膜６及び
基板１はＭＯ８）ランジスタを形成し、一方、第１多結
晶シリコン層３、ＳｉＯ２？％ｊ膜５及び基板１はキャ
パシタを形成し、これらＭＯＳトランジスタとキャパシ
タとが組み合わされてｌメモリセルを形成する。これが
、いわゆる１トランジスタ型メモリセルである。なお、
第２多結晶シリコン層４はワード線として作用し、Ａｔ
層９はビット線として作用するものである。Here, the second polycrystalline silicon layer 4, the SiO2 film 6 and the substrate 1 form a transistor (MO8), while the first polycrystalline silicon layer 3, SiO2? %j film 5 and substrate 1 form a capacitor, and these MOS transistors and capacitors are combined to form l memory cell. This is a so-called one-transistor type memory cell. In addition,
The second polycrystalline silicon layer 4 acts as a word line, and the At
Layer 9 acts as a bit line.
第２多結晶シリコン層４のケ゛−ト及びワード線の形成
に際して本発明を適用する。すなわち、多結晶シリコン
層を成長させた後、その配線抵抗を低下させるために例
えばリン、ヒ素などのような不純物をドープし、その後
、例えばＭｏ、Ｗなどのような高融点金属をイオン注入
により打ち込み、そして最後にアニールする。The present invention is applied to the formation of the gate of the second polycrystalline silicon layer 4 and the word line. That is, after growing a polycrystalline silicon layer, it is doped with impurities such as phosphorus, arsenic, etc. in order to reduce its wiring resistance, and then high melting point metals such as Mo, W, etc. are ion-implanted. Drive and finally anneal.
次いで、本発明を実施する際の各工程を順を追って説明
しよう（第２ａ図、第２ｂ図及び第２ｃ図を参照された
い）。Next, each step in carrying out the invention will be explained in order (see Figures 2a, 2b and 2c).
先ず、第２ａ図に図示の工程で多結晶シリコン層を形成
する。これは、先にも述べたよう例、減圧ＣＶＤ法を適
用して行なうことができる。引き続いて、第２ｂ図に図
示の不純物のドープを実施する。例／ｌば、リンをドー
プしようと思う場合、例えばｐｏｃｔ３． ｐＣｚ３の
ような不純物源を用意して１０５０〜１１００℃の温度
で拡散を行なうことによυこれを実施することができる
。もちろん、拡散に代えてイオン注入を利用することも
できる。First, a polycrystalline silicon layer is formed in the process shown in FIG. 2a. This can be done, for example, by applying the low pressure CVD method as described above. Subsequently, doping with impurities as shown in FIG. 2b is carried out. For example, if you want to dope phosphorus, for example, poct3. This can be done by providing an impurity source such as pCz3 and performing the diffusion at a temperature of 1050-1100°C. Of course, ion implantation can be used instead of diffusion.
不純物のドープが所望のレベルまで完了した後、例えば
Ｍｏ 、 Ｗｏなどのような高融点金属の打ち込みを
行なう。これは、ＭｏＦ６． ｗＦ６などのようなソー
スを使用して、１００〜２００ ｅＶのエネルギー及び
１０１６のドーズでイオン注入により実施することがで
きる。このようにして形成されるシリサイド膜において
、それに含まれる高融点金属の濃度は表面及び境界が低
くなるように分布しておシ、よって酸化されにくいとい
う特徴がある。なお、不純物ドープ後の多結晶シリコン
層に打ち込まれるべき高融点金属は第２ｃ図においてＭ
＋で示されている。引き続いて、図示されていないけれ
ども、形成されたシリサイド膜を高温度でアニール又は
酸化する。すると、シリサイド膜の結晶粒径が大きくな
り、その抵抗が低下する。After the impurity doping is completed to the desired level, implantation of a high melting point metal such as Mo, Wo, etc. is performed. This is MoF6. It can be performed by ion implantation using a source such as wF6 at an energy of 100-200 eV and a dose of 1016. The silicide film formed in this manner has a characteristic that the concentration of the high melting point metal contained therein is distributed so as to be lower on the surface and the boundary, and is therefore less likely to be oxidized. Note that the high melting point metal to be implanted into the polycrystalline silicon layer after doping with impurities is M in FIG. 2c.
Indicated by +. Subsequently, although not shown, the formed silicide film is annealed or oxidized at high temperature. As a result, the crystal grain size of the silicide film increases and its resistance decreases.
さらに、本発明方法は、多結晶シリコンの酸化後でもそ
の酸化膜（ＳｉＯ２）を通してイオン注入を行なうこと
ができる。この方法では、表面ＫＳＩＯ２膜があるので
、酸化され＋すいＭＯやＷの膜の処理が容易になシ、引
き続（ＰＳＧの成長（４００〜４５０℃）時にもＭ、や
Ｗが酸化されない。Furthermore, the method of the present invention allows ion implantation to be performed through the oxide film (SiO2) even after polycrystalline silicon has been oxidized. In this method, since there is a KSIO2 film on the surface, it is easy to process MO and W films that are easily oxidized, and M and W are not oxidized even during the subsequent growth of PSG (at 400 to 450° C.).
（７）発明の効果
本発明に従うと、多結晶シリコン配線の特徴である良好
な加工性及び安定性を生がしたシリサイド配線を非常に
簡単に形成することができる。形成される配線は、もち
ろん、シリサイドの％徴である多結晶シリコンよシ約１
桁低い抵抗を有している。さらに、本発明に従うと、高
融点金属の濃度が表面で低くなるのでシリサイド膜が酸
化されにくくなシ、よって、その処理とが補正とが容易
になる。(7) Effects of the Invention According to the present invention, a silicide interconnect that exhibits good workability and stability, which are characteristics of polycrystalline silicon interconnects, can be formed very easily. Of course, the wiring to be formed is about 1% higher than polycrystalline silicon, which is a percentage of silicide.
It has an order of magnitude lower resistance. Further, according to the present invention, since the concentration of the high melting point metal is lowered at the surface, the silicide film is less likely to be oxidized, and therefore, its processing and correction become easier.
第１図は、本発明によシ得られる半導体装置の一例を示
した断面図、そして
第２ａ図、第２ｂ図及び第２ｃ図は、それぞれ、本発明
の工程を順を追って示した断面図である。
図中、１は基板、２はフィールド絶縁膜、３は第１多結
晶シリコン層、４は第２多結晶シリコン層、５及び６は
ＳｉＯ２薄膜、７はＰＳＧ層間絶縁膜、８はＮ＋拡散層
、そして９はＡｔ層である。
髄許出願人
富士通株式会社
特許出願代理人
弁理士 青 木 朗
弁理士 西 舘 和 之
弁理士 内 １）幸 男
弁理士 山 口 昭 之FIG. 1 is a cross-sectional view showing an example of a semiconductor device obtained according to the present invention, and FIGS. 2a, 2b, and 2c are cross-sectional views showing the steps of the present invention in order. It is. In the figure, 1 is a substrate, 2 is a field insulating film, 3 is a first polycrystalline silicon layer, 4 is a second polycrystalline silicon layer, 5 and 6 are SiO2 thin films, 7 is a PSG interlayer insulating film, and 8 is an N+ diffusion layer. , and 9 is an At layer. Patent Attorney Fujitsu Limited Patent Attorney Akira Aoki Kazuyuki Nishidate Patent Attorney 1) Yukio Patent Attorney Akira Yamaguchi
Claims (1)
下記の工程゛ 多結晶シリコン層を形成すること、 該多結晶シリコン層に不純物をドープすること、該不純
物をドープした多結晶シリコン層にイオン注入により高
融点金属を注入すること、及び高融点金属が注入された
多結晶シリコン層をアニールすること、 を含んでなることを特徴とする高融点金属シリサイド層
の形成方法。[Claims] 1. A method for forming a high melting point metal silicide layer,
The following steps include forming a polycrystalline silicon layer, doping the polycrystalline silicon layer with an impurity, implanting a refractory metal into the impurity-doped polycrystalline silicon layer by ion implantation, and adding the refractory metal to the polycrystalline silicon layer. A method of forming a refractory metal silicide layer, comprising: annealing a polycrystalline silicon layer implanted with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16953582A JPS5961033A (en) | 1982-09-30 | 1982-09-30 | Formation of a high melting point metal silicide layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16953582A JPS5961033A (en) | 1982-09-30 | 1982-09-30 | Formation of a high melting point metal silicide layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5961033A true JPS5961033A (en) | 1984-04-07 |
| JPH0377658B2 JPH0377658B2 (en) | 1991-12-11 |
Family
ID=15888290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16953582A Granted JPS5961033A (en) | 1982-09-30 | 1982-09-30 | Formation of a high melting point metal silicide layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961033A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6486560A (en) * | 1987-09-29 | 1989-03-31 | Nippon Telegraph & Telephone | Manufacture of semiconductor device |
| US5420074A (en) * | 1990-07-05 | 1995-05-30 | Kabushiki Kaisha Toshiba | Method for burying low resistance material in a contact hole |
-
1982
- 1982-09-30 JP JP16953582A patent/JPS5961033A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6486560A (en) * | 1987-09-29 | 1989-03-31 | Nippon Telegraph & Telephone | Manufacture of semiconductor device |
| US5420074A (en) * | 1990-07-05 | 1995-05-30 | Kabushiki Kaisha Toshiba | Method for burying low resistance material in a contact hole |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0377658B2 (en) | 1991-12-11 |
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