JPS5960795A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To delete noise out of a cell plate by providing a noise cancelling word line which is driven concurrently with a word line. CONSTITUTION:The inverted signal of a word line WL (m) is supplied to the noise cancelling word line NWL1. This line WL (m) has the voltage of an earth level in a non-selection mode and is at a high level when it is selected. Therefore the line NWL1 is set at a high level when a memory cell is set in a reading or writing state and then set at an earth level when a certain memory cell is selected. As a result, the capacitive coupled noise that is applied to a cell plate CP1 from the line WL (m) through a coupled capacity Cwp is cancelled. Thus the cell plate voltage is kept at a constant level.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to semiconductor memory devices, particularly M[S(MeLaJ
In5ulator Sem1condo
ctor) Regarding Guinamisoku Random Access Memory (d-RAM).

Conventional technology and problems Conventionally, ff51 was used as a memory cell in d-RAM.
What can be seen in the figure is known.

In FIG. 1, ■ is a p-type silicon semiconductor substrate, 2 is a field insulating film made of silicon dioxide, 3 is a gate insulating/storage capacitor dielectric film made of silicon dioxide,
4 is a cell plate which is a first layer of polycrystalline silicon, 5 is an isolation insulating film made of silicon dioxide, 6 is a transfer gate which is a second layer of polycrystalline silicon, and 7 is a bit line (n+). A mold region 8 is a silicon dioxide insulating film, 9 is an aluminum word line, 10 is a storage capacitor, 11
is the warp IS line and the parasitic coupling capacitance between the cell and plate, I2
indicate storage nodes, respectively. Note that the cell plate 4 in this memory cell is connected to the power supply VOO in the case of a 71%-power supply type. In addition, in the illustrated example, the electrode of the storage capacitor 100 on the semiconductor substrate 1 side is formed with a region 12 of the opposite conductivity type to the semiconductor substrate 1, and can be charged to a voltage of the same level as the power supply voltage. There are, but
Many other variations of this type of memory cell are found.

Now, in order to write data into this memory cell, the stored keyed battery IO is charged from the pin type region 7, which is the pin 1- line. In this type of memory cell, the maximum voltage between the terminals of the product capacitor 10 is the same voltage as the power supply voltage,
The minimum value is 0 [V].

By the way, as the number of products in the memory cell array increases, it has become necessary to use a thin dielectric film 3 with low breakdown voltage in the storage capacitor 10, but the above-mentioned However, when charged to the maximum voltage, that is, the same voltage as the power supply voltage, the insulation of the dielectric film 3 is likely to be destroyed.

In such a case, if the voltage applied to the cell planes 1-4 of the memory cells is kept at a level approximately midway between the power supply voltage and the ground voltage, the electric current rE applied to the dielectric film 3 will be at most half the power supply voltage. The possibility of insulation breakdown is extremely low. In this case, the storage node (
Since the voltage is 0 or van, the maximum voltage applied to the dielectric film 3 is Vt, n/2. Become. tjC is a data storage fi! There is no change in tm.

- Generally speaking, it is desirable to use a single power supply from the point of view of the use of semiconductor memory devices.
Voltage 2 must be generated within the integrated circuit. However, this has various problems. The main reason is that the internal resistance of the voltage generating circuit is relatively low. Due to this influence, for some reason, the voltage of cell plate 4 becomes VDn/
When the voltage changes from 2, if a read or write operation is performed on the memory during the transition period until recovery, a so-called hump noise component will be superimposed on the memory output voltage, causing a read error every time. .

As mentioned above, the following phenomenon can be cited as a cause of the change in the voltage of the cell plate 4.

That is, when a voltage is applied to the sort line 9 in order to select a memory cell, the voltage is differentiated through the parasitic coupling capacitance 11 between the word line and the cell plate 1, and the cell
It is applied to plate 4 and raises the potential of the cell plate.

OBJECTS OF THE INVENTION The present invention provides a semiconductor memory 11g device that prevents noise from entering the cell plate even in cases where the internal resistance of the power supply that supplies voltage to the cell plate cannot be ignored. This is to prevent malfunction.In addition,
The power source referred to herein may be located inside or outside the semiconductor memory device.

Structure of the Invention The present invention is characterized in that the word line capacitively coupled to the cell plane 1- has the greatest influence on noise on the cell plane 1-, and that the cell plane 1- is driven in the memory cell array. Focusing on the fact that there is only one word line for lightning, when the word lines are driven, there is always noise and noise that are driven simultaneously.
A major feature is the provision of a cancellation word line.

The noise canceling word line has the same coupling capacitance with the cell plate as the memory cell word line has, and is driven by the inverted signal of the memory cell word line. This cancels the capacitive coupling noise that the word line imparts to the cell plate, keeping the cell plate voltage fairly constant and preventing malfunctions.

Embodiment of the Invention FIG. 2 is an explanatory diagram of main parts for explaining an embodiment of the present invention.

SA, C1) is a sense amplifier and column decoder;
MCA1 and MCA2 (memory cell array, RI)
1. DI is row decoder and driver, R1)2. D
2 is a row decoder and driver, ■EC is Van/2
Voltage generation circuit, CI)1 and CF2 are cell plates,
WL(m) is the word line at address m, D CL l and D
CL 2 is two 1 wire for dummy cell, NWL l and N
WL2 is a word line for noise cancellation, B L I
and BL2 is the pin 1- line, MCI is the memory cell, I)
MG2 represents a dummy cell, Cwp represents a junction capacitance, and van represents a power supply voltage.

As shown in the figure, the memory cell array has a sense amplifier SΔ and a column decoder CD set to medium temperature and one ζM.
It is divided into two parts, CΔ1 and MCA2, and the cell play 1-
CI) l and CI) 2 are supplied with a voltage of VDD/2.

one memory cell in one memory cell array,
For example, in order to select memory cell MCI in memory cell array MC8l[11, select memory cell MCI of memory cell array MC8l[11], for example, address m-1" W
M W I-(m ) is selected by the row decoder RDI. In the external memory cell array MC82, a dummy circuit is connected to the sense amplifier SΔ, which is a solid flop type, and is used to generate an intermediate voltage between “O” and “1” as a reference. Cell DMC2 is automatically selected. To select this dummy cell I) MC2, the dummy cell word line 1) CL2 is driven.

1); As noted in i, when the word line WL, (rrl) is driven, due to the existence of the coupling capacitance @ Cw p between it and the cell play 1- Cl) 1, the cell play 1-
The voltage of CP 1 will be 20%.

In the present invention, in order to deal with this, a noise canceling word line NWL 1 is provided, and the noise canceling word line NWL 1 has a word line WL(m).
It is designed to supply an inverted signal of . Word line WL
(m) is at ground level voltage when not selected,
If selected, it becomes high/bell. Therefore, the noise
The canceling word line NWL1 is at a high level when a memory cell is in a read or write operation state, and is at a ground level when any memory cell is selected. As a result, the capacitive coupling noise that the word line WL (m) applies to the cell plate +-CI)1 through the coupling capacitance Cwp is canceled, and the cell plate voltage is held constant.

Such an operation must be performed similarly for dummy cell DMC2. That is, dummy cell 1
One word line Cl3 for the dummy cell to which MC2 is connected is driven, and at the same time an inverted signal is applied to the manote line NWI-2 for the noise cancer cell.
- Stabilize the voltage of CP2.

Noise/Kinakansel/month 1 saw + line Nw Lt, N
WL 2 etc. have word lines, transfer gates, and transfer i transistors that do not have transfer active areas, but their active areas are electrically separated by δIn from the pin lines and are not connected to the bit lines. It can be easily formed by adding a transfer gate or the like that does not impede operation to the memory cell array.

The signals that drive the noise canceling word lines NWLI, NWL2, etc., i.e., the inverted signals for the word line W1.1 and the dummy cell word line [] Cl12, etc., use the circuit shown in Figure 3. You can take it out every time.

FIG. 3 is an explanatory diagram of the main parts of the i:1-denier I-der and the 1-driver, and the same parts as those explained with reference to FIG. 2 are indicated by the same symbols.

In the figure, AB is an address hash, Cl< is a word line driving clock generator, and PC is an input (41 children) of a pre-charge clock signal.

As is clear from the figure, it is only necessary to take out the combination signal from the sort line driving generator GK and apply it to the sort line NWLI for the noise key cell (NWL, 2 as well). It is easy to introduce the present invention into conventionally manufactured memory cells.

When the present invention is applied to a memory cell array having folded bit lines, this type of memory cell array has essentially less noise due to capacitive coupling between the focus line and the cell plate. In combination with the fact that the present invention reduces the coupling noise from the word line side, it is possible to construct a memory cell array with extremely low noise.In particular, the pre-charge voltage of the pit line can be reduced. Abbreviation VII
When set to D/2, the voltage of one tip line rises by 2 and the voltage of the other falls due to the sense refresh operation, so the capacitive coupling noise that the bis 1-cotton gives to the cell plate 1- is canceled. Cell plate voltage is stabilized. Also, the pin 1-line voltage is abbreviated as ■. When F is increased to about , /2, the memory cell transfer 1 transistor is biased to the triode region at an early stage, and the residual charge of the capacitor is quickly transferred to the bit line, improving the memory access speed. .

In the above explanation, the voltage applied to the cell plate 1- was mainly described in the form that is generated within the integrated circuit, but this is because the internal resistance of the power supply within the integrated circuit tends to be high. This is because the present invention is considered to be particularly effective. However, even when the cell plate voltage is supplied externally, the cell plate voltage is known to fluctuate, albeit slightly, because wiring resistance within the integrated circuit cannot be ignored. Therefore, it goes without saying that it is effective to apply the present invention to such cases. Note that in order to make the wiring resistance negligible, it would be sufficient to form a sufficiently wide wiring, but this would reduce the degree of integration.

Furthermore, although the present invention is most effective for cells where the capacitive coupling between the sort line and the cell plate is relatively large, such as the double polycrystalline silicon type memory cell shown in FIG. In cells such as three-layer polycrystalline silicon cells, the word "cotton" and the cell plate are directly or indirectly capacitively coupled, so it is of course effective for such cells as well. It is.

Effects of the Invention In the semiconductor memory device of the present invention, a memory cell array C is formed by arranging memory cells each consisting of a transfer transistor and a two-F medium passacitor for charge storage having a cell plate to which a predetermined voltage is applied. , a word line for selecting a memory cell in the memory cell array, a word line for a noise-gain cell driven in synchronization with the word line by an inverted signal of the signal driving the word line. When the word line is driven, it is possible to suppress transient voltage changes on the cell plate caused by capacitive coupling between the word line and the cell plate. L
--11' (liII- is stable and does not work once).

Explanation of 11 in the cylinder on page 41 Figure 1 shows the main parts of the memory cell. III side view, FIG. 2 is an explanatory diagram of the main part of one embodiment of the present invention, and FIG.
It is an explanatory view of the main parts of 1 day 1 day and 1 jf near the driver in the figure.

In the figure, SΔ, CD are sense intensifier 'l'+'d, column dego2-e', MCΔ1. MCC20 memory
Serparui, I< I) 1, I) J is the row decoder and driver, R1) 2, 1. ) 2 is a row decoder and 1-lime, IEC is a Voo/2 voltage generation circuit, and C111.

NWLl, NWL2 are noise canceling manot lines, 13 L I, 13 L 2 are bit lines, MCI
is a memory cell, DMC2 is a dummy cell, Cwp
is the coupling capacity, and van is the power supply voltage.

Figure 1 Flute 2 diagram Figure 3

Claims (1)

[Scope of Claims] (1) Transfer] - A memory cell array consisting of memory cells each composed of a transistor and a charge accumulation capacitor having a cell plate to which a predetermined voltage is applied;
A word line for selecting a memory cell during the memory cell play, and a noise canceling word line which is supplied with an inverted signal of the signal driving the word line and driven in synchronization with the word line. A semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1, further comprising a cell plate to which a voltage approximately 1/2 of the ζ power supply voltage is applied as the predetermined voltage.