JPS5960715U - Automatic recording level adjustment device - Google Patents
Automatic recording level adjustment deviceInfo
- Publication number
- JPS5960715U JPS5960715U JP15325682U JP15325682U JPS5960715U JP S5960715 U JPS5960715 U JP S5960715U JP 15325682 U JP15325682 U JP 15325682U JP 15325682 U JP15325682 U JP 15325682U JP S5960715 U JPS5960715 U JP S5960715U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- amplification circuit
- capacitor
- output
- variable gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案装置の電気回路図、第２図は、同じく
ステレオ録音の場合の電気回路図をそれぞれ示す。
１．１ａ・・・録音電流の入力端子、２，２ａ・・・可
変利得増巾回路、３，３ａ・・・磁気ヘッド、バイアス
回路を含む録音回路、４，４ａ、 １３，１３ａ・・
・ダイオード、５，５ａ、１４，１４ａ、１６，１６ａ
・・・コンデンサ、６，９，６ａ、１５，１５ａ−・・
抵抗、７ ｂ−・・インピーダンス素子、７，７ａ・・
・オペアンプ、１２・・・電気スイッチ、１０．１１・
・・規準電圧源端子、８・・・切換スイッチ。
第
２ 図FIG. 1 shows an electric circuit diagram of the device of the present invention, and FIG. 2 shows an electric circuit diagram for stereo recording. 1.1a... Recording current input terminal, 2, 2a... Variable gain amplification circuit, 3, 3a... Recording circuit including magnetic head and bias circuit, 4, 4a, 13, 13a...
・Diode, 5, 5a, 14, 14a, 16, 16a
... Capacitor, 6, 9, 6a, 15, 15a-...
Resistor, 7b--Impedance element, 7,7a...
・Operational amplifier, 12...Electric switch, 10.11・
...Reference voltage source terminal, 8...Selector switch. Figure 2
Claims (1)
とする可変利得増巾回路と、該可変利得増巾回路の出力
に接続された磁気ヘッドとそのバイアス回路を含む録音
回路と、前記した可変利得増巾回路の出力を整流して直
流出力を得る為の第１のダイオード、第１のコンデンサ
、及び第１の抵抗を含む所定の時足数の整流回路と、該
整流回路の出力を第１の端子の入力とする差動増巾回路
と、規準電圧源より、電気スイッチ及び第２のダイオー
ドを介して充電される第２のコンデンサ及び該コンデン
サと並列に接続された第２の抵抗と、第２のコンデンサ
の充電電圧を前記した差動増巾回路の第２の反転端子に
入力せしめる電気回路と、前記した差動増巾回路の出力
を、前記した可変利得増巾回路の制御入力とする負帰還
回路と、再生録音の切換スイッチ若しくはポーズ指令の
押釦操作と前記した電気スイッチの連動装置とより構成
されたことを特徴とする自動録音レベル調定装置。In a magnetic recording/playback device, a variable gain amplification circuit inputs an electric signal to be recorded, a recording circuit including a magnetic head connected to the output of the variable gain amplification circuit and its bias circuit, and the above-mentioned variable gain amplification circuit. A rectifier circuit for a predetermined number of hours including a first diode, a first capacitor, and a first resistor for rectifying the output of the gain amplifying circuit to obtain a DC output; a differential amplification circuit input to one terminal; a second capacitor charged from a reference voltage source via an electric switch and a second diode; and a second resistor connected in parallel with the capacitor. , an electric circuit that inputs the charging voltage of the second capacitor to the second inverting terminal of the differential amplification circuit, and a control input of the variable gain amplification circuit that inputs the output of the differential amplification circuit. 1. An automatic recording level adjustment device comprising: a negative feedback circuit; a playback/recording selector switch or a press button for a pause command; and an interlocking device for the electric switch described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15325682U JPS5960715U (en) | 1982-10-12 | 1982-10-12 | Automatic recording level adjustment device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15325682U JPS5960715U (en) | 1982-10-12 | 1982-10-12 | Automatic recording level adjustment device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5960715U true JPS5960715U (en) | 1984-04-20 |
| JPH0233329Y2 JPH0233329Y2 (en) | 1990-09-07 |
Family
ID=30339119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15325682U Granted JPS5960715U (en) | 1982-10-12 | 1982-10-12 | Automatic recording level adjustment device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5960715U (en) |
-
1982
- 1982-10-12 JP JP15325682U patent/JPS5960715U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0233329Y2 (en) | 1990-09-07 |
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