JPS595763A - Electric power and signal transmission system - Google Patents

Abstract

PURPOSE:To obtain a signal/electric power simultaneous transmission system which evades such a higher voltage than necessary that dielectric strength causes a problem, by providing a means of setting the crest value of transmit data to a specific value of a remotely fed voltage. CONSTITUTION:Transmit data and a gate signal (a) are supplied to a synchronizing circuit 11 and a clock generating circuit 12. The output data (c) of the synchronizing circuit 11, while modulated by a polarity inverting circuit 13 to a biphase signal format with a synchronizing component as shown in a figure (d), is converted into such two signals A and B reversing in phase each other that the crest value of the digital transmit signal is equal to the necessary voltage of DC power supply electric power to be supplied to a remote terminal. A reception side at a remote spot rectifies those two signals A and B on full-wave basis to obtain DC power supply electric power and also receives the data from the transmission side 1 through an integration circuit 21, clock discriminator 22, and signal discriminating circuit 23 to perform restoration [ to waveform (h)].

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power+1 signal transmission system that shares a transmission line.

In the case of remote control of various devices and devices using wires, interlocking of parent and child devices, etc., DC power and signals may be transmitted from the transmitting side to the receiving side using a common transmission aVc.

In such cases, the signal is usually superimposed on the DC power and transmitted, and then separated on the receiving side, but in this case,
As the potential in the transmission line increases9, the insulation of the transmission line must be increased, and the withstand voltage of the necessary components must be increased to withstand the potential on both the transmitting and receiving sides, resulting in significant cost savings. In some cases, it is necessary to consider the negative effects on the surrounding area due to the high potential.

Therefore, the present invention attempts to avoid such drawbacks by seamlessly combining the DC power source power and the signal to be transmitted.11 On the transmitting side, the serial digital signal to be transmitted is Converts both digital transmission signals into two digital transmission signals set to the required voltage of the DC power to be transmitted and whose polarities are opposite to each other.
At the receiving end, both received digital transmission signals are split into two, one side separates the original serial digital signals from both digital transmission signals, and the other side This rectifies the digital transmission signal and reproduces the DC power supply power.

The illustrated embodiment will be described below.

FIG. 1 is a block diagram showing the configuration of the (b) path. In the figure, 1 is a transmitting side, 2 is a receiving side, and 1 to n receiving sides are arranged in parallel. These are, for example, digital circuits that process 8 bits of serial data per frame.

FIG. 2 is a timing chart showing the No. 18 waveform of each part in FIG. 1.

The transmitting side 1 uses a serial digital signal source (data) consisting of 8 bits "1°H+l□l' for each frame as a transmission signal, and also uses the signals g, A gate signal with an 8-bit interval as shown in FIG. , the clock generation circuit is based on the gate signal as shown in FIG.

The first half of the period t per bit shown in is “0” and the second half is “1”.
” and sends it to the synchronization circuit 11 and the polarity inversion circuit 13.

Upon receiving the transmission data and the clock pulse, the synchronization circuit 11 outputs 8 bits of "1" per frame as shown in FIG. A serial digital signal consisting of 0'1 is output and sent to the polarity inversion circuit 13.

The polarity inversion circuit 13 converts the serial digital signal (
In response to the clock pulse (i 2 , ) and the clock pulse (i 2 , ) shown in FIG.
A shown in FIG. 2e, in which the digital transmission signal is modulated into a digital transmission signal such as a phase signal, and the peak value of the digital transmission signal becomes the required voltage of the DC source power to be transmitted, and the polarity thereof is reversed.

BConvert into two transmission output signals and output. in particular,
As shown in Figure 3, exclusive (JR
The circuit 131 is connected to the forward and reverse two switching circuits 13 in the subsequent stage.
2, 133, the exclusive U R circuit iai receives the serial digital signal clock pulse and changes the serial digital signal at the rising and falling points of the clock pulse, and changes the serial digital signal to "1" and "1".
The two forward and reverse switching circuits 132 and 133 modulate the digital transmission signal into the digital transmission signal shown in FIG. The power is amplified and output into two forward and reverse transmission outputs of 1g having high power.

Note that these two transmission output signals are trapezoidal waves as shown in FIG. 2e, but this is due to the transient characteristics of the output circuit, transmission line, etc. Figure 2 f, Figure C
For reference, the transmission output signal that appears when the 8th bit is "I II" indicated by the dotted line in the serial digital signal of 0 is shown.

The two transmission output signals A and B are transmitted to the receiving side 2 through one transmission line and two transmission lines each.

The receiving side 2 branches the received forward and reverse two transmission signals 100 to 100, 100 to 100 to the integration circuit 2I, and the other to the double wave rectifier path 24.
Enter.

The integration circuit 21 removes noise from the signal and distributes it to the clock discrimination circuit 22 and the signal discrimination circuit, and the clock discrimination circuit 22 reproduces the clock pulse shown in FIG. 2g from the signal. Then, it is sent to the signal discrimination circuit O, and the signal discrimination circuit tg1. ．． The signal from the integrator circuit and its clock pulses decode the serial digital signal i'r shown in the second figure. Further, the double-wave rectifier circuit 24 distorts the two forward and reverse transmission signals and sends it to the smoothing circuit 5. The smoothing circuit smoothes the rectified waveform (trapezoidal wave) to return it to the original DC power supply voltage. It is reproduced and output as power source power. The output is supplied as a power source to a subsequent device and is also used as a power source for each circuit on the receiving side.

Specifically, as shown in FIG. 3, the integrator circuit 21 includes CR circuits 211 and 212 in which diodes are arranged in parallel at the front stage, and a Schmitt trigger inverter 213 at the rear stage in two forward and reverse signal lines. , 214, and the time constants of the CR circuits 211 and 212 are switched by diodes on the outgoing and return paths of the signal, and therefore, as shown in FIG. (Figure 4a
, ), the positive 11+11 A k i 4 is shaped into a slightly wider square wave shown in Figure 4, and the negative side B is shaped into a square wave with a narrower width Vc shown in Figure 4 C1.

Otsuk discrimination circuit 22Ii, exclusive in the front stage
Equipped with a monostable multivibrator 222 at the rear stage, exclusive
Two square waves are connected to the OR1412 circuit (Figure 4).
, FIG. 5C,)k, and the time difference between them results in the pulse shown in FIG. 4D, which triggers the monostable multivibrator 222, which causes The clock pulse shown in Figure 4e is obtained. In addition, the clock pulse is pulse "r period t /2
Set the trigger pulse to the monostable multivibrator 222 (Fig.
, ) is prohibited, and the monostable multivibrator 222 is prohibited from being re-triggered at the middle of the period to obtain the desired number of pulses.

The signal discriminator circuit consists of a register 231, receives the signal from the integrating circuit 21 (see Figure 4) and the above clock pulse, and selects II 1 at the rising point of the clock pulse.
11 and "I II TE I + 1., .111 II and 11011 "0" K changes or continues Fig. 4 f
, that is, the original serial digital signal (second figure, ) is reproduced. The serial digital signal lags the original signal by about four.

According to the present invention, signals and DC power can be transmitted using two transmission lines, multiple receiving sides can be installed in parallel, and power can be obtained even if there is no power source on the receiving side. The construction work during equipment installation is simple and simple, and the electric potential in the transmission line does not increase, so there is no need to increase the insulation of the transmission line, and the withstand voltage of the circuits on the transmitting and receiving sides increases. There is no need to do this, reducing costs. It is extremely convenient and useful.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention. FIG. 1 is a block diagram showing the main configuration, FIG. 2 is a timing chart showing signal waveforms in each part of FIG. 1, and FIG. FIG. 4, a circuit diagram showing a specific circuit example, is a timing chart showing signal waveforms at each section (receiving side) Vc in FIG. l...Sending side 2...Receiving side l]...Synchronization circuit 21...Integrator circuit 12...
... Clock generation circuit 22 ... Clock discrimination circuit 1
3... Polarity inversion circuit O... Signal discrimination circuit 24.
・Double wave rectifier circuit δ・・・Smoothing circuit

Claims (1)

[Claims] On the transmitting side, the serial digital signal to be transmitted is converted into two digital transmission signals whose peak value is set to the required voltage of the DC power supply power to be transmitted, and whose polarity is positive and opposite, so that both digital transmission signals are It is transmitted to the receiving side through one transmission line, and on the receiving side, both received digital transmission signals are branched into two, one side distinguishes the original 7 real digital signals from both digital transmission signals, and the other side separates the original 7 real digital signals from both digital transmission signals. A power/signal transmission method characterized by rectifying both digital transmission signals on the side to reproduce DC power supply power.