JPS5955508A - Ladder monitor device - Google Patents

Abstract

PURPOSE:To attain quick check and maintenance work and to improve the working efficiency, by displaying automatically a ladder wiring diagram of a basic sequence circuit at a display device in case said sequence circuit having a sequence control circuit has a fault. CONSTITUTION:A sequence control circuit is formed by providing a ladder- shaped wiring to each other among basic sequence circuits provided in response to each controlled system. Fault detecting circuits C1-Cn are provided to those basic sequence circuits, and the numeric data is transferred to a data memory 2 through data transfer circuits DT1-DTn. A CPU3 works based on a control program stored in a program memory 4 when said numeric data is transferred to the memory 2. A CPU5 serving as a control circuit reads a fault diagnosing program sent from a CPU3 out of the memory 4. Based on this data, the ladder wiring diagram is displayed at a CRT8 for a faulty sequence circuit through a display driving circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a sequence control circuit in which basic sequence circuits that are installed corresponding to each controlled object and that operate according to a predetermined sequence are wired to each other in a ladder shape. This invention relates to a ladder monitor device that automatically displays a ladder wiring diagram of the failed basic sequence circuit on a display device such as a CRT when a controlled object related to the circuit fails for some reason.

Conventionally, in a sequence control circuit that operates each controlled object according to a predetermined sequence, control related to a certain basic sequence circuit among the basic sequence circuits that are wired in a ladder shape to each other forming the U and -t sequence control circuits. When an object breaks down for some reason, only a maintenance manager with a considerable number of years of experience can easily discover the faulty basic sequence circuit. Furthermore, the larger the scale of the sequencer, the more difficult it is for a maintenance manager to easily discover the larger the number of basic sequence circuits, making inspection and maintenance work extremely difficult. It was hassle-free.

This invention was made in order to solve the above-mentioned problems, and its purpose is to mutually ladder the basic sequence circuits which are provided for each control RJ object and operate according to a predetermined sequence. When a certain basic sequence circuit fails in a sequence control circuit wired in the form of d3, the ladder wiring diagram of that basic sequence circuit is automatically displayed on a display device such as CR1, An object of the present invention is to provide a ladder 1-unit device that can speed up inspection and maintenance work and improve work performance.

An embodiment of a ladder monitor device embodying the present invention will be described below with reference to the drawings.

In FIG. 1, the Nijiken control circuit 1 shown at J5 is constructed by wiring a large number of basic sequence circuits UC1 to UCn in a ladder shape, and each of the Amagi sequence circuits U
01 to U C11 operate according to a predetermined sequence, and actuate the corresponding controlled objects (not shown).

In Figure 12, failure detection circuits 01 to C11 are provided corresponding to the basic sequence circuits UC1 to UCn, and detect failures in the basic sequence circuits UC1 to UCn, respectively, and transmit the detection signals to the next stage data transfer. Circuitry 1
~D'1- Output to n. Each detection circuit 01 to C11
In this embodiment, ``indicates'' each of the circuit elements such as relays, timers, relay contacts, limit switches, and thermals installed in the basic sequence circuits UC1 to UCn. By detecting the same basic sequence circuit UC1 and U Cn's failure PiI, abnormalities in circuit elements, process delay abnormalities, or failures specific to the controlled object (for example, motor overload, setting abnormalities, positioning abnormalities, The relays and other circuit elements to be detected in each of the basic sequence circuits Uc1 to Ucn are each assigned a relay number, and are identified by the relay number. ing.

Each data transfer circuit list 1 to D'l'n is a circuit number that specifies each basic sequence circuit UC1 to UCn that is a detection target of the failure detection circuits C1 to C11, respectively;
In this embodiment, numerical data representing the relay number is set in advance.

When a detection signal is input from each of the data transfer circuits DT 1 to 1) to the corresponding fault detection circuit c 1 to On, the set numerical data is transferred to the data transfer circuit DT 1 through the first storage circuit. Transfer to 2 and cover.

When the data is transferred to the data L2, the central processing unit (hereinafter referred to as the first CPU) 3 stores the data in the program memory 4 in the second storage circuit. Control program []
In addition to storing the control program described above, the program menu U4 also stores a fault diagnosis program. Each basic sequence circuit UC1
~Ladder data for displaying the ladder wiring diagram of UCn and when each basic sequence circuit UC1 to UC11 breaks down, the basic sequence circuit UC+-UC11
There is each fault indication data C for displaying the names of circuit elements such as relays and the details of the fault. Zoshi C1 1st CI
) When the number 1 direct arta is transferred to the daimono 72, U3 transforms j'l at -, and based on the data, the block [
The same number of 11r1 data stored in 1gramme7ri4, TJ
Basic sequence circuit UC corresponding to four relay numbers
1 to UCn, and outputs a control signal for reading the J-gram data.

Based on the control signal from the first CPU 3, the central processing unit (hereinafter referred to as the second CPU) 5 as a control circuit executes the iWJ program memory 40 specified by the first CPU 3. The failure program data is read out, and based on this data, the display drive circuit 7 is programmed as shown in FIG. It outputs a display control signal for displaying the name 10a, its failure details 10b, the name 11a of circuit elements such as relays, and the failure details 111). At this time, the second CP LJ
! 5 is the number stored in the Demono Seven 2 (the ladder diagram 9 displayed on the CRT 8 based on the 1r1 data).
The circuit elements that are energized are displayed as ()/L, l--, and the circuit elements that are not energized are displayed as half-1--.

The USB disk device @6 transfers each program data to the program memory 4 and records each program data in the program memory 4.

Next, the operation of the ladder data device configured as described above will be explained.

Now, for example, the I (th) basic sequence circuit UCk of the sequence control circuit 1 has failed for some reason, and the failure detection circuit Ck detects it and sends the detection signal to the data transfer circuit 1.
When output to Tk, the data transfer circuit DTk transfers the numerical data preset in the circuit D'1-k to the data memory 2.

When the numerical data is transferred, the first CPU 3 executes a fault diagnosis program for displaying the failure of the basic sequence circuit 1 corresponding to the numerical data. , outputs the control fU number for reading the data in A to the second CPIJ55.
In response to this control signal, the LJ 5 reads out the designated program data and numerical data from the data memory 2, and outputs a display control signal to the display drive circuit 7 in accordance with this data.

Therefore, the display drive circuit 7 is configured to display a ladder diagram 9 of the kW-th basic sequence circuit LJCk on the CRT 8 (for example, the same circuit Ck).
If it is configured as shown in FIG. 3 but not shown in FIG. The circuit elements that are not energized are displayed as half 1--, and the name 10a of the controlled object and its failure details 10() and the circuit element name 11a and its failure details 111 are displayed.
) is displayed at the bottom of the ladder diagram 9.

In this way, in this embodiment, the ladder diagram 9 displayed on the CRT 8, the failure names 10d and 11a, and the failure details 1Qb
With RE 4J, which produces ILB, you can immediately see the failure location and failure details, and inspection and maintenance work can be performed quickly and accurately.

In addition, in this embodiment, the basic sequence circuit UC+~
Fault detection circuits 01 to On are provided for UCn, but C fault detection circuits C1 to Cn are provided for only a desired part of the basic sequence circuits UC1 to UCn to detect -C1 faults, and a ladder wiring diagram is created. It may also be displayed.

As described in detail above, the present invention provides a sequence control circuit that is provided corresponding to each controlled object and operates each relay that drives the controlled object in accordance with a predetermined sequence. When a certain basic sequence circuit breaks down for some reason, the ladder wiring diagram of the basic sequence circuit is automatically displayed on the display device 6. This will speed up inspection and maintenance work. It is industrially excellent as a rudder and monitor device that can improve work performance.

[Brief explanation of the drawing]

Fig. 1 (sequence control circuit diagram for explaining the present invention; Fig. 2 is an electric block circuit diagram of the ladder monitor device; Fig. 3 is a circuit diagram for explaining the basic sequence circuit diagram; Fig. 4) is an explanatory diagram showing contents displayed on a CRT. Sequence control circuit 1, data memory 2, program memory 4, CPU 5, display drive circuit 7, CRT 8, basic sequence circuits UC1 to UCn, and failure detection circuits C1 to Cn.
, data transfer)'A circuit 1) T1~D"I-n. Patent applicant: Toyota Auto Range Co., Ltd.
Patent Attorney On 1) Hironobu

Claims (1)

[Scope of Claims] 1. A sequence control circuit that is installed corresponding to each controlled object and operates each relay that drives the controlled object according to a predetermined sequence, the sequence control circuit comprising: A display drive circuit that displays the ladder wiring diagram of each basic sequence circuit on the display device, and a display drive circuit that corresponds to a part or all of each of the basic sequence circuits.
A detection circuit that detects a failure of the controlled object related to the corresponding basic sequence circuit, and a basic sequence circuit that is installed corresponding to each of the above detection circuits and corresponds to the detection circuit in A. A data transfer circuit in which numerical data representing a circuit number is set in advance and which transfers the numerical data based on the detection operation of the detection circuit; and a data transfer circuit that stores the numerical data transferred from each of the data transfer circuits. a first memory circuit; a second memory circuit that stores ladder data for displaying a ladder wiring diagram of the basic sequence circuit; read numerical data from the first memory circuit; reads the ladder data of the basic sequence circuit corresponding to the numerical data from the second storage circuit, and based on both data, outputs a display control signal for displaying the ladder wiring diagram of the basic sequence circuit on the display device. , and a control circuit that outputs to the display drive circuit. 2. The detection circuit detects the operating state of the relay or relay contact that constitutes the basic sequence circuit, and detects and overturns a failure in the basic sequence circuit. and the numerical data representing the circuit number identifying the basic sequence circuit in the data transfer circuit is preset with numerical data representing the relay M month identifying the relay. The ladder seven-unit field described in paragraph 1.