JPS5955039A - 封止形半導体装置 - Google Patents

封止形半導体装置

Info

Publication number
JPS5955039A
JPS5955039A JP57166208A JP16620882A JPS5955039A JP S5955039 A JPS5955039 A JP S5955039A JP 57166208 A JP57166208 A JP 57166208A JP 16620882 A JP16620882 A JP 16620882A JP S5955039 A JPS5955039 A JP S5955039A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
semiconductor chip
epoxy
external terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57166208A
Other languages
English (en)
Inventor
Kiichi Futai
二井　喜一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57166208A priority Critical patent/JPS5955039A/ja
Publication of JPS5955039A publication Critical patent/JPS5955039A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕　　　　　　　゛ この発明は１例えばエポキシ等の樹脂で封止加工（パッ
ケージング）された、ＰＥＴ等の封止形半導体装置に関
する。。
〔発明の技術的背景〕
例えばＦＡＴ等の半導体装置は、エボキシャシリコーン
等の樹脂で封止加工（パッケージング）されている。こ
れら２つの樹脂のうち、・エポキシ樹脂を用いて封止加
工した場合は、フレームとの接着強度１機械的特性１価
格等Ｃ二優れており、またシリコーン樹脂を使、用した
場合は。
耐熱性、＊気的特性、熱伝導性等に優れている。
そしてこのエポキシ樹脂やシリコン樹脂は、約Ｊ　ｏＩ
ｌΩ・副以上の絶縁体としての抵抗率を有している・ 〔背景技術の問題点〕 しかし、このようなエポキシ樹脂やシリコーン樹脂ン…
いて、Ｆｈｉ’ｌ’等の半導体装置を封止加工すると、
これらの樹脂が有する抵抗率は約７’　ｏ＠　ｍΩ・（
７）以上と非常に高い抵抗率のため１例えばこのＦＢＴ
等の半導体装置を、複数個まとめて運搬する場合、半導
体装置相互間の摩擦により、樹脂【：大量の静電気が発
稙してしまう口Ｃｏ　＊置。静電、め鼻ヶカえ。、半導
体、ｉ体がｌｉｌ損じたり、また装置の本抹外面Ｃユは
□こり等が付看して例えは′λ部端子等の導串′性な低
下させてしまう。
〔発明の目的〕
この発明は上記のような問題点を解決するためになされ
たもので１例えばＦＢＴ等の樹脂封止された半導体装置
（−おいて、樹脂（−静電１気が発生して装置が破損す
ることな防止できる封止形半導体装置を提供することを
目的とするＤ〔発鳴の概要〕　□　　□ Ｔなわち、、９、の発明Ｃ子・、係る封止形半導体□汐
装置：、２４．−□ 半導体チップおよびこれに関連する外部端子？。
Ｉ性樹脂を混入した１−ｊη録の１脂により封５圧した
ものである。　　　□ 〔発明の実施例〕′−１ 以７−而によりこの発明ＯＷ−実施例を説明する。（９
）はその装置・を示・じたち・ので、第１図１は、甲平
面崗、第、２．図は第１画のＡ−Ａ′線Ｃユおける断面
構成を示すも□ので、・単導体チップｉｉの電極端子ｔ
　２ａ　−’　７２”ｂ”）ｉ’　”、’ワイヤ７　、
？　ｔｌ　、”Ｉ　；？斥により外湘端□子ｔ’　ン’
　ａ　”、′’ｔ　”４　ｂｔ二接続して外部１１゜ に引き出すよう龜さ糺ソいるシそしてこ：の半導体チッ
プＩＩおよびワイヤ１３ａ　、　ｌ　、９　ｂ　７ａｊ
含む外部端子／　４　ａ　＊　Ｉ　４　ｂ　？Ａ（Ｄ円
囲は、樹脂１５により封止加工（パッケージング）が施
される。
こ力樹１１＠ｉｓは、型内で所定の重量比で添加される
硬化成形する口 この封止用の樹脂１５には１例えは金属との接１強度や
機械的特性に優れた。エポキシ等の□：′：゛１門脂□
を扇いる・このエポキシ樹脂ｆ二は１例えば胃・、町ヒ
踊：力添加と同時Ｃ，ポリアセチレン等の導、、ｉ、１
１″＆訃１°０°１”７ぜ、−１“、−入着に伴ない、
″絶縁性情脂昨しての□工・ボキシ□樹脂は１次第に導
電性を帯諒るようになるもので、この導電性樹脂の混入
量は１次のような上限および下限からなる範囲で考えら
れる。
上限＝４脂１５の導□電Ｗが同上す□ること（巳□より
生じるよう（二なる。外廓端子（’　Ｊ’　ｔ　ａ　、
：、　ｔ　４ｂ）間のリーク覗流が、半導体装置として
の性能上悪影響を及は丁こ唐のなｌ／：”、樹脂″１６
の抵抗率が約１ｏｌＩ　Ω：・ｍ１以上功範囲、′　□
　　　　′□下限：°樹脂、５の導電ｔ４’ｚｘ失ｉゎ
ｋて絶縁体となることのない、＃ｉ−脂５の抵抗率が約
１０’″Ω・ｍ以下の範囲。
つまりエポキシ等の封止用樹脂に、上記のような上限お
よび下限で設定した範囲内において。
ポリアセチレン等の導電性樹脂を混入し、半導電性の封
止用樹脂を形成するロ ー「なわちこのような抵・抗率の減少した半導電性の樹
脂１１５を用いて、半導体チ、ツブｌ″ノを封１に加工
すれば、ん４ｎ￥１ｔｓｔ：発生する静“５気の量は、
極くわすかなものとなる。、ｏ　　、、・、例えば、上
記した導電性樹脂の混入量：を、、調節し。
抵抗率をノθ′００．・−安、設定し亨、、、懸脂ノ５
を用いて、半力脳体−ツ７　ｔ、、、、　ｔ　、　７封
、止加工、シ、て、次！ようＣ二試験してみる。すなわ
ちこの樹脂封止され、　・　、′：′、、、１１ま た半導体装置を１例えば運搬時を想定して。
１０９旧固町とめ、てて・ヒ、、ミ＝γＡ　（ＪＪ、琴
！、、【石入れ。
こり〕容器な適当に振動させ、この振動により半１１１
　１１　１１１１１ 導体装置相互間に起る摩擦によって、封止用の、１・１
″、１′：：・１ニー・・ ％ｌｉｌ　５賢静市５．カ、雫：、生、ｔ　；６．Ｆ　
瞥トｊ、竺、・　モ、のようにして七〇〕静電気の量を
測定してみたとこ、　　　　　　　、：゛　１　　・ ろ、答器振動後ＯＪ？ｉ＋１．ｌ定結果より、５０ｖ程
度で・　　　：１１ あることが確認された。
しかし上茜是１と同様の静警気、試←、！、’−ｊ’抵
抗率がｔ　ｏ’″Ω・鋸である。従来の絶縁性樹脂で封
止い　　　　　　　　　　　、、、１．　　・　・　　
　１　。
加工された半導体装置で行なうと、約２００ν□　　　
　　　　　　　　　　　　　　　　　・　１゜もの静電
気が発生し、た。Ｔなわちこの試験上において明らかと
なるようＣと、半導体チップｉｔの封止用樹脂として、
導電性樹脂を混入した半導電性の樹脂１５を用いること
Ｃ巳よ１）、□半導体装置（二発生する静市気量１・１
．従来め約２ｏθＶ□がら５ｏ　Ｖ程度に減少されるよ
うになる。□〔、発ＴｉＡｆＪ）効Ｖ）　　′、　　　
　　　　　　・以上のようにこの発明（−よれば、・絶
′礫性樹脂に導電性樹脂な゛弾入した半導電性の樹１脂
を用いて封１を加工された半導体装置を使用丁□ること
によ１）１例えばこの装置の運搬時に発生する静電気の
□階を、４４くわず、かに抑えることができる妊で、半
導体装置自体が静“重患（二、よって破損することが解
消きれると共に、半導体装置：の外面に・はこｊ＋４が
付着しづらくなりン例えば外部端子等！７１奪小性が低
下することを防止で六るｎ４、因面の藺１４１な１免明
　　　　　　　　　　　　　□第１図はどの発明の一実
□施例に係る封止形半導体装：、麹を説：明する平面を
図、第２図は、第１図のＡ−’Ａ’線に沿った断ｌＩＯ
構成図である◎　□１１７７・・・半導体チップ、、Ｉ
４’ａ、ｊ４ｂ・・・外部端“子、ｔｓ・・・樹脂。
＝７− ３４！１図 矛２図 １７７−

Claims (1)

    【特許請求の範囲】
  1. 絶縁性樹脂（二導寧性樹脂を混入した半導電性の樹脂で
    封止加工を施したことを特徴とする封止形半導体装置。
JP57166208A 1982-09-24 1982-09-24 封止形半導体装置 Pending JPS5955039A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57166208A JPS5955039A (ja) 1982-09-24 1982-09-24 封止形半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57166208A JPS5955039A (ja) 1982-09-24 1982-09-24 封止形半導体装置

Publications (1)

Publication Number Publication Date
JPS5955039A true JPS5955039A (ja) 1984-03-29

Family

ID=15827095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57166208A Pending JPS5955039A (ja) 1982-09-24 1982-09-24 封止形半導体装置

Country Status (1)

Country Link
JP (1) JPS5955039A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1091407A1 (de) * 1999-10-04 2001-04-11 Infineon Technologies AG Überspannungsschutzanordnung für Halbleiterbausteine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1091407A1 (de) * 1999-10-04 2001-04-11 Infineon Technologies AG Überspannungsschutzanordnung für Halbleiterbausteine

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