JPS5954288A - Device for protecting hybrid integrated circuit - Google Patents

Device for protecting hybrid integrated circuit

Info

Publication number
JPS5954288A
JPS5954288A JP57165826A JP16582682A JPS5954288A JP S5954288 A JPS5954288 A JP S5954288A JP 57165826 A JP57165826 A JP 57165826A JP 16582682 A JP16582682 A JP 16582682A JP S5954288 A JPS5954288 A JP S5954288A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
output
semiconductor element
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57165826A
Other languages
Japanese (ja)
Inventor
花村 勝利
大山 照夫
川里 康雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP57165826A priority Critical patent/JPS5954288A/en
Publication of JPS5954288A publication Critical patent/JPS5954288A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (イ) 技術分野 本発明は混成集積回路の保護装置、特に熱的に検出を行
う保設装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field The present invention relates to a protection device for a hybrid integrated circuit, and particularly to a preservation device that performs thermal detection.

(ロン 従来技術 出力回路の保膿装置としては第1図に示す如(、コンプ
リメンタリ−出力トランジスタの夫々のエミッタに直列
に接続したエミッタ抵抗の電圧も、鳩を検出し、電圧隻
、■が一定値を超えると保護回路が働いてコンプリメン
タリ−出力トランジスタを遮断する方法が採られていイ
)。
(Ron) As shown in Figure 1, a conventional output circuit purulent preservation device detects the voltage of the emitter resistor connected in series to each emitter of the complementary output transistor, and the voltage is constant. If this value is exceeded, a protection circuit operates and shuts off the complementary output transistor.

斯る方法では正常状77、!?にも拘らず犬1ご号入力
時に出力回路に過大71i流が流れて保SIt回路が動
作する尽合がある。これは電圧検出方法に、Lるイ11
護装置1つ1は応答床jWがきわめて速いことに起因し
ている。
With this method, the normal state is 77! ? Nevertheless, there is a possibility that an excessive 71i current flows into the output circuit when the dog No. 1 is input, causing the protection SIt circuit to operate. This is due to the voltage detection method.
This is due to the fact that the response bed jW is extremely fast.

そこで出力トランジスタの発熱を検出して保護回路を動
作させる方法を提案する。この方法に依れば出力トラン
ジスタの発熱を倹知才ろので大信号入力時に保護回路が
働く不、都合を除去できる。
Therefore, we propose a method to detect the heat generation of the output transistor and activate the protection circuit. According to this method, the heat generated by the output transistor can be efficiently reduced, thereby eliminating the inconvenience and inconvenience of the protection circuit operating when a large signal is input.

その具体的構造を第2図に示す。アルミニウムの如き金
属基板(11)の表面に酸化アルミニウム膜の如き絶縁
薄層(1乃を設けた混成集積回路基板(1)−J二に銅
箔よりなる導電路(2)を設け、導電路(2)上にヒー
トシンク(3)を介して出力用トランジスタ(4)を固
着し、央に感温半導体素子(5)は近隣の導′71を路
(2)上に固着している。しかしなからj耕ろ+Il(
;告では出力トランジスタ(4)の発熱はヒートシンク
(3)→n?に路(2)→絶縁薄層(12)→金属基板
(11)→絶縁薄層(12)→導電路(2)の経路で感
温半導体素子(5)に伝達されるので、検知時間も長(
且つ熱抵抗も太き(なり出力トランジスタ(4)の発熱
を正確に検出できない欠点がある。
Its specific structure is shown in FIG. A conductive path (2) made of copper foil is provided on a hybrid integrated circuit board (1)-J2 in which a thin insulating layer (1) such as an aluminum oxide film is provided on the surface of a metal substrate (11) such as aluminum. (2) An output transistor (4) is fixed on the top via a heat sink (3), and a temperature-sensitive semiconductor element (5) in the center is fixed with a neighboring conductor '71 on the path (2). Nakara j till + Il (
;In the report, the heat generated by the output transistor (4) is caused by the heat sink (3)→n? Since the information is transmitted to the temperature-sensitive semiconductor element (5) through the path (2) -> insulating thin layer (12) -> metal substrate (11) -> insulating thin layer (12) -> conductive path (2), the detection time is also shortened. Long (
In addition, the thermal resistance is large (therefore, the heat generation of the output transistor (4) cannot be accurately detected).

(ハ) 発明の開示 本発明は世1点に鑑刀、てtCされ、良好l、C溝度ス
、や出方法に」、る混成集積回路の保護4リベを1;?
 fi+、するものである。
(C) Disclosure of the Invention The present invention has been thoroughly reviewed and evaluated, and provides four methods for protecting hybrid integrated circuits:
fi+.

本発明に依る混成集積回路の(’Z護装置i、Ifは第
31ツ]および第4図に示す如く、pグ(fべ導件金j
・1ツ’+’j イ)べ11)の表面に?縁薄層(12
)を設けた混Tr’Z隼イメ1111路ニアil:板i
ll上に所望の導電路(2)を設け、−外電路(2) 
J二にヒ トシンク(3)を介し7で出力トランジスタ
(4)’、設け、更にヒートシンク(3)上に感温半導
体素子(5)を固着し、出力トラ:/ジスタ(4)の発
熱をI盛固半;tj’、体イ・、了−(5)で検出して
出力回路の電流を遮断する様に構成されている。
As shown in FIG.
・On the surface of 1tsu'+'j a)be11)? Edge lamina (12
) Mixed Tr'Z Hayabusa image 1111 road near il: board i
A desired conductive path (2) is provided on the ll, and a -outer conductive path (2)
An output transistor (4)' is provided at 7 through a human sink (3) to J2, and a temperature-sensitive semiconductor element (5) is fixed on the heat sink (3) to reduce the heat generated by the output transistor (4). It is configured so that the current of the output circuit is cut off by detecting the current value (5).

に)実施例 混成集積回路基板(1)はアルミニウムの如き良熱伝導
性金属基板(印の表面を陽極酸化により生成した酸化ア
ルミニウムの如き絶縁薄層(12)で被覆して形成さね
る。斯る混成集積回路基板(1)は放熱性に富むので出
力回路の組込みにり、に適である。
2) Embodiment The hybrid integrated circuit board (1) is formed by covering a highly thermally conductive metal substrate (marked surface) with an insulating thin layer (12) such as aluminum oxide produced by anodic oxidation. The hybrid integrated circuit board (1) has excellent heat dissipation properties, so it is suitable for incorporating an output circuit.

141[る混成集積回路基板(1)−J:には銅箔より
成る導電路(2)を所望のパターンにエツチング(2て
形成するO 導電路(2)上にはヒートシンク(3)なろうイ・1け
するQヒートシンク(3)上には出力トランジスタ(4
)および感温半導体素子(5)を固着する。ヒートシン
ク(3)の形状は第3図の如く平4′(1,なものでも
、λ)るいは第4図の如く階段状のものでも良い。後者
はボンディングを行う際に導電路(2)との段差をσオ
11する点で有利でk)る。感温半導体素子(5)とし
てはシリコンプレーナー型トランジスタあるいはシリコ
ンダイオード等を用いる。PN接合のもつ一2mV’/
CのAit fB−係数を利用しているからである。
A conductive path (2) made of copper foil is etched into a desired pattern on the hybrid integrated circuit board (1)-J. A. The output transistor (4) is placed on the Q heat sink (3).
) and the temperature-sensitive semiconductor element (5) are fixed. The shape of the heat sink (3) may be a flat 4' (1, λ) shape as shown in FIG. 3, or a stepped shape as shown in FIG. The latter is advantageous in that it reduces the height difference with the conductive path (2) when bonding is performed. A silicon planar transistor, a silicon diode, or the like is used as the temperature-sensitive semiconductor element (5). The voltage of the PN junction is 2mV'/
This is because the Ait fB-coefficient of C is used.

出力トランジスタ(4)の発熱は感温半導体素子(5)
で直ちに検出され、その出力で出力l・ランジスタ(4
)を流れる電流を遮断する様に働く。具体的には出力ト
ランジスタ(4)とそのドライバ一段の間の電源ライン
にリレー(力を挿入して、感温半導体素子(5)の出力
でこのリレー(7)を遮断する○第5図に更に具体化さ
れた作画装置を示す。感温半導体素子(5)としてPN
P)ランジスタを用い、PNP )ランジスタのベース
はツェナー?lj圧を抵抗R1およびR2で分圧して電
圧で所定の保護動作温度に対応してバイアスしている。
The heat generated by the output transistor (4) is generated by the temperature-sensitive semiconductor element (5).
The output is immediately detected by the output l transistor (4
) works to cut off the current flowing through the Specifically, a relay (force) is inserted into the power line between the output transistor (4) and the first stage of its driver, and the output of the temperature-sensitive semiconductor element (5) shuts off this relay (7). A more specific drawing device is shown.PN is used as the temperature-sensitive semiconductor element (5).
P) Using a transistor, PNP) Is the base of the transistor Zener? The lj pressure is divided by resistors R1 and R2, and the voltage is biased in accordance with a predetermined protection operating temperature.

出力トランジスタ(4)の温度上昇に伴いPNP)ラン
ジスタのベースエミッタ電圧V、1.が減少し設定電圧
以下になると、PNPトランジスタは導j山しリレー(
力は遮断して出力トランジスタ(4)(4)の電流を遮
断する。
As the temperature of the output transistor (4) rises, the base-emitter voltage of the PNP transistor (V) increases, 1. When the voltage decreases and becomes below the set voltage, the PNP transistor becomes conductive and the relay (
The power is cut off and the current in the output transistors (4) (4) is cut off.

(ホ)効果 本発明に依れば出力トランジスタ(4)(4)の過大電
流による発熱を感温半導体素子(5)で検出しているの
で、過大電流を検知するまで若干の猶予ができ瞬時的に
大信号が入力されたときに働くおそれはな(なり過保護
を防止できる。
(E) Effect According to the present invention, heat generation due to excessive current in the output transistors (4) (4) is detected by the temperature-sensitive semiconductor element (5), so there is a slight delay until the excessive current is detected. There is no risk of it working when a large signal is input (overprotection can be prevented).

更に感温半導体素子(5)は直接ヒートシンク(3)に
固着されるので出力トランジスタ(4)の発熱を早く且
つ正確に検知でき、精度の高い保1fiits)作を行
なえる○ 更にまた従来用いた高ワツトのセメント抵抗を不要とし
、保護装置を大巾に簡略化でき集積化に寄与できる。
Furthermore, since the temperature-sensitive semiconductor element (5) is directly fixed to the heat sink (3), the heat generated by the output transistor (4) can be detected quickly and accurately, allowing highly accurate maintenance. It eliminates the need for a high-wattage cement resistor, greatly simplifies the protection device, and contributes to integration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を説明する回路1″/.1、第2図Q主
従来の構造を説明する断面図、第3図および第4図は本
発明の構造を説明する断面図、第5図は本発明の具体化
された保護装置を説明する回路1ネ1である0 主な図番の説明 (1)・・・混成集積回路基板、 (2)・・・導電路
、 (3)・・・ヒートシンク、 (4)・・・出力ト
ランジスタ、(5)・・・感温半導体素子。 出願人 三洋電機株式会社 外】名
Figure 1 is a circuit 1''/.1 explaining a conventional example, Figure 2 is a cross-sectional view explaining the main Q main conventional structure, Figures 3 and 4 are cross-sectional views explaining the structure of the present invention, Figure 5 The figure is a circuit 1 illustrating a protection device embodying the present invention.0 Explanation of main figure numbers (1)...Hybrid integrated circuit board, (2)...Conducting path, (3) ... Heat sink, (4) ... Output transistor, (5) ... Temperature-sensitive semiconductor element. Applicant Sanyo Electric Co., Ltd. Name

Claims (1)

【特許請求の範囲】[Claims] 1、混成集積回路基板上に所望の導電路を設は該導電路
上にヒートシンクを介して出力用半導体素子を設けた出
力回路を有する混成集積回路において、前記ヒートシン
ク上に感温半導体i<子を付着し前記出力用半導体素子
の発熱を前記感温半導体素子で検出して出力回路の電流
を遮断することを特徴とする混成集積回路の保護装置。
1. A desired conductive path is provided on a hybrid integrated circuit board.In a hybrid integrated circuit having an output circuit in which an output semiconductor element is provided on the conductive path via a heat sink, a temperature-sensitive semiconductor i< element is placed on the heat sink. 1. A protection device for a hybrid integrated circuit, characterized in that heat generation of said output semiconductor element is detected by said temperature-sensitive semiconductor element to cut off current in an output circuit.
JP57165826A 1982-09-21 1982-09-21 Device for protecting hybrid integrated circuit Pending JPS5954288A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57165826A JPS5954288A (en) 1982-09-21 1982-09-21 Device for protecting hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57165826A JPS5954288A (en) 1982-09-21 1982-09-21 Device for protecting hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5954288A true JPS5954288A (en) 1984-03-29

Family

ID=15819731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57165826A Pending JPS5954288A (en) 1982-09-21 1982-09-21 Device for protecting hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5954288A (en)

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