JPS5954287A - Device for protecting hybrid integrated circuit - Google Patents

Device for protecting hybrid integrated circuit

Info

Publication number
JPS5954287A
JPS5954287A JP57165825A JP16582582A JPS5954287A JP S5954287 A JPS5954287 A JP S5954287A JP 57165825 A JP57165825 A JP 57165825A JP 16582582 A JP16582582 A JP 16582582A JP S5954287 A JPS5954287 A JP S5954287A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
temperature
semiconductor element
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57165825A
Other languages
Japanese (ja)
Other versions
JPH0355992B2 (en
Inventor
花村 勝利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP57165825A priority Critical patent/JPS5954287A/en
Publication of JPS5954287A publication Critical patent/JPS5954287A/en
Publication of JPH0355992B2 publication Critical patent/JPH0355992B2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (イ)技術分野 本発明は混成集積回路の保護装置、特に熱的に検出を行
う惺砕装置A1に関する。
DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field The present invention relates to a protection device for a hybrid integrated circuit, and particularly to a crushing device A1 that performs thermal detection.

(ロ) 従来技術 出力回路の保護装置としては第1図に示す如く、コンプ
リメンタリ−出力トランジスタの夫々のエミッタに直列
に接続したエミッタ抵抗の電圧等、■を検出し、電圧等
、V;が一定値を超えると保砕回路が働いてコンプリメ
ンクリ−出力トランジスタを遮断する方法が採られて℃
・イ)。
(b) As shown in Figure 1, a conventional protection device for an output circuit detects the voltage, etc., of an emitter resistor connected in series to each emitter of a complementary output transistor, and makes sure that the voltage, etc., V; is constant. When the temperature exceeds this value, a circuit is activated to cut off the complementary output transistor.
·stomach).

斯る方法では正常状態にも拘らず大信号入力時に出力回
路に過大電流がyllu ttて惺護回路力爾IJ作す
る場合がある。これは′r11圧検出方法による保護装
置は応答速I7!がきわめて速し・ことに起因している
0そこで出力トランジスタの発熱を検出して情i護回路
を動作させる方法を提案する。この方法に依才1は出力
トランジスタの発熱をIt知1゛4)ので大信号入力時
に保護回路が働(不都合を除去できろ。
In such a method, even in a normal state, an excessive current may be generated in the output circuit when a large signal is input, causing a protection circuit to be activated. This means that the protection device using the 'r11 pressure detection method has a response speed of I7! Therefore, we propose a method for detecting the heat generation of the output transistor and operating the protection circuit. The advantage of this method is that the output transistor generates heat (1-4), so the protection circuit works when a large signal is input (this problem can be eliminated).

その具体的構造を第2図に示す。アルミニウムの如き金
属基板(11)の表面に酸化アルミニウム膜の如き絶縁
t1・4層(12)を設けた混成44”、積回路基板(
1)上に銅箔よりなる導電路(2)を設け、導電路(2
)上にヒートシンク(3)を介して出力1’l’J ト
ランジスタ(4)を同着し、更に感温半導体素子(5)
は近隣の導電路(2)上に固着して℃・る。しかしなが
ら斯るTtM造では出力トランジスタ(4)の発熱はヒ
ー トシンク(3)→導電路(2)→絶縁薄層02→金
属基板(11)→絶線薄層圓→導電路(2)の経路で感
温半導体素子(5)に伝達さλLるので、検知時間も長
く且つ熱抵抗も大きくなり出力トランジスタ(4)の発
熱を正確に検出できない欠点がある。
Its specific structure is shown in FIG. A hybrid 44'', integrated circuit board (
1) A conductive path (2) made of copper foil is provided on the conductive path (2).
), an output 1'l'J transistor (4) is attached via a heat sink (3), and a temperature-sensitive semiconductor element (5) is also attached.
is fixed on the neighboring conductive path (2). However, in such a TtM structure, the heat generated by the output transistor (4) follows the path of heat sink (3) → conductive path (2) → insulating thin layer 02 → metal substrate (11) → disconnected thin layer circle → conductive path (2). Since λL is transmitted to the temperature-sensitive semiconductor element (5), the detection time is long and the thermal resistance is also large, making it difficult to accurately detect the heat generated by the output transistor (4).

(ハ)発明の開示 不発1工1〕は切点に鑑みてなさiシ、良好な温度検出
方法による混成集積回路の保護装置を4是供するもので
ある。
(C) Disclosure of the Invention [1] In view of the cut-off point, the present invention provides a protection device for a hybrid integrated circuit using a good temperature detection method.

本発明に依る混成集積回路の保6り6装置直は第3図に
示す如く、良熱伝導性金属基板01)の表面(lこ絶縁
薄層02)を設けた混成集積回路基板(1目二に所望の
導電路(2)を設け、導電路(2)上にヒートシンク(
3)を介して出力トランジスタ(11)を設け、出力ト
ランジスタ(4)の近傍の絶縁N層(I2)を除去(−
2て露1tl l、た基板(11)上に感温半導体素子
(5)を固>k L、出力トランジスタ(4)の発熱を
感温半導体素子(5)C検出して出力回路の電流を遮断
する様に構成されている。
As shown in FIG. 3, the device for maintaining a hybrid integrated circuit according to the present invention is a hybrid integrated circuit board (first side) provided with a surface (l thin insulating layer 02) of a metal substrate 01 with good thermal conductivity. A desired conductive path (2) is provided on the second conductive path (2), and a heat sink (
3) through which the output transistor (11) is provided, and the insulating N layer (I2) near the output transistor (4) is removed (-
2. After 1tl l, the temperature-sensitive semiconductor element (5) is fixed on the substrate (11). The heat generation of the output transistor (4) is detected by the temperature-sensitive semiconductor element (5), and the current of the output circuit is It is configured to block.

(ロ)実施例 混成集積回路基板(1)は、アルミニウムの如き良熱伝
導性金属基根囲の表面を陽極酸化により生成した酸化ア
ルミニウムの如き絶縁薄層(12)で被覆して形成され
る。斯る混成集積回路基板(1)は放熱慴に富むので出
力回路の組込みに最適でス・)る。
(B) Embodiment The hybrid integrated circuit board (1) is formed by covering the surface of a metal base with good thermal conductivity such as aluminum with an insulating thin layer (12) such as aluminum oxide produced by anodic oxidation. . Such a hybrid integrated circuit board (1) has excellent heat dissipation and is therefore ideal for incorporating an output circuit.

斯る混成集積回路基板(1)上には年1箔より成る導電
路(2)を所望のパターンにエツチングにより形成する
On the hybrid integrated circuit board (1), conductive paths (2) made of foil are formed in a desired pattern by etching.

導電路(2)上にはヒートシンク(3)を介して出力ト
ランジスタ(4)を固着している。また出力トランジス
タ(4)の近傍の絶縁薄層(12)をエンドミルで研削
して基板的)を露出し、基板(叩上に感温半導体素子(
5)を銀ペーストで固着する。感温半導体素子(5)と
してはノリコンプレーナー型トランジスタあるし・はシ
リコンダイオード等を用いる。l)N接合のもつ一2m
V/pの温度係数を利用しているからである。
An output transistor (4) is fixed on the conductive path (2) via a heat sink (3). In addition, the insulating thin layer (12) near the output transistor (4) is ground with an end mill to expose the substrate (substrate), and the temperature-sensitive semiconductor element (
5) is fixed with silver paste. As the temperature-sensitive semiconductor element (5), a planar type transistor, a silicon diode, or the like is used. l) N-junction length 2m
This is because the temperature coefficient of V/p is used.

出力トランジスタ(4)の発熱は感温半導体素子(5)
で検出され、その出力で出力トランジスタ(4)を流れ
る電流を遮断する様に働く。具体的には出力トランジス
タ(4)とそのドライバ一段の間の電源ラインにリレー
(力を挿入し7て、感温半導体素子(5)の出力でこの
リレー(力を3#i 11;j’rする。
The heat generated by the output transistor (4) is generated by the temperature-sensitive semiconductor element (5).
The output is detected by the transistor (4), and its output works to cut off the current flowing through the output transistor (4). Specifically, a relay (force) is inserted into the power supply line between the output transistor (4) and the first stage of its driver, and the output of the temperature-sensitive semiconductor element (5) is used to connect this relay (force) to the power line between the output transistor (4) and the first stage of its driver. r.

第4図に更に具体化された保勲装(1〆1゛を示す。感
温半導体素子(5)としてI) N P l−ランジス
タを月1い、PNP)ランジスタのペースも、l−ツノ
−ノー−’(H,JEケ抵抗R7およびR2で分圧した
′電圧で191定の(、j、、護動作温度に対応してバ
イアスしていイ)。出力トランジスタ(4)の温度上昇
に伴いI)NI) )ランジスタのペースエミッタ電圧
V、1.が減少し設定電圧以下になると、PNPトラン
ジスタは導通しリレー(7)は遮断して出力トランジス
タ(4+(Jの電流を遮断する。
Fig. 4 shows a more specific protection device (1〆1゛).As the temperature-sensitive semiconductor element (5), the I) N P l-transistor is used once a month, and the pace of the PNP) transistor is also -No-' (H, JE, voltage divided by resistors R7 and R2 is 191 constant (, j, biased according to the protection operating temperature). Due to the temperature rise of the output transistor (4) I) NI) ) Pace emitter voltage V of the transistor, 1. When the voltage decreases to below the set voltage, the PNP transistor becomes conductive and the relay (7) is cut off, cutting off the current of the output transistor (4+(J).

(ホ) 効果 本発明に依れば出力トランジスタ(4)(4)の過大電
流による発熱を感温半導体素子(5)で検出【7てい2
)ので、過大電流を検知するまでの若干の猶予ができ瞬
間的に大信号が入力されたときに1111 (:に;そ
れはな(なり過保護を防止できる。
(e) Effect According to the present invention, heat generation due to excessive current of the output transistor (4) (4) is detected by the temperature-sensitive semiconductor element (5) [7
), there is a slight delay until overcurrent is detected, and when a large signal is momentarily input, 1111 (:に;That's not it) can prevent overprotection.

更に感温半導体素子(5)は直接基板(11)に固着さ
れるので出力トランジスタ(4)の発熱を早(検知でき
確実に保護+lij作できる。
Further, since the temperature-sensitive semiconductor element (5) is directly fixed to the substrate (11), heat generation of the output transistor (4) can be detected quickly and protection can be reliably performed.

更にまた従来用いた高ワツトのセメント抵抗を不要とし
、保護装置を大巾に簡略化でき集積化に寄与する。
Furthermore, the conventionally used high-wattage cement resistor is not required, and the protection device can be greatly simplified, contributing to integration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1Nは従来例’X i+S1’明する回路図、第2図
は従来の構造を説明する断面図、第31¥1は本発明の
詳細な説明する断面図、第4図は本発明の具体化さt’
tた保護装置aを説明する回路図で、15)る。 主な図番の説明 (1)・・・混成集積回路基板、 (,2)・・・4′
j1(j路、 (3)・・・ヒートシンク、(4)・・
・出力トランジスタ、(5)・・・感温半導体素子。
No. 1N is a circuit diagram explaining the conventional example 'X i + S1', FIG. 2 is a cross-sectional view explaining the conventional structure, No. 31\1 is a cross-sectional view explaining the present invention in detail, and FIG. 4 is a specific example of the present invention. t'
15) is a circuit diagram illustrating the protective device a. Explanation of main drawing numbers (1)...Hybrid integrated circuit board, (,2)...4'
j1 (j path, (3)... heat sink, (4)...
- Output transistor, (5)...temperature-sensitive semiconductor element.

Claims (1)

【特許請求の範囲】[Claims] 1、良熱伝導性金属基板の表面に絶縁薄層を設けた混成
集積回路基板上に所望の導電路を設は該導電路上に出力
用半導体素子を設けた出力1回路を有する混成集積回路
において、前記出力用半導体素子の近傍の前記絶RR層
を除去して露出1−だ金属基板表面上に感温半導体素子
を伺%”(L、、ifl !!旧11力用半導体素子の
温度上昇を前記感温半2jj;休素子で検出して出力回
路の電流を遮断することを特徴とする混成集積回路の保
護装置f’f。
1. A desired conductive path is provided on a hybrid integrated circuit board having a thin insulating layer on the surface of a metal substrate with good thermal conductivity. , remove the RR layer in the vicinity of the output semiconductor element and place the temperature-sensitive semiconductor element on the exposed metal substrate surface. A protection device f'f for a hybrid integrated circuit, characterized in that the temperature sensing half 2jj is detected by the dead element and the current in the output circuit is cut off.
JP57165825A 1982-09-21 1982-09-21 Device for protecting hybrid integrated circuit Granted JPS5954287A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57165825A JPS5954287A (en) 1982-09-21 1982-09-21 Device for protecting hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57165825A JPS5954287A (en) 1982-09-21 1982-09-21 Device for protecting hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS5954287A true JPS5954287A (en) 1984-03-29
JPH0355992B2 JPH0355992B2 (en) 1991-08-27

Family

ID=15819711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57165825A Granted JPS5954287A (en) 1982-09-21 1982-09-21 Device for protecting hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5954287A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5146254A (en) * 1974-10-14 1976-04-20 Nanba Press Kogyo Kk

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5146254A (en) * 1974-10-14 1976-04-20 Nanba Press Kogyo Kk

Also Published As

Publication number Publication date
JPH0355992B2 (en) 1991-08-27

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