JPS595314A - Data processor - Google Patents

Abstract

PURPOSE:To shorten a monitor period without increasing a processing load of a central processor, by collecting a data by the number of times of collection by a data transmission controlling circuit, and thereafter, transferring in a lump the collected data to an input/output apparatus. CONSTITUTION:A high speed monitor request signal is generated to a picture processing device 4 from a process 8. The picture processing device 4 transmits a monitor data collecting period, a data address group, the number of times of collection, and the number of monitor data to a transmission controlling circuit 3. The inside of the transmission controlling circuit 3 receives a command through a transmitting and receiving circuit 10 and a transmitting and receiving buffer circuit 11, and a command deciding circuit 12 and a monitor data collecting period timer 13 are set, a collecting frequency counter 14 is set, a monitor data number register 15 is set, and an address of an address buffer memory 16 is stored. After said operation is completed, a data of a process input/output device 2 is transferred to a monitor data buffer memory 18 by a transfer controlling circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that monitors a process, etc., and particularly to a data processing device that can monitor the operation of a process even when the response of an input/output device cannot fully follow the operation of the process. The present invention relates to a data processing device.

As shown in FIG. 1, the data processing device that monitors processes, etc. has 1 central processing unit (CPU) 1. Process input/output device 2, transmission control circuit 3, image processing device 4 and CRT
Consists of 7. The central processing unit 1 of such a data processing apparatus often performs not only data collection for monitoring process input/output data, but also other important data processing. Therefore, in order to reduce the processing load on the central processing unit 1, transfer by dynamic memory access (DMA transfer) is performed between the process input/output device 2 and the transmission control circuit 3.

The image processing device 4 sends a data transfer request command 5 to the transmission control circuit 3, and after receiving the monitor data 6, the CR
Display monitor data on T7.

However, the transmission time between the transmission control circuit 3 and the image processing device 4 is long, and the processing time of the image processing i[4 itself is long, so that the monitoring period (TM) is generally about 1 second or more. Therefore, if a process change occurs at or below T4, it could not be fully monitored.

On the other hand, in cases where process changes occur in several tens to hundreds of milliseconds, the process movement is unlikely to affect the entire time period.

The purpose of the present invention is to reduce the process change by several tens to several lQQms.
Even if this happens, it should be possible to monitor it.

FIG. 2 shows an embodiment of a data processing device according to the present invention.

Process 8 issues a high-speed monitor request signal 9 to image processing device 4 to notify that high-speed monitor is required. In response to this, the image processing device 4 transmits the monitor data collection cycle TM, data address group, number of times of collection, and number of monitor data to the transmission control circuit 3 as a data transfer request command.

Within the transmission control circuit 3, commands are sent to the transmission/reception circuit 10. The command is received via the transmission/reception buffer circuit 11, and the command judgment circuit 12, settings of the monitor data collection cycle timer 13, settings of the collection number counter 14, settings of the monitor data number register 15, and the address of the monitor data are stored in the address buffer memory 16. Remember. After the above operations are completed, the data is transferred to the monitor data buffer memory 18 without being processed by the transfer control circuit 17.

That is, the transfer control circuit 17 transfers the address stored in the address buffer memory 16 to the address buffer 1.
9, a path acquisition right request signal zO is sent to the central processing unit l, and after receiving the path acquisition permission signal 21, an address signal 22 and a data transfer signal 23 are output. Process input/output device 2ti.

Upon receiving the data transfer signal 23, the data is transferred to the monitor data buffer memory 18. After one cycle of this transfer is completed, the address of the next monitor data is moved to the address buffer 19, and the address of the re-monitor data buffer memory 18 is also moved to the next address. After repeating the above operation the number of times set in the monitor data number register 15, the address of the address buffer memory 16 is returned to the initial address. On the other hand, the address of the monitor data buffer memory 18 is continuously updated to the next address.

This completes the first monitoring operation. The next monitoring operation is started after the set time of the monitor data collection cycle timer 3 has elapsed. The monitoring operation is repeated for the number of times set in the collection number counter 4.

With this, the transfer between the process input/output device 2 and the monitor data buffer memory 18 is completed. Thereafter, the data in the monitor data buffer memory 1B is transferred to the transmitting/receiving buffer 11. It is transmitted to the image processing device 4 via the transmitting/receiving circuit IO.

In this way, the data collected at high speed is transferred to the image processing device 4 and C.
It can be analyzed using RT7.

According to the present invention, the monitoring cycle, which conventionally required about 1 second, can be reduced to several tens of seconds without increasing the processing load on the central processing unit 1.
It can be shortened to m5.

[Brief explanation of drawings]

Figure 1 shows a prototype of a data processing device using a CRT. Ze; Figure 1 /y-7 ), →)

Claims (1)

[Claims] 1. Transfer the monitor data collection cycle, address group, number of collections, and number of monitor data from the input/output device that displays monitor data to the data transmission control circuit, and transmit the data transmission control circuit and the process input/output device. The monitor between
By collectively transferring the collected data to the input/output device after collecting data for the number of times of data collection in each data collection cycle, the processing load on the central processing unit is not increased, and the input/output device and the data transmission device A data processing device that records and analyzes changes in process conditions in a shorter time than the response time of.