JPS5952885A - Super conductive schottky transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable to form a broad-band high sensitive amplifying circuit of microscopic signal and a high speed logic circuit of microscopic logic amplitude and low power consumption by a method wherein a superconductive metal layer and two semiconductor layers are joined together, said superconductive metal layer is turned to an emitter or a collector, the first semiconductor layer is turned to a base, and the second semiconductor layer is turned to a collector or an emitter. CONSTITUTION:An n type impurity semiconductor layer 13 is grown on an n<+> type substrate 1 by performing a crystal growing method, and a p type impurity semiconductor layer 14 is formed thereon. Subsequently, after a semiinsulating semiconductor layer 15 has been formed, a transistor is formed by providing a superconductive metal electrode 16 and electrodes 17 and 18. The impurity layers 13, 14 and the semiinsulating layer 15 are formed using the same substance as the base material by controlling the dopant so that the required impurity density or semiinsulating layer can be formed. As a result, a high sensitivity and low noise amplification of microscopic signal or a low level and high speed switching operation can be performed at the operating temperature less than the superconductive transition temperature of the superconductive material of superconductive metal electrode 16 based on the principle of operation different from the conventional bipolar and the field-effect type transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a super shot;V- transistor and a method of manufacturing the same.

The basic structure of conventionally used bipolar transistors is a combination of pn junctions of semiconductors. In addition to the pn junction, the field effect transistor basically has a 4M structure including a Schottky junction or an MIS junction. The junction structure that is the basis of the operation of these transistors is a commonly used combination of semiconductor materials and metal materials. Any of these junction structures, ie, PN junction, Schottky junction, or 41Ml5 junction, has a barrier height of several hundred mV or more. Therefore, in any case, the bias voltage to the element for transistor operation is required to be on the order of several volts, and even if technological expedients such as miniaturization of the geometrical shape are used, the bias voltage is low. There are limits to reducing noise and lowering power consumption, and it is no longer possible to meet the increasingly sophisticated needs of recent years.

Figure 1 shows the basic configuration of a conventional bipolar transistor, in which an n+ type (or p+ type) substrate 1 is placed under an upper pressure, a p type (or n type) impurity layer 2 is formed by diffusion or crystal growth, and On top of that, n-type (or p-type) impurities are formed in the same manner, and metal poles are formed at required locations. In this device structure, a substrate 1 which is a semiconductor portion. Impurity layer 2. A barrier-free ohmic junction is created between the impurity 3 and the metal of the electrodes 4, 5, and 6, respectively. Created in this way,
By applying an appropriate bias voltage to the pn junction between the impurity layer 3 and the impurity layer 2 and between the impurity layer 2 and the substrate 1, active functions such as amplification or switching of the signal applied to the 'a electrode are performed. be able to.

For example, the pn junction barrier height is 0 in the case of Si (silicon).
．． Since the voltage is 8 to 1V, the lowest IV bias voltage must be applied to operate, and this value cannot be significantly reduced by 1V, so the width of the impurity layer 20 and the voltage
Measures such as reducing the distance between I40 to submicrons are aimed at reducing the force and increasing the operating speed. However, the power consumption of a single Si bipolar transistor is about 2 mW, and the switching speed is about 80 ps, which has almost reached its limit, and the current situation is that no further improvement can be expected.

Figure 2 shows the basic structure of a general conventional MIS type lightning field effect transistor, in which an n-type (or p-type) semiconductor layer 8 is formed on an insulating substrate T, and a metal electrode is placed on top of the n-type (or p-type) semiconductor layer 8. 11
and 12 to serve as source and drain electrodes, respectively, and source electrodes 11 . An insulating layer 9 and a metal electrode 10 above the insulating layer 9 are formed between the drain electrodes 12 to serve as a gate electrode. When the gate electrode 1 (IK voltage number V) is applied, a so-called channel layer is formed between the semiconductor layer 8 and the insulating layer 9, and the current flowing through the source i+ between the pole z and the drain electrode 12 changes. Using
It performs functional operations such as signal amplification or switching. In transistors with this structure, using Sl as the semiconductor material has the advantage that the power consumption is smaller than that of bipolar transistors, but has the disadvantage that the switching speed is several ns or more, which slows down the operation speed. . Furthermore, when a compound semiconductor material is used, the controllability of the interface between the semiconductor layer 8 and the insulating layer 9 becomes poor, making it unsuitable for practical use. There are two types of iW field effect transistors, one-junction type and Schottky junction type, which work on the same principle of operation, and one is Schottky junction type using compound semiconductor materials such as oaAs (gallium arsenide).
T is put into practical use, but in any case, the barrier height of the junction is several millivolts or more, so the power consumption is relatively large, about 1 μW per gate. The high barrier height also limits the low noise operation of the trap.

This invention was made in consideration of the above points, and reduces the power consumption and noise caused by the particularly high junction barrier of conventional bipolar transistors, and achieves low noise and high sensitivity of the micro size 1A. It is an object to obtain bipolar transistors based on new active mechanisms capable of amplification or low-level fast switching. Furthermore, by manufacturing an integrated circuit based on this element, it becomes possible to realize a highly sensitive wideband amplifier or a high-speed logic circuit. The present invention will be explained below based on the drawings.

The third figure is a diagram showing the basic purchase of a super Schottky transistor as an embodiment of the present invention. As shown in 1 to 5 in the same figure, this transistor further includes an n-type (or p-type) impurity semiconductor 7PN (hereinafter referred to as an impurity layer) 13 on an n+ type (or p+ type) substrate 1.
A p-type (or n-type) impurity semiconductor layer (hereinafter referred to as an impurity layer) is formed by crystal growth such as B E, etc.
14 It is also formed mainly by crystal growth. Subsequently, a semi-insulating semiconductor layer (hereinafter referred to as semi-insulating layer 5) 15 is formed by the Y crystal growth method, and then a superconducting metal electrode 16. Denmurai 1r.

It can be used as a transistor by providing 18 feet. Here, the impurity layer 13. Impurity layer 14. Semi-insulating layer 1
No. 5 is made by using the same material as a 1σ body and controlling the dopant so as to form the required impurity concentration or semi-insulating 1 sigma. In addition, impurity layer 1
3. A grain phase may be selected so that a Peter junction is formed between the impurity layers 14 instead of a pn junction. Furthermore, the height of the Schottky barrier formed between the superconductor metal electrode 16 and the semi-insulator If415 is selected to be a combination that is about 7 degrees lower in the case of ohmic properties. The substrate 1 has an impurity layer 13 grown thereon. Since the impurity layer 14 and the semi-insulating layer 150 grow as crystals, they are made to have lattice matching with these materials, and 18 ohmic electrodes are provided on the side opposite to the grown layer.

As a specific example of this structure, for example, an n-type ink is used on the substrate 1.
(indium phosphide) or n-type oaAs (gallium arsenide), impurity layers 13, 14. InGaAs (indium gallium arsenide) is used as the base material of the semi-insulating layer 15, the impurity layer 13 is n-type, the impurity layer 14 is p-type, and the semi-insulating layer 1
5 controls the impurity concentration so that it becomes semi-insulating. Impurity layer 13. A Peter junction is used between the impurity layers 14. 9
The impurity layer 13 is Kn-type InGaAs, and the impurity rf
P-type InP or p-type InAIP (indium aluminum phosphorus) is used for N 14, and semi-insulating 1nl' is used for semi-insulating layer 15Ilc. In this case, the semi-insulator layer 15 is made extremely thin to a few LOi or less to form the impurity layer 14 and the superconductor metal layer. ! 16 can also be provided. Furthermore, as the material of the superconductor metal electrode 16, pb (lead), Nb (
A superconducting material such as niobium (niobium) is used, and it is covered with a material such as gold to prevent deterioration such as oxidation. Also, the pole 17.
Gold or the like is used for 18.

The superconductor metal electrode 1 was designed by Takumi to have such a structure.
It is possible to perform high-sensitivity, low-noise amplification or low-level, high-speed switching operations based on operating principles different from conventional bipolar or field-effect transistors at an operating temperature below the superconducting transition temperature of superconducting materials (6). can.

That is, by using a super Schottky junction instead of the conventional pn junction, at around ±ImV,
Efficient tunnel injection can be performed between the superconductor metal electrode 16 and the impurity layer 140. The first reason is that the density of states of the superconducting metal is extremely large around ±1 mV, so that the tunnel current l can be increased. At this time, in order to lower the tunnel resistance and perform injection efficiently,
In order to obtain an extremely low Schottky barrier of close to 1 mV, it is necessary to use a semiconductor material that can reduce the barrier height. For example, in addition to materials such as InGaAs,
Possible materials include G d HgTe, Pb, and 5nTe. Furthermore, the leakage current in the reverse direction is reduced by K, m
4 <Insert thin semi-insulator layer 1jY. Tunnel current is controlled by superconductor metal electrode 16. This is done by applying a voltage between the 11 and 11. The charged particles injected into the impurity layer 14 in this way are collected by a voltage applied to the pn junction or heterojunction between the impurity layers 13 and 14, pass through the substrate 1, and are collected at the electrode 18. The points are the same as in the case of a normal bipolar transistor. Also, unlike the case of a normal field effect transistor, super+If,
Although the conductive metal electrode 16 is made of metal, it is characterized by being an injection electrode at a low level in order to maintain the operating temperature at an extremely low temperature and make it a superconductor. According to a specific example using the above-mentioned moon phase, superconductor metal i! In the conventional bipolar transistor, the electrons injected by superm-conducting tunneling are reduced due to slight recombination in the base region and impurity layer 14.
It crosses the pn junction between 13 and the 1ll-\tero junction barrier to reach the region of impurity layer 13. The fact that the current delivery rate decreases due to loss in the base region is the same as in normal transistors. By using a mixed crystal semiconductor material to lower the barrier height, high-sensitivity, low-noise amplification of minute signals or low-level high-speed switching becomes possible. The pn junction or hethyl junction between the impurity layers 13 and 14 is made of the material of the above-described specific example to create a structure with an extremely shallow junction barrier, thereby achieving low noise and low power consumption.

For this purpose, the pn junction structure includes a structure that conducts by a tunnel mechanism as well as a normal junction conduction mechanism.

FIGS. 4 and 5 show other embodiments of this invention,
The basic configuration of the present invention shown in FIG. 3 is a modification of the bipolar transistor.

1 structure shown in FIG. 4 is made by making the structure shown in FIG. P14.
The Schottky barrier formed between the superconducting metal poles 16 is made of a material that has an appropriate height, and the temperature associated with it is
The depletion J□□□ formed in the semi-insulating material 415 shown in FIG.
It is characterized by being 1 instead of 0.

A transistor with such a structure can be manufactured using a single crystal growth method that allows good control of impurity concentration and film thickness, such as MBIE.
, MO-CVD, LPE or CVD. J, select a substrate 1 made of a material that is easily lattice matched with a semiconductor material that has a low Schottky barrier height formed between it and a superconducting metal such as N, b, k' b, etc.
The surface of this substrate 10 is made to have good mechanical flatness and is clean at the atomic level, and an impurity layer 1 having the required characteristics is formed thereon.
3.14. The semi-insulator layer 15 is formed by sequentially growing a single crystal using a single crystal growth method such as MBB.

The first construction shown in Figure 5 is the actual 'It'! , ii, 'j Technique 61G This was done in view of the convenience, and the basic operating principle is the same as that in FIG. 3, with a buffer layer 19 provided between the substrate 1 and the impurity layer 130. be. This buffer layer 19 provides lattice matching between the substrate 1 and the impurity layer 130,
This layer is for forming good quality impurity layers 13, 14 and semi-insulating layer 15 on the clean surface, and is usually made of the same type of semiconductor as substrate 1, and is made of impurity layers 13, 14 and semi-insulating layer 15 on top of substrate 1. It is grown in the same manner as layer 15.

This method is characterized in that high-quality semiconductor chips with good lattice matching can be obtained.

As a specific example, similar to the specific example of the embodiment shown in FIG.
After growing PIFl as a buffer layer 19, InGaA
, s impurity layer 13. ．． 14 and semi-insulating layer 15, or InGaA, s as impurity M13.
1nPIi as impurity waste 14 and semi-insulating layer 15
Alternatively, I nA, IAs Jf4 Y is grown.

Thereafter, an electrode layer made of a superconducting metal is applied to the semi-insulator layer 15.
A superconducting metal electrode 16. electric 4ti
1? Then, electrodes 18 are formed to complete the basic structure.

An integrated circuit based on the basic structure and operating principle described above is created by forming a composite pattern including interconnections by a process such as photoetching on a structure formed up to the superconducting metal ML pole 16 layer. It is.

In Figures 3 to 5, the thickness of each phase material in 1ja construction is as follows. Substrate 1 is InP.

The impurity layer 13 is a semiconductor layer made of G aAs m I n AS or the like and has a thickness of 100 μm to 500 μm.
A low-barrier, high-mobility layer made of nGaAs or the like with a thickness of 500 to 0.5 μm.

The impurity layer 14 is InP, InAIP"E or InGaA
The base cambium layer consists of
m, the semi-insulator layer 15 is a barrier leakage current adjustment layer made of InPt or 1nGaAs, and has a thickness of 0 to 100k; the buffer layer 19 is made of 1nP or 1nGaA8, etc., and the substrate 1.
and 0.5 μm to 1-μm thick active layer for lattice matching.
shall be. In addition, the superconductor metal plate 16 has a thickness of Nl)
s o 7V~0.2μm-+-Au I (10A
The thickness is about 0.5 μm, or about 0.2 μm with a combination of PB, In, and Au. The ohmic electrodes 17 and 18 are made of a metal suitable for each substrate and have an arbitrary thickness.

As explained in detail above, the super Schottky transistor according to the present invention is composed of a junction between a superconducting metal layer and first and second semiconductor layers, with the superconducting metal layer serving as an emitter or a collector, Since the first semiconductor layer is used as the base and the second semiconductor layer is used as the collector or emitter, if this super Schottky transistor is considered as the basic structure of an integrated circuit, it can be used as a wide-band high-sensitivity amplifier circuit for minute signals of less than μV. Furthermore, it becomes possible to create a low power consumption high speed logic circuit with a minute logic amplitude of around 1 mV. Also,
Super Schottky diodes are used mainly in the extremely low temperature region, below the superconducting transition temperature of superconducting metals, because they are expected to improve performance by about two orders of magnitude compared to conventional Schottky transistors in both noise level and power consumption. high-sensitivity electromagnetic wave detectors such as or Josephson junction diodes, and first-stage Il'' amplifiers of general low-noise amplifiers, S Q [
It has extremely excellent effects, such as being able to configure a low-level, low-power consumption logic operation circuit similar to the first-stage amplifier of a high-sensitivity sensor such as JIL, a Josephson logic operation circuit, and the like. It is something.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of the configuration of a conventional bipolar transistor, FIG. 2 is a schematic diagram of the configuration of a conventional single-hole, field-effect transistor, and FIG. 3 is a schematic diagram of the configuration of a super Schottky transistor as an embodiment of the present invention. FIG. 4 and FIG. 5 are schematic diagrams of the configuration of the modified example. In the figure, 1 is a substrate, 13 and 14 are impurity layers, 15 is a semi-insulating layer, 16 is a superconducting metal ↑a, 17° and 18 are electrodes, and 19 is a buffer layer. i゛"-...,゛・1 Figure 1 Figure 3 Figure 4 Figure 5 Akira (1117 I'// Month / 7111
= Indication of lN'l Relation to Showa S year special Irf application No. 1 Otsu 339θ and the case of the person who made the 3h11 correction. 'II
:(ifi l 'Yumi 4 Designated Agent Ibaraki ll, 1 Niiharu-gun Sakura Htl+i Garden 11111 Suzari 4-;
00351 Chestnut Institute of Technology Iir Technology Comprehensive Research Income 5 卍 5 卍 5 卍 5 卍 5 卍 5 卍 The detailed description of the invention in the detailed description of the invention in the 6 sleeve ``apply'' is corrected to ``apply the voltage number V''. (2) “p-type 111A1p” in page g, line 79 of the same
(-(Indium Aluminum Phosphorus)” is “p-type InAlA
s (indium aluminum arsenide)". (3) Same, page 10, line G, “GdHgJ is “0 song g”
I am corrected. (4) Same, on page 14', first line, "desired location" is corrected to "required location." (5) Same, 1st ode, 1st line [InAlp J to i
] Corrected as nAlAs J.

Claims (4)

[Claims] (1) Consisting of a superconducting metal layer and a first and second semiconductor layer, the %i4'+11. The conductive metal layer is used as the emitter or collector, and F+II Tl
13. A super Schottky transistor whose base is the first semiconductor Jf4 and whose collector or emitter is the second semiconductor layer. (2) Consisting of a superconducting metal layer and a first and second semiconductor layer, the superconducting metal layer is used as an emitter or a collector, ^II Mj: the first semiconductor layer is the base, the first semiconductor layer is the A second semiconductor layer is used as a collector or an emitter, and a semiconductor material and structure are used as the first semiconductor layer to reduce the height of a Schottky barrier formed between the superconductor metal layer and the first semiconductor layer. Unique features and 1-Ro super Schottky transistor. (3) It is composed of a three-way junction of a superconducting metal layer and a first and second semiconductor layer, with the superconducting gold FA layer as an emitter or collector, the first semiconductor layer as a base, and the second semiconductor layer as an emitter or collector. a semiconductor layer t collector or emitter,
1. A super Schottky transistor further characterized in that a semi-insulating semiconductor layer for reducing leakage current is formed between the superconducting metal layer and the first semiconductor layer. (4) A second semiconductor layer made of n-type impurity-doped InGaAs on an n-type nP or n-type QaAS substrate, a second semiconductor layer 191G made of p-type impurity-doped InGaAs, and an impurity-doped semiconductor layer 191G made of p-type impurity-doped InGaAs. Not In
Semi-insulating semiconductor layers made of GaAs are sequentially grown, and a superconducting metal layer of Nb or Pb is placed on the ^II Ri4 semiconductor layer structure, and each required electrode part is formed. A method for manufacturing a super Schottky transistor characterized by obtaining a three-dimensional structure.