JPS5952849B2 - timing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a timing circuit, particularly a current source circuit that can be used to step-by-step select the slope of a sawtooth wave or ramp wave signal used for the time axis of an oscilloscope, etc. in a desired permutation. Regarding.

In general, an oscilloscope's time-domain slope signal generation circuit uses a plurality of high-frequency gradient signals to generate a slope signal having a calibrated (i.e., known), accurate, and widely varying slope. A Miller integrator circuit including a precision timing resistor and a timing capacitor or a combination of a constant current source and at least one timing capacitor is used.

One of the latter conventional examples is shown in FIG.

In FIG. 1, since the output voltage 2 from the potentiometer 10 is applied to the non-inverting input terminal of the operational amplifier 12,
The emitter voltage of transistor 14 is maintained at a substantially constant value of V2.

High precision (0.1% error) timing resistor R1~R
Of n, R-Rn are switches 81-5n-, respectively.
A voltage ■□ is applied via a switch 16 to one end of each of the timing resistors R1 to Rn.

If the switches 81 to Sn are selectively opened and closed and the timing resistors R1 to Rn are selectively inserted into the circuit, the composite timing resistance value becomes, for example, 4MΩ, 2MΩ,
800Ω, ..., 40KQ, 20Ω,
8 to Ω over a wide range, transistor 1
4 emitter current or collector current (timing current) 1out, for example, 10μA, 20μA, 50μ
A, -, can be varied in 1-2-5 permutations, such as 1 mA, 2 mA, 5 mA.

On the other hand, timing capacitors C1 to C3 are connected to the collector of the transistor 14, and among these, C2 and C3 are connected in series to switches SA and SB, respectively.

Additionally, the collector of transistor 14 is connected through a switch (eg, transistor) 18 to a sweep gate circuit (not shown).

Now, assuming that the switch 18 is in the open state, the timing current 1out flows into both the timing capacitor C1 and the timing capacitor q or q, or C2 and C3, selectively inserted into the circuit by the switches SA and SB. do.

Here, if the combined resistance value of the timing resistor and the combined capacitance of the timing capacitor actually inserted in the circuit are R and C, respectively, and the voltage across the timing capacitor is e, then Iout, = (Vl-V2)/ This is because of R, and a tilted wave with good linearity can be obtained.

The slope or timing of this slope wave is determined by the switches 81 to Sn.
, -1, and by selectively opening and closing SA and SB, for example, 1. 2. 5.10.20.50. ...
1-2-5 permutation of... or 1. 2. 4.10.
20.40. can be varied in a 1-2-4 permutation.

The voltage e is obtained from the output terminal OUT via the buffer tank intermediate unit 20.

Note that after the sweep period has passed, the switch 18 is closed by a signal from the sweep gate circuit, and the charges accumulated at both ends of the timing capacitor are discharged.

By the way, in a high-end oscilloscope, the maximum variable ratio calibrated for a timing current of 1 out is 40 in a 1-2-4 permutation.
0x, 1-2-5 permutation is 500x, and both are 9
precision timing resistors R1-R9 and at least eight switches 80-S8 are required.

Therefore, it has the disadvantage that the configuration is complicated, large in size, and expensive.

Furthermore, in order to continuously vary the slope of the voltage e between each step, the switch 16 may be connected to the potentiometer 22 side, and the voltage at the upper end of the timing resistors R1 to Rn may be varied. Since the current flowing through the potentiometer 22 changes depending on the magnitude of the timing resistance, the variable range changes, and the resistance value of the potentiometer 22 becomes negligible compared to the timing resistance value.

The present invention uses the voltage-controlled variable current source shown in FIG. 2 to provide a timing circuit with a relatively simple configuration that eliminates the drawbacks of conventional timing circuits.

Hereinafter, the present invention will be described in detail based on the accompanying drawings.

In FIG. 2, the output voltage 3 of the potentiometer 24 (used as a control voltage) is applied to the non-inverting input terminal of the operational amplifier 26, which is a voltage follower, so the output voltage of the operational amplifier 26 is also It is 3.

The other ends of resistors R□ and R2 (resistance values are also assumed to be R1 and R2, respectively) each having one end connected to the emitter (voltage ■2) of the transistor 14 are connected to a voltage ■0. Since the voltage (1)3 is applied, the timing current 1out, that is, 1out changes depending on the control voltage (3).

It is assumed that the current amplification factor β of the transistor 14 is sufficiently large and the base current can be ignored.

Therefore, as shown in FIG. 3, a voltage V□/3 is applied through the non-inverting input terminal 28 of the operational amplifier 12, and the resistance values of the resistors R1 and R2 are as shown in parentheses. The number in parentheses after the symbol indicating the resistor indicates the resistance value)
, by switching the switch SW in the order of terminals 30, 32° and 34, the voltage at the left end of this switch SW (the voltage in equation (1)
3) change to V, V1/3.0, respectively.

Therefore, in equations (2), (3), and (4), ■2=V
□/3. If R,=R2=R, when V3=■1, v32v1/3 or when open'," 1out1: 1out2: 1out3=
1 out can be changed in a 4:2:1, ie, 1-2-4 permutation.

On the other hand, as shown in FIG. 4, the voltage at the terminal 28 is set to v1/4.
If we change the resistance value of resistor R2 to 2R/3, we get (5
), (6), (7) in the same way as formulas,
,”1out1: 1out2: 1out3=100
:10:1, that is, the timing current 1out changes in a 1-10-100 permutation.

In each of the embodiments shown in Figures 3 to 5, three calibrated timing currents are obtained by using two timing resistors and one switch, so the configuration is simpler and cheaper than the conventional circuit. It is clear that this will happen.

Incidentally, in the embodiments shown in Figs. 3 and 4, the timing current 1out is only changed within one digit by the control voltage (3).
For example, if the resistance values R of resistors R1 and R2 in FIG.
With a 40-100-200-400 permutation, 1out can be made variable over three orders of magnitude.

Similarly, in FIG. 4, the values of resistors R1 and R2 are each set to 1.
If you switch to 0x and 100x and change the switch SW in each case, this time it will be 1-2-5-10-20-50-1
1 out can be varied over three orders of magnitude in the 00-200-500 permutation.

The details will be described later with reference to FIGS. 9 to 11.

It goes without saying that in the case of FIG. 5, modifications similar to those described above can be made if necessary.

However, in this case, if R1 and R2 are each multiplied by 1,000, the timing current can be varied over a wide range from 1 to 100,000 in 10 steps.

By the way, in the embodiments shown in FIGS. 3 to 5, the timing current 1
The change in out is 1-2-5. 1-2-4. 1-10
-100 permutations and not consecutive integer multiples,
According to the embodiment of the present invention shown in FIGS. 7a and 8a described below, the timing current 1out can be adjusted from 1 to 9 using a simple circuit.
can be varied in successive integer permutations.

Before explaining the embodiments shown in Figs. 7a and 8a, we will explain the circuits having the same effects as those in Figs. 6a and 6a.
This will be explained based on figure b.

In FIG. 6a, if the resistance values of the resistors R1 to R4 are as shown in the figure and the voltage at the terminal 28 is R2, then the transistor 14
Since the emitter voltage of is also R2, when only the switch S1 is closed When only the switch S2 is closed When only the switch S3 is closed When only the switch S4 is closed If it is selectively opened and closed as shown in (however, ○ means closed, no mark means open.

(The same applies to the following drawings), it can be seen that the timing current 1out can be changed to any integer from 1 to 10 by combining these switches.

Furthermore, the resistance value of each resistor R1-R4 is 10 times (or 1/
By newly providing four resistors with a value (10 times) and four switches, 1 out can be made continuously variable from 1 to 110.

Furthermore, if you add 4 resistors and 4 switches with values 100 times (or 17100 times), 1 out becomes 1 to 11
It can change continuously up to 10.

Now, FIG. 7a shows an embodiment of the present invention which achieves the same effect with a simpler structure than the circuit of FIG. 6a.

Connect resistors R1 to R3 and four switches to S4 with a resistance ratio of 1:3:0.6 as shown in the figure, and apply a voltage of 1/1 to terminal 28.
If 2 is applied, when only switch S1 is closed, when only switch S2 is closed, when only switch S3 is closed, when only switch S4 is closed, S1 to S4 are selected as shown in Fig. 7b. By opening and closing the timing current 1out, it is possible to change the timing current 1out to a continuous integer from 1 to 9.

Furthermore, the resistance value of each resistor R1-R3 is 10 times (or 1
If three new resistors and four switches with a value of /10 times) are installed and switched, 1out will change continuously from 1 to 99, and furthermore, 1 out will change continuously from 1 to 99. If you add 3 resistors and 4 switches, 1 out will be 1 to 99.
It will change up to 9.

The embodiment of FIG. 7a has the advantage over the case of FIG. 6a that it requires the same number of switches and does not require a high precision resistor per digit on one side, for example a timing current of 1ou
Continuously variable t up to about 1,000 times has the notable advantage of requiring fewer three high-precision resistors.

Therefore, according to this embodiment, the circuit configuration can be made simpler and more compact, which is of great economic benefit.

FIG. 8a is another example in which the resistance values of the resistors R1 to R3 in FIG. 7a are changed (resistance ratio 2:3:1),
By operating the switches 81 to S4 as shown in FIG. 8b, the timing current 1out can be continuously changed from 1 to 9.

Furthermore, in this embodiment, as mentioned in the embodiment of FIG.
/10 times) and 100 times (or 17100 times) and 8 switches, 1o
It is clear that ut can be varied in consecutive integer multiples from 1 to 999.

FIG. 9a shows another embodiment of the present invention, in which the timing current 1out is varied over a wide range using a simpler circuit, similar to the conventional example shown in FIG.

Switches S□, S2 each consist of two interlocking switches for selectively inserting resistors R2, R2' and R3, R3', respectively, into the circuit.

Now, if the switch 40 is connected to the calibration (CAL) side and the switches 81 to S4 are selectively opened and closed, the timing current is 1o.
ut changes over nine stages.

For example, as in the embodiment shown in FIG. 4, v2 is set to v1/4, the resistance values of resistors R□ and R1' are each set to R52R/3, and switch S1. Open S2/S3. When S4 is selectively opened and closed, 1out changes in a 1-2-5 permutation (see Figure 9b).

Next, with Sl closed, R2,
R2' is connected to make the parallel combined resistance value of resistors R1 and R2 R/10, and resistor R1'.

If the parallel resistance value of R2' is 2R/30, as shown in Figure 9b, when switch S2 is open, the remaining 83°S
By opening and closing 4, 1 out can be changed in a 10-20-50 permutation.

Furthermore, R3゜R3' are connected in parallel to form resistors R1 and R3'.
2. Parallel resistance value of R3 is R/100, resistor R□', R
If the parallel resistance value of 2' and R3' is 2R/300 and the switches 81 to S4 are opened and closed as shown in Fig. 9b, 1ou
t varies in 100-200-500 permutations.

On the other hand, if we look at the change in 1 out using the same method as above with reference to the example in FIG.
It can be seen that 1out changes in the 0-100-200-400 permutation.

Note that if the switch 40 is switched to the non-calibration (UNCAL) side and the potentiometer 42 is adjusted to change the output voltage of the operational amplifier 44 from 1 to 1, the switch S1
．． The timing current 1out is set to 10 regardless of whether S2 is opened or closed.
Since it can be varied over a wide range more than double, there is no need for timing to be calibrated, and it is suitable when it is desired to obtain an arbitrary timing current 1out.

As mentioned earlier, in a high-end oscilloscope, the maximum calibrated variable ratio of 1out is 500 times in the 1-2-5 permutation, and in the conventional example shown in Figure 1, nine high-precision timing resistors R1 to R9 and At least 8 switches S□ to S8 are required, but in this example, there are 6 timing resistors and 6 switches, both of which are 2/3, so the circuit configuration is simple, small, and inexpensive. There is an advantage that

Moreover, the accuracy of the timing current 1out is determined only by the resistor and the voltage 1, and is the same as the conventional circuit shown in FIG.

Incidentally, the timing resistors may be of a series type as shown in FIG. 10 instead of being of a parallel type as shown in FIG. 9a.

In this case, the switches S1 and 81' and S2 and 82' are respectively interlocked.

Also, R2 = 9R1, R3 = 90R1, R2' = 9R
1', R3'=9OR1'.

Note that the terminal 46 is connected to the switch 40 in FIG. 9a, and the terminal 48 is
is naturally connected to the emitter of transistor 14 in FIG. 9a.

The embodiment of FIG. 11 replaces switch S1 of FIG. 9a with switch 81' and diode D0. Substitute with D2, and further substitute with the 9th
Switch S2 in figure a is replaced with switch 82' and diode D3.
．． D4 was substituted, and the other parts are essentially the same.

In this embodiment, timing resistors R1', R2', R3
'The voltage at the right end of these resistors should be set to V2 or higher so that current flows only toward the emitter of the transistor 14.
Moreover, the resistance values of diodes D□ to D4 are R2 and R2, respectively.
', R3, R3', if it cannot be ignored, it is necessary to take this into account when selecting the timing resistance value.

FIG. 12 shows an operational amplifier 5 in place of the current source transistor.
1 is an embodiment of a timing circuit according to the invention using an integrator including 0 and a capacitor C and a switching transistor 52;

The base of transistor 52 is connected to, for example, a sweep gate circuit (not shown) to receive square wave pulses as shown.

The transistor 52 operates during the low level period t1 of the rectangular wave pulse.
The open circuit is turned off at ~t2, and the capacitor C is charged by the timing current 1out.

When time t2 is reached, the transistor 52 becomes conductive, the charge on the capacitor C is discharged, and a sawtooth signal as shown appears at the output terminal OUT of the operational amplifier 50.

By the way, when the resistance values of both resistors R1 and R2 are equal,
If the changeover switch 54 is switched to the contacts 54a, 54b, and 54C in this order, the voltage at the inverting input terminal of the operational amplifier 50 becomes approximately 0.
Since it is maintained at volt, the timing current 1out
It can be seen that it changes as V, /2R, Vl/R, and 2V1/R, and is variable in a 1-2-4 permutation.

Therefore, the slope of the slope signal at the output terminal OUT of the operational amplifier 50 also changes at the same rate.

FIG. 13 shows a case where the resistance value of the resistor R2 in FIG. 12 is multiplied by 273 and the voltage applied to the terminal 54a is changed to 1/3.

In this case, by switching the changeover switch 54, the fourth
As in the case of the figure, the timing current 1out is 1-2-5
It can be changed in permutations.

In Figure 14, four resistors and four switches are added to the circuit in Figure 12 or Figure 13, and the timing current 1out is reduced to 9.
This is a practical example of changing in stages.

Note that FIG. 14 specifically shows one embodiment of the internal circuit of the operational amplifier 50.

The base voltage of transistor Q1 is essentially 0 volts due to the cancellation of the base-emitter voltage VBE and the voltage drop across diode D1.If the gain of transistor Q1 is large enough, the base voltage fluctuation of Ql can be ignored, so it is possible to obtain an accurate slope. It is possible to obtain gradient waves that have a wide range of characteristics and vary over a wide range.

In this embodiment, for example, the resistance values of resistors R1 and R1' are both R1, the resistance values of resistors R2 and R2' are both R/9, the resistance values of resistors R3 and R3' are both R/90, and the voltage + v2
v1/2 and lever, timing current 1out is 1-2-
It can be varied in 4-10-20-40-100-200-400 permutations.

FIG. 15 shows still another embodiment of the present invention using a Miller integration circuit.

Transistor 14, resistors R1 to R3, R1' to R3'
, switches S1-S4, and S1'-S2' are current sources similar to those shown in FIGS.

The base of transistor 56 is connected to, for example, a sweep gate circuit (not shown), and a rectangular pulse as shown is applied to the base.

Before time t, the diode D1. D2 is conductive, and the timing current 1out of transistor 14 flows through diode D2 and not through capacitor C.

However, when the emitter voltage of resistor 56 becomes negative at time t1, diode D1. D2 is in a cut-off state.

Therefore, the timing current 1out flows into the capacitor C of the Miller integrator and charges it at a constant rate.

At time t2, the emitter voltage of transistor 56 increases and diode D1. D2 becomes conductive again, so capacitor C
The charge on the diode D0. is discharged. By canceling the voltage drop at D2, the output voltage becomes approximately 0 volts.

Therefore, a sawtooth voltage as shown is generated at the terminal OUT.

The timing current 1out can be determined by appropriately selecting the resistance value of the timing resistor as explained in detail in the previous embodiments.
Switch S...S2. S・', S2', S3. It is clear that by selectively opening and closing S4, it changes in nine stages.

Therefore, detailed explanation will be omitted.

In addition, in the circuits shown in Figs. 1 to 11, the timing current is 1o.
Since ut is changed, the base voltage of the transistor 14 remains approximately constant even when the switch is changed.

Even if the voltage applied to the non-inverting input terminal of the operational amplifier 12 is made variable, 1out will change, but in that case, the base voltage of the transistor 14 will also change, so the slope signal of the oscilloscope to obtain the desired large amplitude output will change. Not suitable for generation circuits.

Furthermore, in the embodiment of the present invention, the timing current 1out is mainly
Although we have explained the case where the
In all other embodiments like the embodiment in the figure, 1 out
Of course, it is possible to make it continuously variable.

As explained above, according to the present invention, the number of expensive components required can be reduced compared to conventional timing circuits, and the slope of the timing current, that is, the sawtooth wave or ramp wave signal, can be varied over a wide range. Since it can be changed, it is possible to miniaturize the circuit, which is extremely economically beneficial.

[Brief explanation of drawings]

FIG. 1 is a conventional timing circuit, FIG. 2 is a voltage-controlled variable current source circuit used in an embodiment of the present invention, FIGS. 3 to 5 are embodiments of the present invention, and FIG. 6a is a circuit other than the present invention. FIG. 6b is a diagram showing the open/closed state of the switch used to explain the operation of FIG. 6a, and FIG.
a, 8a. Figure 9a shows an embodiment of the present invention, Figures 7b and 8b, respectively.
Figure 9b is a diagram showing the open and closed states of the switches used to explain the operations in Figures 7a, 8a, and 9a, respectively.
Figures 0 to 15 are examples of the present invention. 10.22, 24, 42... Potentiometer, 12. 26. 44. 50... Arithmetic amplifier, 14, 52. 56. Ql, Q2...
Transistor, 20...Buffer amplifier, 28,4
6,48. OUT・・・Terminal, R1-Rn, R
□', R3'...Resistor, 16°18, 40.
St~Sn I, SA, SB, Sl', S2'
, SW...Switch, C9C1~C3...
...Capacitor, D1-D4...Diode.

Claims (1)

[Claims] 1. A transistor, an operational amplifier that inputs the emitter voltage and a reference voltage of the transistor and applies an output voltage to the base of the transistor, and a first transistor connected between the emitter of the transistor and a constant voltage source. a resistor, a second resistor having one end connected to the emitter of the transistor, a variable voltage source selectively applying a plurality of different voltages to the other end of the second resistor, and a variable voltage source connected to the collector of the transistor. 1. A timing circuit comprising: a capacitor having a capacitance of 100 nm, and obtaining ramp signal voltages of different slopes from both ends of the capacitor. 2. an inverting amplifier whose input terminal voltage is maintained at a substantially constant value and a capacitor connected between the input and output terminals; a first resistor connected between the input terminal of the inverting amplifier and a constant voltage source; a second resistor having one end connected to the input terminal; and a variable voltage source selectively applying a plurality of different voltages to the other end of the second resistor, the voltage flowing through the first and second resistors. A timing circuit characterized in that a sum of currents flows through the capacitor to obtain ramp wave signal voltages with different slopes from the output end of the amplifier.