JPS5952711A - Detecting circuit of displacement amount - Google Patents

Abstract

PURPOSE:To apply a slow logical element while obtaining high resolution and fast response performance by using a single carrier frequency, and to realize a small-sized system, low power consumption, and reliability improvement by providing a main interpolation part which obtains resolution (m/n)lambda by using a clock frequency (n/m)fc and a subordinate interpolation part which operates at a clock frequency nfc and divides displacement (m/n)lambda into units (1/n)lambda. CONSTITUTION:When fine displacement which is not detected by the main interpolating circuit 14, i.e. displacement corresponding to 2mum occurs and a signal SIN rises at t0, a signal SY1D falls synchronizing with a signal CK1 and a signal SY2D having time delay corresponding to one pulse of the signal CK1 also falls. A pulse generated in a period wherein the signal SY1d is at ''L'' and the signal SYSD is at ''H'' presets a counter 13 to ''1'' and the counter counts by a value which is one greater than a pulse CP generated in a period wherein the signal SY2D is at ''L'' and a signal SYIM is at ''H'', i.e. an corresponding extent when the signal SYID is referred to. In a figure, the counter 13 counts up to six at the time of the end of the pulse CP after t0 and the value is held until it is initialized at timing t1. Namely, the subordinate interpolating circuit detects actual displacement at intervals of 1mum.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is based on a phase modulation signal (hereinafter abbreviated as PM signal in Unknown A 111) corresponding to the amount of relative movement between two relatively moving objects. Carrier frequency f applied to a phase modulation displacement detection device that detects displacement. using a PM signal of (1
//n) Relates to a displacement detection circuit that obtains λ resolution.

Background Art and Problems In digital displacement detection circuits that obtain PM signals and measure displacement movements, there are various difficulties in achieving both J5 response speed and resolution. An example was to use a carrier frequency of Φ.

Now, the recording wavelength of the scale is λ, and the carrier frequency is f (
If the amount of displacement s is set as X, then the PM signal ePM is.

ePM=EPM ”' (ω.t+2πx/λ)−(1
) However, ω. =2πfc. In equation (1), the scale recording wavelength λ
If 1 resolution R is required for R, then R=λ4 (2) where n is a positive integer. Therefore, the phase change within one period of carrier frequency fc is 2
For π, engineering/. It is to obtain a resolution of "/n" for one period 'rc (= '/fC) of h + z, f. Therefore,
To obtain resolution R (=λ/n), fck=cλ/
A clock frequency of R) "fc - f3) is required.

According to equation (3), increasing the resolution R, i.e., λ/r
This shows that a high clock frequency is required to reduce t, which means that a high-speed logic element is required.

On the other hand, regarding the response speed, e PM while moving at speed VM
= El)M sin 2π(fo VM/λ)t=
EPM sin 2π (fo+Δfo)t
... It is transformed like a package). In this formula, the maximum value ΔfMAX that ΔfC can take is f. As is clear from this consideration, in order to increase the response speed ■M, f.

This indicates that it is necessary to choose a high value. Increasing f, increases the interpolation clock frequency f, in order to increase the resolution.

Not only does this make signal processing difficult, but it also makes it difficult to employ low-power logic elements such as C-M08IC and large-scale integrated circuit LSIs, making it difficult to reduce system power consumption and cost. It will be impossible to achieve this goal. Furthermore, using the carrier frequency of the decimal number has the disadvantage of complicating the circuit.

OBJECTS OF THE INVENTION An object of the present invention is to make it possible to apply low-speed logic elements while satisfying high resolution and high-speed response performance for a single carrier frequency, and to reduce the size, power consumption, and cost of the system. An object of the present invention is to provide a displacement amount detection circuit in a phase modulation type position reading device having a novel configuration, which makes it possible to improve reliability.

Summary of the Invention In order to achieve the above object, a displacement detection circuit according to the present invention uses a clock frequency of (n/m) fc to calculate (
”/n) λ main interpolator to obtain a resolution of λ, and nj
In an advantageous embodiment of the present invention, a sub-interpolation circuit is provided which operates at a clock frequency of
The sub-interpolation circuit receives the output of at least one synchronization circuit for synchronizing an asynchronous PM signal (hereinafter abbreviated as SIN signal in this specification) with a clock f0, and receives a clock ("/ m) It has a synchronization circuit for resynchronizing with fc, and for each cycle of the phase modulation signal, one resolution (1/rl) within the displacement (rr3/rl) λ section is provided.
n) Minute displacement in units of λ The gate circuit includes a gate circuit for converting the number of clock pulses into the number of clock pulses, a counter circuit for counting the output thereof, and a control circuit thereof.

EXAMPLES Below, the present invention will be explained in more detail using examples with reference to the drawings, but these are merely illustrative, and various modifications and improvements may be made without going beyond the scope of the present invention. Of course.

FIG. 1 is a block diagram showing the basic configuration of a displacement detection circuit according to the present invention.

The waveform-shaped PM signal (hereinafter abbreviated as 8 signal in this specification) is applied to the synchronization circuit l of @l,
It is synchronized with the clock frequency NFC. Next, the output of the first synchronization circuit 1 is led to the second synchronization circuit 2, and synchronization is achieved at a clock frequency of (r'm)fc. 3 is an interpolation circuit that has been used conventionally.
I/m) using a clock frequency of fc (”/n
) obtain a resolution of λ. The first synchronization circuit l and the second
2 8 signals 81+82 synchronized by the synchronization circuit 2 of
is applied to the gate circuit 4 together with the clock frequency nfc. This output indicates that the S1 signal is
) 0 to m −1 pulses are output depending on the position of the Sl signal within one cycle of f c, that is, between (''/n)λ.
By connecting the output of the gate circuit 4 to the m-ary counter 5 and simultaneously referring to the output of the interpolation circuit 3, the resolution of λ/n can be obtained. can get.

A more detailed explanation will be given below based on a specific example.

FIG. 2 is a block diagram showing the configuration of an application example suitable for combination with a system using a microcomputer or the like, and constitutes a data output type interpolation circuit. In a displacement detection system using a Magnescale, a scale wavelength λ of 200 μm is generally used. The resolution is 1 μm and the carrier frequency is f. = 501<
To realize in Hz, n2200, hence lQMHz
clock signal is required. In the example, m=10 is selected, and for example, the Sho interpolation unit described in JP-A-57-514 obtains a resolution of 10 μm, and the sub-interpolation unit according to the present invention obtains a resolution of 1 μm. .

In FIG. 2, 8 and 9 are synchronization circuits, which are synchronized by the counter signal CK1 of the asynchronous signal SIN k 10*1z. The synchronization circuit 80 output syl signal indicates at what position in the interval of the clock signal CK2 (7) applied to the main interpolation circuit, that is, the interval of 0 μm, at which the SIN signal becomes active (Low active). The falling edge is referenced. 10 is also a synchronization circuit, but it uses an I MHz clock signal C as a synchronization pulse.
K2 is used, and its output SYIM signal is CK
2 is input to the main interpolation circuit 14.

IJ is a gate circuit, and the S Y 21) signal is activated,
The period until the 8Y and M signals are activated, that is, SY
is L, and the 8 Y t M signal is interpolated into the I-1'' interval to output a CK1 signal, that is, a CP times signal.

As mentioned above, in order to detect at which position within 10 μm of one section of the CK2 signal the SIN signal is activated,
Originally, the 5YID signal should be referred to, but in order to simplify the circuit configuration, the 5Y2L) signal is used.

12 gate circuits are 4-hit binary counters]
5YtD (the next CK signal after the i signal falls)
, Outputs one pulse at the timing. At this output, counter 13 is preset to l and 8Y2D
Correct the thinned out CP pulse by reference to the signal.

FIG. 3 shows the situation when a minute displacement that cannot be detected by the main interpolation circuit 14 occurs; the T1 period is stationary;
A timing chart is shown when a displacement corresponding to two pulses of the KCK1 signal for two periods, that is, 2 μm occurs.

When the SIN signal falls at t□, the 5YtD signal falls in synchronization with the CKl signal, and the 8Y2D signal also falls with a time delay of one pulse of the CK1 signal.
Y1D signal is L''', S Y 5I-) (iji
The pulse PR to be ordered during the period of number ``H'' is preset in the counter 13Yl, and when the 5Y2D signal is L'', the pulse PR is
The counter 13 is caused to count a value that is 1 greater than the pulse CP generated during the period when the signal is ゞ■1'' in YI81, that is, the value corresponding to when referring to the 5YtD signal.In the example shown in FIG. counts 6 at the end of the CP pulse after to, and holds this value until it is initialized at the next tl timing.In the T1 period, it remains stationary, so even at timing t1, all ( A similar operation is performed, and the displacement in the T2 cycle is detected as a displacement equivalent to 2 μm since the first shift of the counter 13 after timing t2 counts 4 in the same procedure.

Next, an actual displacement detection method including a sub-interpolation circuit will be explained. As described in detail in Japanese Patent Application Laid-Open No. 57-514, the main interpolation circuit is
The amount of movement detected is output in an incremental amount data output format. Therefore, in order to measure the actual cumulative movement of the lid, it can be obtained by adding up the incremental data output for each period of the SIN signal. The resolution of the main interpolation circuit is in units of 10 μm, and if this quantization unit is even slightly exceeded, it is determined that there has been a movement of 10 μm. On the other hand, the sub-interpolation circuit absolutely represents the actual position within one section of the CK2 clock that cannot be detected by the main interpolation circuit, that is, the .mu.m section, for each period of the sIN signal. In other words, the sub-interpolation circuit detects the actual displacement in units of 1 μm, and the value of the counter 13 is the amount of movement detected by the main interpolation circuit (in units of 1 μm).
Therefore, in order to obtain the actual movement amount, the 10t1m obtained from the main interpolation circuit must be measured at the timing when it should be measured.
The value of the counter 13 of the sub-interpolation circuit (1 μ
By subtracting the value (unit: m), the cumulative amount of movement at a resolution of 1 μm can be determined.

As described in detail, the present invention provides the following effects.

1) The processing resolution can be improved without increasing the clock frequency of the main interpolation circuit.

2) Conventionally, multiple carrier frequencies have been used due to the need for response speed and resolution, but all applications can be addressed using only a single carrier frequency.

Full compatibility between systems is maintained.

3) The additional elements required by the present invention are only a few parts such as counters and flip-flops, and can be treated as additional circuits to the basic configuration used by Sasakama, and the circuits added by the present invention. The same processing format can be adopted regardless of the presence or absence of.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a displacement detection circuit according to the present invention, FIG. FIG. 3 is a timing chart of the device shown in FIG. ■...First synchronization circuit, 2...Second synchronization circuit, 3...Main interpolation circuit, 4-...Gate circuit, 5...
m-adic counter, 6...output of main interpolation circuit, 7...m
Output of decimal counter, 8 to IO...synchronization circuit, 11.
12... Gate circuit, 13... Decimal binary counter, 14... Main interpolation circuit. Patent applicant Sony Magnescale Co., Ltd. Procedural amendment 1 Indication of the case 1982 Patent application No. 164520 2 Name of the invention Displacement amount detection circuit 3 Person making the amendment Relationship with the case Patent applicant Address Name Name Sony Magnescale Scale Co., Ltd. 4 agents 〒10
5 Address: Shiba 3-chome Building 5, 3-2-14 Shiba, Minato-ku, Tokyo Subject of amendment The claims of the present application are amended as follows. (1) A displacement detection device using a phase modulation method that detects the amount of displacement based on a phase modulation signal corresponding to the amount of relative movement between two relatively moving objects is applied to phase modulation of a carrier frequency f. Using signal 7, (t
/n) In a displacement detection circuit that can obtain a resolution of λyz,
(”/m) using a clock frequency of fc 7Z
The interpolator operates at a clock frequency of nfo to obtain a resolution of (m/n)λ and a displacement (m/n)λ of (1/n).
n) A displacement detection circuit characterized by comprising a sub-interpolation circuit that divides into units of λ.

Claims (2)

[Claims] (1) Carrier frequency f applied to a phase modulation type displacement detection device that detects displacement based on a phase modulation signal corresponding to the amount of relative movement between two relatively moving objects.
For a scale of wavelength λ using a phase modulation signal of c (
In a phase shift detection circuit that obtains a resolution of (I/rl)λ, a clock frequency of (n/n)fo is used to obtain (I/rl)λ.
n) The main interpolator operates at a clock frequency of nfo to obtain a resolution of λ, and the displacement (r/r1) is
A displacement detection circuit characterized by having a sub-interpolation circuit that divides into (''/n) λ units. (2) The sub-interpolation circuit clocks the phase modulation signal f. at least one synchronization circuit for synchronizing with a clock (n/m) f; It has a synchronization circuit for re-synchronizing the phase modulation signal, and detects minute displacements in units of resolution (1/n)λ within the displacement (m/rI)λ interval for each cycle of the phase modulation signal. above nfc
2. The displacement detection circuit according to claim 1, further comprising a gate circuit for converting the number of clock pulses into a number of clock pulses, a counter circuit for counting the output thereof, and a control circuit thereof.