JPS5952467B2 - information processing system - Google Patents

information processing system

Info

Publication number
JPS5952467B2
JPS5952467B2 JP53011462A JP1146278A JPS5952467B2 JP S5952467 B2 JPS5952467 B2 JP S5952467B2 JP 53011462 A JP53011462 A JP 53011462A JP 1146278 A JP1146278 A JP 1146278A JP S5952467 B2 JPS5952467 B2 JP S5952467B2
Authority
JP
Japan
Prior art keywords
usage rate
processing device
processing
failure
information processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53011462A
Other languages
Japanese (ja)
Other versions
JPS54104752A (en
Inventor
勝 松永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53011462A priority Critical patent/JPS5952467B2/en
Publication of JPS54104752A publication Critical patent/JPS54104752A/en
Publication of JPS5952467B2 publication Critical patent/JPS5952467B2/en
Expired legal-status Critical Current

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  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)

Description

【発明の詳細な説明】 本発明は処理装置の障害部分を切離してフオールバツク
処理を行ない得る処理装置が現用と予備の複数で構成さ
れる情報処理システムに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system comprising a plurality of active and spare processing units capable of performing fallback processing by isolating a faulty part of the processing unit.

処理装置は、処理装置を構成する構成要素、例えば記憶
装置の一部、あるいはバッファ記憶装置等に障害が発生
した場合において、障害発生部分のみを切離すことによ
り、処理装置の機能低下をまねくが処理を続行すること
が出来るようになつている にのような処理をフオール
バツク処理という)。前記処理装置を複数台使用し、か
つ構成処理装置中に予備処理装置を備えているシステム
において部分障害が発生し、処理能力低下が生じた場合
の処理について述べる。処理装置に入力されるデータ量
が少なく、処理装置の使用率が少ない場合においては、
障害発生により処理装置構成要素が切離されて、処理装
置の能力低下が生じても、入力データ量が少ないため充
分データ処理を行なう事が出来る。しかしながら、処理
装置に入力されるデータ量が多く、処理装置の使用率が
高い場合においては、障害が発生し、処理能力低下を生
じている処理装置をいつまでも使用することは、未処理
データ量の増加、端末応答時間の増加が発生し、計算機
利用者に対して多大の迷惑をかけることになる。データ
発生量が多い場合に障害が発生し、処理装置の能力低下
が発生した場合においては、能力低下の生じている処理
装置をいつまでも使用するよりは、直ちに当該処理装置
による処理を停止させ、予備処理装置に切替えて処理継
続することによつて、システム全体の処理を円滑に行な
うことが出来る。
When a failure occurs in a component constituting the processing device, such as a part of the storage device or a buffer storage device, the processing device is designed to prevent functional degradation of the processing device by disconnecting only the portion where the failure has occurred. Processing that allows processing to continue is called fallback processing). A process will be described in the case where a partial failure occurs in a system that uses a plurality of the processing devices and includes a preprocessing device among the constituent processing devices, resulting in a decrease in processing capacity. When the amount of data input to the processing device is small and the usage rate of the processing device is low,
Even if a component of the processing device is separated due to the occurrence of a failure and the performance of the processing device is reduced, sufficient data processing can be performed because the amount of input data is small. However, when the amount of data input to a processing device is large and the usage rate of the processing device is high, it is difficult to continue using a processing device that has experienced a failure and reduced processing capacity due to the amount of unprocessed data. This causes an increase in the terminal response time, causing a great deal of inconvenience to computer users. If a failure occurs when a large amount of data is generated, and the performance of a processing device decreases, it is better to stop processing by the processing device immediately and make backup backups, rather than continue to use the processing device with decreased capacity. By switching to the processing device and continuing the processing, the processing of the entire system can be performed smoothly.

この発明の目的とするところは、上記の如き従来の問題
点を除去するものであり、処理装置の部分障害発生時に
おいて、処理装置使用率を監視することによりシステム
運用管理が行なえるという効果を有する情報処理装置を
提供することである。
The purpose of the present invention is to eliminate the above-mentioned conventional problems, and to achieve the effect that system operation management can be performed by monitoring the processing device usage rate when a partial failure occurs in the processing device. An object of the present invention is to provide an information processing device having the following features.

この発明の特徴とするところは、処理装置使用J率監視
装置により処理装置の使用率を測定し、使用率が一定値
以上になり、かつ処理装置のハードウェアが障害発生し
た場合に処理装置が割込を起す機構を備け、この割込信
号によりフオールバツク処理をやめ、当該処理装置の停
止、および予備・処理装置への切替処理を行なわせるこ
とである。
The feature of this invention is that the usage rate of the processing device is measured by a processing device usage rate monitoring device, and when the usage rate exceeds a certain value and a failure occurs in the hardware of the processing device, the processing device is activated. A mechanism for generating an interrupt is provided, and the interrupt signal causes the fallback processing to be stopped, the processing device to be stopped, and the processing to be switched to the backup/processing device to be performed.

次に本発明の実施例につき図面を用いて詳細に説明する
。第1図は本発明の一実施例である情報処理装置の処理
方式を示すプロツク図である。処理装置は使用率測定回
路2によつて処理装置が動作中は一定時間間隔毎の平均
使用率を常に測定する。処理装置の平均使用率を判定す
るために、時間間隔設定レジスタ3によつて指定された
時間間隔毎に、その時の平均使用率をトリガ信号11に
よつて使用率保持レジスタ4に保持する。使用率保持レ
ジスタ4に平均使用率が保持されると、使用率測定回路
2は現時点の平均使用率をりセツトし、次の時間間隔ま
での平均使用率の測定を継続する。平均使用率の測定時
間間隔は任意にプログラムにて設定出来るようにしてあ
り、プログラムにて、測定時間間隔が指定されると時間
間隔設定信号10により、時間間隔設定レジスタ3に設
定される。使用率設定レジスタ5は、プログラムによつ
てあらかじめ指定された処理装置平均使用率を保持して
いる。
Next, embodiments of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing a processing method of an information processing apparatus according to an embodiment of the present invention. The processing device constantly measures the average usage rate at regular time intervals by the usage rate measuring circuit 2 while the processing device is in operation. In order to determine the average usage rate of the processing device, the average usage rate at each time interval specified by the time interval setting register 3 is held in the usage rate holding register 4 by the trigger signal 11. When the average usage rate is held in the usage rate holding register 4, the usage rate measurement circuit 2 resets the current average usage rate and continues measuring the average usage rate up to the next time interval. The measurement time interval of the average usage rate can be arbitrarily set by the program, and when the measurement time interval is designated by the program, it is set in the time interval setting register 3 by the time interval setting signal 10. The usage rate setting register 5 holds the average usage rate of the processing device specified in advance by the program.

使用率設定レジスタ5に設定された平均使用率値は、障
害発生時における処理を判断する為の基準値として利用
される。すなわち障害発,生時に使用率設定レジスタ5
に設定された平均使用率値と障害発生時の平均使用率値
(使用率保持レジスタ4に保持されている平均使用率値
)とは、使用率比較回路6によつて比較される。使用率
比較回路6は使用率保持レジスタ4の値2が使用率設定
レジスタ5より大きい場合にのみ信号16が出るように
なつている。使用率比較回路6からの信号16は障害発
生時に発生する障害発生信号17と共に決定回路7に入
れられ、決定回路7により停止割込信号18が出される
The average usage rate value set in the usage rate setting register 5 is used as a reference value for determining processing when a failure occurs. In other words, when a failure occurs, the usage rate setting register 5
The average usage rate value set in 1 and the average usage rate value at the time of failure occurrence (the average usage rate value held in the usage rate holding register 4) are compared by the usage rate comparison circuit 6. The usage rate comparison circuit 6 is designed to output a signal 16 only when the value 2 of the usage rate holding register 4 is larger than the usage rate setting register 5. The signal 16 from the usage rate comparison circuit 6 is input to the decision circuit 7 together with a fault occurrence signal 17 generated when a fault occurs, and the decision circuit 7 issues a stop interrupt signal 18.

停止割込信号18が発生すると当該処理装置は停止処理
を行なうと共に、予備処理装置の起動処理を行なう。障
害発生信号17は、処理装置内に障害が発生し、処理装
置の一部機能停止を行なう必要が生じた場合にのみ有効
になる信号であり、一時的な障害の時には有効とはなら
ない以上述べた如き処理方式であるので本発明にあつて
は次の如き効果を得ることが出来る。
When the stop interrupt signal 18 is generated, the processing device performs a stop process and also starts a preprocessing device. The failure occurrence signal 17 is a signal that becomes valid only when a failure occurs in the processing device and it becomes necessary to stop some functions of the processing device, and does not become valid in the case of a temporary failure. Since the processing method is as follows, the following effects can be obtained in the present invention.

(1)処理装置障害発生時における処理装置の使用率を
監視することにより処理装置の使用率が設定値よりも高
い場合においては、当該処理装置の処理を停止し、予備
処理装置に切替えて処理出来るので、システム全体のデ
ータ処理量の減少、端末応答時間の悪化を防ぐ事が出来
る。
(1) By monitoring the usage rate of a processing device when a processing device failure occurs, if the usage rate of the processing device is higher than the set value, the processing of the processing device is stopped and processing is switched to the backup processing device. As a result, it is possible to prevent a reduction in the amount of data processed by the entire system and a deterioration in terminal response time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す情報処理装置の処理方
式を示すプロツク図である。 1・・・・・・使用率監視装置、2・・・・・・使用率
測定回路、3・・・・・・時間間隔設定レジスタ、4・
・・・・・使用率保持レジスタ、5・・・・・・使用率
設定レジスタ、6・・・・・・使用率比較回路、7・・
・・・・決定回路、10・・・・・・時間間隔設定信号
、11・・・・・・トリガ信号、12・・・・・・使用
率設定信号、17・・・・・・障害発生信号、18・・
・・・・停止割込信号。
FIG. 1 is a block diagram showing a processing method of an information processing apparatus according to an embodiment of the present invention. 1... Usage rate monitoring device, 2... Usage rate measuring circuit, 3... Time interval setting register, 4...
...Usage rate holding register, 5...Usage rate setting register, 6...Usage rate comparison circuit, 7...
...Decision circuit, 10...Time interval setting signal, 11...Trigger signal, 12...Usage rate setting signal, 17...Failure occurrence Signal, 18...
...Stop interrupt signal.

Claims (1)

【特許請求の範囲】[Claims] 1 処理装置障害時該障害処理装置に代わつて処理を行
なう予備処理装置を含む複数の処理装置で構成され、各
処理装置は障害部分を切離してフオールバツク処理が可
能に構成された情報処理システムにおいて、これら処理
装置の使用率を測定する使用率測定手段と、該使用率測
定手段から得られる使用率が予め設定される使用率に達
していない場合の障害ではフオールバツク処理を行なわ
しめ、予め設定される使用率を超えている場合の障害で
は障害処理装置を予備処理装置に切替える手段とを具備
したことを特徴とする情報処理システム。
1. In an information processing system configured with a plurality of processing devices including a preliminary processing device that performs processing in place of the faulty processing device in the event of a processing device failure, each processing device is configured to be able to perform fallback processing by separating the faulty part, There is a usage rate measuring means for measuring the usage rate of these processing devices, and if the usage rate obtained from the usage rate measuring means does not reach the preset usage rate, fallback processing is performed and the preset usage rate is set. An information processing system comprising means for switching a failure processing device to a backup processing device in the event of a failure when the usage rate is exceeded.
JP53011462A 1978-02-06 1978-02-06 information processing system Expired JPS5952467B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53011462A JPS5952467B2 (en) 1978-02-06 1978-02-06 information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53011462A JPS5952467B2 (en) 1978-02-06 1978-02-06 information processing system

Publications (2)

Publication Number Publication Date
JPS54104752A JPS54104752A (en) 1979-08-17
JPS5952467B2 true JPS5952467B2 (en) 1984-12-19

Family

ID=11778751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53011462A Expired JPS5952467B2 (en) 1978-02-06 1978-02-06 information processing system

Country Status (1)

Country Link
JP (1) JPS5952467B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6139895A (en) * 1984-07-30 1986-02-26 Matsushita Electric Ind Co Ltd Controller or induction motor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6139895A (en) * 1984-07-30 1986-02-26 Matsushita Electric Ind Co Ltd Controller or induction motor

Also Published As

Publication number Publication date
JPS54104752A (en) 1979-08-17

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