JPS59501139A - Fused platinum silicide fuse and Schottky diode and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] fused silicided platinum fuse and Background of the invention of Schottky diode and its manufacturing method 1. Field of invention TECHNICAL FIELD This invention relates to integrated circuits, and more particularly, to a method useful for programming integrated circuits. and 1-z.

26 prior art In programmable read-only memory (FROM), various materials are They are melted or "blown" to print integrated circuit devices. program. Such materials include nickel-chromium alloys (chromium), polysilicon Contains silicides of metals that are difficult to dissolve.

Also, as part of the device's circuit, FROM consists of semiconductors on which integrated circuits are formed. A Schottky diode is typically formed by a metal contact to the body substrate. Typical.

Two patents disclosing platinum silicide fuses and Schottky diode devices Issued to Liam El Price (WilliamIiL, Pr1ce) and assigned to the assignee of this application. The first patent was issued on August 16, 1977. A US patent named ``Silicided Platinum Fuse Links for Integrated Circuit Devices'' was developed. No. 4.042,950, the second of which was issued on January 23, 1979. Published ``Method for manufacturing platinum silicide fuse links for integrated circuit devices'' No. 4,135.295. These patents apply to silicon substrates. A method and structure for making a platinum silicide fuse is disclosed above. finally made One end of the exposed platinum silicide fuse is connected to the integrated circuit by a first metal interconnect line. connected to other parts of the road. The other end of the fuse is sealed by a metal interconnect line. connected to a Schottky diode, the lower lightly doped Schottky diode formed by a platinum silicide contact with the substrate.

The metal interconnect required between the fuse and the Schottky diode presents two problems. occurs. The first is to set fuse sensor 1 (fuse and Schottky diode). This means that there is a limit to how small the area required for measurement can be made.

Second, the manufacturing steps required to metallize a Schottky diode are This means that the forward and reverse electrical characteristics of This is true for metallization Even if Yong covers the Schottky and forms a field plate around the diode, It happens even in good cases.

Schottky diode fuse array smells during fuse programming All shots other than those associated with fuses to be programmed Reverse Schottky leakage is important because the diodes are reverse biased.

The current leaked by a reverse-biased Schottky diode is is lost from the current available to program the current. to large-scale FROM In the case of This results in large array current leakage. To avoid reducing programming yield These leakages need to be compensated for. This requires an increase in peripheral circuits. , thus increasing the die size, which is an undesirable result.

This invention represents a significant improvement over the prior art.

Summary of the invention This invention combines a platinum silicide fuse and a Schottky diode, thereby resulting in a more compact configuration with improved reverse electrical characteristics. In addition, the fused In various embodiments of used and Schottky diodes, various forward electrical It is possible to select structures with properties.

The present invention provides a method for incorporating fuses into integrated circuits formed on the surface of a semiconductor substrate. and a Schottky diode device, the device having an aperture on the substrate surface. and a silicon layer on the surface of the insulating layer and the opening, a silicon layer is defined and in contact with a first portion on the insulating layer and through the opening; a second portion in contact with the plate, the device having substantially the same shape as the silicon layer; further comprising a silicided metal layer on the silicon layer having a The first portion of the metal silicide layer on the first portion of the contact layer has a preselected electrical potential. The system has a cross-sectional dimension that opens when a voltage larger than the voltage is applied. A second portion of the silicided metal layer on the second portion of the silicon layer is together with a silicon layer. to form a Schottky diode. Polysilicon is used as the silicon layer material, and the silicon The Schottky diode contacts the silicided metal layer and its polysilicon material within the aperture area. formed by.

The reverse electrical breakdown characteristic of the formed Schottky diode is determined by the insulating layer. Field play of the Schottky diode from a second region on the periphery of the aperture. a third portion extending onto said insulating layer having a silicided metal layer thereon serving as a silicide layer; Significant improvements can be made by having the silicon layer with .

Brief description of the drawing The invention will be clearly understood from the following detailed description taken in conjunction with the drawings.

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the device shown in FIG. 1 along line A-A.

3A, 3B, 3C, and 3D illustrate the manufacture of the apparatus shown in FIG. The various stages in the process for FIG. 4 is a plan view of another embodiment of the invention.

FIG. 5 is a cross-sectional view of FIG. 4 along line B-8.

FIG. 6 is a circuit representation of the device of FIG.

FIG. 7 is a cross-sectional view of another embodiment in which a laser heating step is used.

FIG. 8 is a sectional view of still another embodiment of the invention.

Figures 9A and 9B illustrate problems with prior art Schottky diodes.

detailed description Figure 1 shows a plan view of a device that combines a silicide fuse and a Schottky diode. It is shown. This fusion amorphous structure, typically formed on a silicon semiconductor substrate, , having a general shape similar to that of an integrated circuit interconnect line. less equipment Tomo IIIA has a small cross-sectional shape that concentrates high current and melts the fuse. It must be done. This is the narrowed portion 20 in FIG. rX The second part 21 marked J indicates the area of the Schottky diode. Third Figures A, 3B, 3C and 3D are for manufacturing the apparatus shown in Figure 1. Some stages of the case are shown.

FIG. 3A shows the preparatory manufacturing steps for producing selectively grown thick field oxide. Indicates the floor. The substrate 10 is covered with a preliminary silicon oxide layer 11A, and the nitride layer 15 is Locate the desired contact area by known masking and etching techniques It is decided. The substrate 10 is placed in an oxidizing atmosphere so that the unadded portions have the desired thickness. grow up. The nitride layer 15 is then stripped away, leaving a thin oxide layer underneath. is removed. Figure 3B shows this situation.

At this stage, instead of simply growing field oxide? Quickly contact us Openings may be etched where areas are needed.

The substrate 10 with the contact openings and the overlying oxide layer 11 are then separated by approximately 1000 It is completely covered by a layer of polysilicon 12 of on-gestorm thickness. layer 1 2 is an interconnection line of an integrated circuit with a narrowed portion 20 and a contact area 21; The shape shown in Figure 1, which has a general shape similar to that of the defined by etching. The '43C diagram shows the specifications for polycrystalline silicon 12. This shows the layer that has been removed.

The entire substrate 10 with polysilicon layer 12 and insulating layer 11 preferably has a thickness of about 400 It is completely covered by an angstrom thick platinum layer 16. The standard technique is , by sputtering platinum onto the surface. Figure 3D is coated with platinum. This shows the equipment used. Following this, a platinum layer 16 and a polysilicon layer ] 2 It is heated and sintered at a temperature between 600°C and 600°C. During the sintering process, the polysilicon content The layer 12 and the layer 16 of platinum molecules are diffused into each other to form the polysilicon layer 12 and the layer 16 of platinum molecules. A silicided platinum layer is formed to replace the platinum layer 16 and has a qualitatively identical shape.

The silicon atoms diffused throughout the platinum layer 16 are oxidized to form platinum silicide. Forms a protective oxide on top. This oxide forms easily in the absence of excess silicon. polysilicon layer 12 is supplied with excess silicon over platinum. In addition, it must be thicker than the platinum layer 16. Sintering of platinum layer 16 In the areas that are not covered, the platinum is etched but protected with silicon dioxide and silicified. It is removed by immersing the entire substrate 10 in a solution of aqua regia that does not affect platinum. It will be done. The silicon dioxide covering the platinum silicide can be chemically or sputtered edge treated. The device must then be metallized in a masking process. and patterned to form the desired interconnections. fuse and schottky The metal lines from the diode fuse cell to the rest of the integrated circuit are made of titanium. It is formed by a double layer of gsten alloy 18 and aluminum 17. Titanium - Tungsten layer 18 is used to maintain the integrity of aluminum 117 , if the aluminum layer 17 is interposed with TiWQ! Silicification if there was no t18 Reacts with the material layer')3. The resulting device is shown in FIGS. 1 and 2. ing.

The notable features and effects of polysilicon covered Schottky diodes are: 7 Applications of Prior Art Uncovered Schottky Diodes This is best illustrated by comparing it to Shion. Figure 9A shows an unsintered shot. FIG. Intervening polysilicon l as described above The platinum layer is placed in direct contact with the silicon substrate 10 without any 1i12 . Sintering occurs between the substrate and the platinum layer, and the unsintered platinum material is etched with aqua regia. A defined platinum silicide layer 40 is formed after being removed in a processing step. layer 41 is a protective silicon dioxide layer on top of the platinum silicide layer 40.

An oxide layer present on top of the platinum silicide layer 40 for clean contact with the metal During the etching step to remove 41, field oxide layer 11, especially silicided A small amount of oxide (200 to 400 angstroms) is also deposited around the material layer 40. removed. The resulting exposure around the platinum silicide Schottky contact layer 40 The silicon region 42 is a depletion region for platinum silicide Schottky. form part of. Further, in this area, the exposed silicon substrate 10 is exposed to the shot. to the metal line 43 connecting the diode to the pt3i fuse (not shown). Therefore, when contacted in region 42, the platinum silicide Schottky diode and Allows for an arrangement of electrically parallel second Schottky diodes. metal line 43 does not represent a dual metal layer of TiW and A1 as described above.

exposed depletion region or in parallel with the platinum silicide Schottky diode. Due to the effect of having a surrounding Schottky diode, the measured electrical characteristics Sexuality is damaged. The oxide layer 11 tapers more gently toward the contact region. or as the ratio of the surrounding area to the Schottky contact area increases. As the temperature increases, the characteristics deteriorate more rapidly. Using tapered oxide contacts in this way For example, in selective oxidation, these effects can reduce the Schottky dye. Aether is severely degraded in quality.

In a polysilicon-covered Schottky diode device, a thin oxide region is protected by a layer of polysilicon and platinum silicide, and the device is There is no loss of quality in between. Furthermore, the platinum silicide layer on the thin oxide region Forms an excellent field plate against Schottky. The equipment shown in Figure 1 The position has very good reverse leakage. The forward voltage has no peripheral components, but Increased by the thickness of the polysilicon remaining in the platinum silicide layer.

Another embodiment of the invention includes two parallel Schottky dies with different operating characteristics. It is a silicified platinum fuse fused with aether. Figures 4 and 5 show this example. shows. Unlike the problematic Schottky diodes of the prior art, these two parallel The Schottky diode is a conscious design. This device is The silicide layer 13 as a layer, the underlying polysilicon layer 12 and the constricted portion, etc. and two contact areas 22 and 23.

The contact region 22 is made of a polysilicon-based semiconductor diode similar to that described above. form a circle. In contrast, platinum silicide layer 13 is in contact with single crystal substrate 10 in region 23. do. This makes it more efficient compared to Schottky diodes based on polysilicon. More standard metal silicide/single crystal silicon shot with normal PtSi'* voltage ]・A kid diode is formed.

FIG. 6 represents a schematic circuit diagram of this fused structure. Fuse 30 is a contour Schottky diodes representing different Schottky diodes in the open region 22.23 Corresponds to the constriction region 20 in FIGS. 4 and 5 with odes 32 and 33 do. This structure provides a typical platinum silicide forward voltage at low currents and Improved reverse leakage of condensed Schottky diodes is possible.

In the manufacturing process for the construction of this device, the steps shown in FIG. The exposed polycrystalline layer 12 does not completely cover the exposed substrate 10 but only partially. will be changed so that Metal layer 16 is then sputtered directly onto substrate 10. completely covering the underlying structure. By sintering, The area of metal layer 16 near the contact at the substrate is connected to the substrate rather than to polycrystalline layer 12. 10, causing more silicon interdiffusion.

Yet another embodiment of the invention is shown in FIG.

This iI4 structure is shown in Figure 3C with no special steps added before or after the steps shown. It is achieved by doing things. Polycrystalline layer 12 is exposed to laser light and thereby The area of the polycrystalline layer 12 is recrystallized. This recrystallized region 12 is the seventh It is shown as region 14 in the figure. Subsequent processing proceeds as described above. do. The resulting structure is in contact with monocrystalline silicon, an extension of the substrate 10. It comprises a Schottky diode with a silicide layer in contact with it, thereby making it possible to A Schottky diode with the forward operating characteristics of a recon while maintaining improved inverse properties due to the lack of exposed oxide edges surrounding It is formed.

FIG. 8 shows yet another structure of the invention, in which a platinum silicide fuse is used. is fused with a single crystal Schottky diode. In this case, the oxide 19 A thin layer (approximately 300 angstroms) of cover. A polycrystalline layer 12 overlies a thin oxide layer 19 and an underlying substrate. It is specified that there is no contact with 10. The metal silicide layer 13 is formed as described above. and defined, the contact with the substrate 10 forms a Schottky diode. .

This structure provides an unimpaired platinum silicide forward voltage and also allows for platinum silicide on thin oxide Provides improved reverse leakage due to field plate effect. In this structure, many Thin oxide thickness for reliable crystal-to-single silicon contact The thickness of platinum is required to be 1.5 times as large as the thickness of the platinum.

To fabricate this particular structure, the exposure of the substrate 10 shown in FIG. The ejected part is oxidized again to form a thin oxide layer on it, or , the thin oxide layer 11A under the nitride layer 15 is simply left unremoved. Next, The silicon layer 12 is masked and etched so as not to completely cover the contact area. Defined by tuching. Use the specified policy and control as a mask. The underlying thin oxide is etched away, as shown in Figure 8. Leaving polysilicon layer 12 and thin oxide layer 19 as shown. platinum metallai The oxidation and sintering steps are performed as described above.

The invention has been particularly shown and described with reference to preferred embodiments. format and changes in details may be made without departing from the spirit of the invention. This will be easily understood by those skilled in the art. Accordingly, the appended claims It is intended that exclusivity be granted to the invention as limited only by the enclosing text herein.

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Claims (1)

[Claims] 1. Fused fuses connected to integrated circuits formed on the surface of semiconductor substrates and a Schottky diode device, an insulating layer provided on the surface of the substrate and having a frontage, the insulating layer and the opening; a silicon layer disposed on the top surface, the silicon layer forming interconnections of the integrated circuit; the first portion formed as a connecting line and passing through the first portion on the insulating layer and the opening; a second portion of contact with the substrate, having a substantially identical shape to the silicon layer; further comprising a silicided metal layer disposed on the silicon layer having a A first portion of the silicided metal layer on the first portion of the silicon layer is preselected. It has a cross-sectional dimension that opens when a voltage greater than the applied voltage is applied. , a second portion of the metal silicide layer on the second portion of the silicon layer is The fused fuse and shield form a Schottky diode with the conductor layer. Schottky diode device. 2. The device according to claim 1, wherein the silicon layer includes a polysilicon material. Place. 3. The silicon layer extends from the second portion on the periphery of the insulating layer opening to the insulating layer. a third portion extending over the layer, said third portion having said gold silicide ff1 thereon; layer, thereby improving the breakdown characteristics of the Schottky diode. 3. The apparatus of claim 2, wherein: 4. The silicided metal layer is deposited on the shaped polycrystalline layer and is difficult to dissolve. sintering a layer of metal with said polycrystalline layer and unsintered portions of said metal layer; 4. The device of claim 3, formed by removing. 5. The device according to claim 4, wherein the hard to dissolve metal includes platinum. 6. The metal silicide layer is in contact with the substrate through the opening, and 3. A device according to claim 2, wherein a second Schottky diode is thus formed. . 7. The metal silicide layer is a molten metal layer deposited on the shaped polysilicon layer. by sintering a layer of metal, and the unsintered portion of said metal layer; is formed by removing the metal layer, and the metal layer is in contact with the substrate. an extension from the metal layer on the second portion of the polycrystalline layer; A metal layer is formed on the polysilicon layer and the base in contact with the polysilicon layer. 7. Apparatus according to claim 6, sintering together with the plate. 8. The apparatus according to claim 7, wherein the hardly soluble metal includes platinum. 9. The device of claim 1, wherein the silicon layer comprises a single crystal material. 10. The silicon layer is for contacting the insulating layer and the substrate. a polycrystalline silicon layer deposited over the opening, the polycrystalline layer being exposed to laser light; at least the second portion of the polycrystalline layer in contact with the substrate Claim 911, wherein the silicided metal layer is recrystallized into single crystal silicon. A layer of refractory metal deposited on the shaped silicon layer is sintered and the Claim formed by removing unsintered portions of the metal layer Apparatus according to clause 10. 12. The silicon layer extends from the second portion on the periphery of the insulating layer opening to the insulating layer. a third portion extending over the layer, the third portion having the metal silicide layer over the layer; , thereby improving the breakdown characteristics of the Schottky diode. , the apparatus according to claim 11. 13. The device according to claim 11, wherein the hardly soluble metal includes platinum. 14. Integrated circuits formed on the surface of a semiconductor substrate and a Schottky diode device, an insulating layer having an opening provided on the surface of the substrate; and a G block provided on the insulating layer. a polycrystalline silicon layer, the polycrystalline silicon layer being an interconnect of the integrated circuit. a first portion shaped as a connecting line and constricted and a first portion around said opening; Leaving part 2, gold silicide provided on the polycrystalline layer having substantially the same shape as the polycrystalline layer; further comprising a metal layer, thereby forming a polycrystalline layer on the constricted first portion of the polycrystalline layer. The first portion of the metal silicide layer is energized by applying a voltage higher than a preselected voltage. a front surface on the second portion of the polycrystalline layer; A second portion of the silicided metal layer extends beyond the periphery and is in contact with the substrate. , whereby a Schottky diode is formed with said substrate. Fuse and Schottky diode devices. 15. A portion of the insulating layer below the second portion of the polycrystalline layer is Claim 1, which is thinner than a portion of said insulating layer under said narrowed first portion of The device according to item 4. 16. The silicided metal layer is a refractory layer deposited on the shaped polycrystalline layer. by sintering a thin metal layer and removing the unsintered portion of said metal layer. the metal layer is formed by removing the metal layer before contacting the substrate. leaving a portion extending from the metal layer on the second portion of the polycrystalline layer; is the polysilicon layer and the substrate in contact with the polysilicon layer; 16. The apparatus of claim 15, wherein the apparatus is sintered in a single layer. 17. The device according to claim 16, wherein the hardly soluble metal includes platinum. 18. Fuse and Schottky diode devices integrated in integrated circuits A method for manufacturing a semiconductor substrate, the method comprising: forming an insulating layer having an opening on a semiconductor substrate; and depositing a silicon layer over the insulating layer and the shrine opening; The silicon layer is masked 6 and etched to reduce the constriction of the insulating layer. and a second part that makes contact with the board through the above 10. shaping the integrated circuit into interconnect lines; and depositing a layer of a less soluble metal on the layer, the metal layer being The shaped silicon has a predetermined thickness that is thinner than the thickness of the silicon layer. The refractory metal layer is sintered with the silicon layer to form a layer substantially identical to the silicon layer. forming a silicided metal layer having a shape, the thickness of the metal layer is determined in relation to the thickness of the silicon layer so that the silicon layer remains after sintering. A method of manufacturing a fused fuse and Schottky diode device. 196 The step of forming the silicon layer includes forming the silicon layer into the insulating layer opening. a third portion extending from the second portion of the silicon layer on the periphery of the silicon layer onto the insulating layer; The steps of scrubbing and etching the silicon layer are roughly explained. 19. The method of claim '18. 20. The silicon layer includes polycrystalline silicon, and the melting method. 21, generally comprising the step of heating the silicon layer with a laser; at least the second portion of the silicon layer is recrystallized into a single crystal material by 20. The method of claim 19, wherein: