JPS5950100B2 - 三重拡散論理エレメント - Google Patents

三重拡散論理エレメント

Info

Publication number
JPS5950100B2
JPS5950100B2 JP50078543A JP7854375A JPS5950100B2 JP S5950100 B2 JPS5950100 B2 JP S5950100B2 JP 50078543 A JP50078543 A JP 50078543A JP 7854375 A JP7854375 A JP 7854375A JP S5950100 B2 JPS5950100 B2 JP S5950100B2
Authority
JP
Japan
Prior art keywords
region
regions
semiconductor
type
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50078543A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5119984A (en:Method
Inventor
エ− タツシ パトリツク
ケ− ラツセル ルイス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signetics Corp
Original Assignee
Signetics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp filed Critical Signetics Corp
Publication of JPS5119984A publication Critical patent/JPS5119984A/ja
Publication of JPS5950100B2 publication Critical patent/JPS5950100B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/615—Combinations of vertical BJTs and one or more of resistors or capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/641—Combinations of only vertical BJTs
    • H10D84/643—Combinations of non-inverted vertical BJTs and inverted vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic
    • H10D84/652—Integrated injection logic using vertical injector structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP50078543A 1974-07-15 1975-06-24 三重拡散論理エレメント Expired JPS5950100B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/488,754 US4005470A (en) 1974-07-15 1974-07-15 Triple diffused logic elements
US488754 1983-04-26

Publications (2)

Publication Number Publication Date
JPS5119984A JPS5119984A (en:Method) 1976-02-17
JPS5950100B2 true JPS5950100B2 (ja) 1984-12-06

Family

ID=23940988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50078543A Expired JPS5950100B2 (ja) 1974-07-15 1975-06-24 三重拡散論理エレメント

Country Status (6)

Country Link
US (1) US4005470A (en:Method)
JP (1) JPS5950100B2 (en:Method)
CA (1) CA1033848A (en:Method)
DE (1) DE2531367A1 (en:Method)
GB (1) GB1474826A (en:Method)
NL (1) NL7508387A (en:Method)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4153487A (en) * 1974-12-27 1979-05-08 Tokyo Shibaura Electric Co., Ltd. Method of manufacturing intergrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
US4151019A (en) * 1974-12-27 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
US4097888A (en) * 1975-10-15 1978-06-27 Signetics Corporation High density collector-up structure
US4144098A (en) * 1977-04-28 1979-03-13 Hughes Aircraft Company P+ Buried layer for I2 L isolation by ion implantation
JPS5998557A (ja) * 1982-11-27 1984-06-06 Nissan Motor Co Ltd Ｍｏｓトランジスタ
EP0111977B1 (en) * 1982-12-20 1989-04-05 Koninklijke Philips Electronics N.V. Integrated circuit and method
US4567644A (en) * 1982-12-20 1986-02-04 Signetics Corporation Method of making triple diffused ISL structure
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten
US6551869B1 (en) * 2000-06-09 2003-04-22 Motorola, Inc. Lateral PNP and method of manufacture
US7598521B2 (en) * 2004-03-29 2009-10-06 Sanyo Electric Co., Ltd. Semiconductor device in which the emitter resistance is reduced

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3356860A (en) * 1964-05-08 1967-12-05 Gen Micro Electronics Inc Memory device employing plurality of minority-carrier storage effect transistors interposed between plurality of transistors for electrical isolation
US3414783A (en) * 1966-03-14 1968-12-03 Westinghouse Electric Corp Electronic apparatus for high speed transistor switching
US3564443A (en) * 1966-06-29 1971-02-16 Hitachi Ltd Semiconductor integrated circuit device containing lateral and planar transistor in a semiconductor layer
GB1304591A (en:Method) * 1970-02-18 1973-01-24

Also Published As

Publication number Publication date
GB1474826A (en) 1977-05-25
DE2531367A1 (de) 1976-02-05
CA1033848A (en) 1978-06-27
DE2531367C2 (en:Method) 1987-09-17
JPS5119984A (en:Method) 1976-02-17
NL7508387A (nl) 1976-01-19
US4005470A (en) 1977-01-25

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