JPS5948930A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5948930A
JPS5948930A JP57159787A JP15978782A JPS5948930A JP S5948930 A JPS5948930 A JP S5948930A JP 57159787 A JP57159787 A JP 57159787A JP 15978782 A JP15978782 A JP 15978782A JP S5948930 A JPS5948930 A JP S5948930A
Authority
JP
Japan
Prior art keywords
groove
wafer
grooves
glass film
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57159787A
Other languages
Japanese (ja)
Inventor
Kazuhisa Wada
和田　一久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP57159787A priority Critical patent/JPS5948930A/en
Publication of JPS5948930A publication Critical patent/JPS5948930A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

PURPOSE:To avoid the generation of warpage even when the thickness of a semiconductor wafer is thin by previously forming a groove, which is similar to the groove of the surface of the semiconductor wafer in a plane shape but is displaced in the direction, to the back when the groove is bored to the surface and a glass passivation film is buried in the groove. CONSTITUTION:A P type layer 2 is diffused and formed to the N type Si wafer 1 to generate a PN junction 3, the grooves 4 penetrating the junction 3 from the surface of the layer 2 are formed, and the inner surfaces of the grooves are coated with the first glass films 5 for passivation. The grooves 14, which are similar to the grooves 4 but the direction thereof is displaced from the grooves 4, are also formed to the surface, in which there is no layer 2, of the wafer 1 at the same time as the films 5 are formed, and the surfaces of the grooves 14 are also coated with glass films 15. The surfaces of the layers 2 and the backs of the wafer 1 are each coated with electrodes 6 and 7, and the unnecessitated films 15 are removed by using a fluorine group etching liquid. Accordingly, the generation of warpage is prevented even when the wafer is thin, and the thickness of the wafer is reduced.

Description

【発明の詳細な説明】 本発明は半導体装置のガラスパシベーション膜形成方法
の改良に係り、特にシリコン半導体ベレットを金篇ステ
ムに接着する原生じる歪を低減した信頼性の高い半導体
装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for forming a glass passivation film for a semiconductor device, and more particularly to a method for manufacturing a highly reliable semiconductor device by reducing the strain caused by bonding a silicon semiconductor pellet to a gold braid stem. .

ガラスパシベーションとは、半導体ヘレットノ側面に露
出するＰＮ接合面をガンス被膜で覆う表面処理の一方法
である。この場合、一般には半導体ウェーハに少なくと
も２つ以上の異なる導電型の領域を形成し、このウエー
ノ・から複数の半導体装置を得るべく各素子間を分離す
るようにＰＮ接合面を貫通する溝を形成し、この溝の内
壁に露出するＰＮ接合面をガラスセ被覆し、前記溝の中
央部を分断して各別の半導体ペレツ１１こ分割する。Glass passivation is a surface treatment method for covering the PN junction surface exposed on the side surface of a semiconductor with a Gans coating. In this case, generally at least two or more regions of different conductivity types are formed on the semiconductor wafer, and grooves are formed that penetrate the PN junction surface to separate each element in order to obtain a plurality of semiconductor devices from this wafer. Then, the PN junction surface exposed on the inner wall of this groove is coated with glass, and the groove is divided at the center to separate each semiconductor pellet into 11 pieces.

このようなガラスパシベーション技術（こよると、有機
物を使用した表面処理に比べて耐熱性、耐湿性の向上が
図れ、また組立工程の著しい合理化が可能であること等
から多くの技術が開発されている。Many technologies have been developed such as this glass passivation technology, which improves heat resistance and moisture resistance compared to surface treatments using organic materials, and allows for significant streamlining of the assembly process. There is.

このような背景において、ウエーノ１つのベレットの収
得率が高く、かつ組立工程の自動化の容易なベレット構
造としで、第１図に示すガラスでパシベーションされた
ダイオード等がある。In this background, there is a diode passivated with glass as shown in FIG. 1, which has a pellet structure that has a high yield of one pellet and can easily automate the assembly process.

すなわち、Ｎ形のシリコン半導体ウェーノー１と、その
主面全面にＰ形不純物を拡散しで形成したＰ形層２との
間にＰＮ−ｊＨ合３を形成し、Ｐ形層２の表面からＰＮ
接合３に充分到達する溝４を酸化膜などをマスクしたシ
リコンの化学エツチング等の手段によって形成する。つ
いで、この溝４に電気泳動法、沈澱法などの方法によっ
て粉末ガラスを充填した後に、酸素ガスもしくは酸素・
窒素の混合ガス中で焼成し、ガラス皮膜５をＰＭ接合面
端縁を覆うように形成する。こうしてガラスノくシベー
ション工程を完了したシリコンウェーハ・の両面にそれ
ぞれ電極６および７を形成した後に、ダイシング工程を
行うことにより第２図に示すような個々のベレット８に
分割し、このベレット８を金属ステム９にソルダ１０を
介しで接着する。この時、ベレットにはガラス皮膜５と
シリコンとの熱膨張の差により応力が生じている。また
、ベレット８は金属スチーム９にソルダ１０を介してマ
ウントされでいるので、金属ステムとベレットの熱膨張
差により大きな応力を受ける。このためベレット搭載時
にあるいはそのあと行なわれると一トサイクル試験や実
稼動時の熱履歴によってガラスに割れが発生したり、シ
リコ／に亀裂が生じたりするため、耐圧歩留の著しい低
下や信頼性の著しい劣化が起きる。このためガラスでパ
シベーションされたベレットは、比較的安価で熱膨張係
数の大きい銅等の金属ステムにマウントすることは問題
があった。That is, a PN-jH mixture 3 is formed between an N-type silicon semiconductor wafer 1 and a P-type layer 2 formed by diffusing P-type impurities over the entire main surface thereof, and a PN-jH mixture is formed from the surface of the P-type layer 2.
A groove 4 sufficiently reaching the junction 3 is formed by means such as chemical etching of silicon using an oxide film or the like as a mask. Next, after filling this groove 4 with powdered glass by a method such as electrophoresis or precipitation, the groove 4 is filled with oxygen gas or oxygen gas.
Firing is performed in a nitrogen gas mixture to form a glass film 5 covering the edge of the PM bonding surface. After forming electrodes 6 and 7 on both sides of the silicon wafer that has undergone the glass oxidation process, a dicing process is performed to divide it into individual pellets 8 as shown in FIG. It is bonded to the metal stem 9 via a solder 10. At this time, stress is generated in the pellet due to the difference in thermal expansion between the glass film 5 and silicon. Furthermore, since the beret 8 is mounted on the metal steam 9 via the solder 10, it is subjected to a large stress due to the difference in thermal expansion between the metal stem and the belet. For this reason, if it is carried out during or after loading the pellet, the glass may crack or silicone may crack due to the thermal history during one-cycle testing or actual operation, resulting in a significant drop in pressure yield and reliability. Significant deterioration occurs. For this reason, it is problematic to mount a glass passivated pellet on a metal stem made of copper or the like, which is relatively inexpensive and has a large coefficient of thermal expansion.

従来、このマウント工程の歪の低減のためには、第１の
方法としてステムとベレットの間にモリブデン板やタニ
グステン板などの熱膨張係数が比較的シリコンに近いも
のを中間拐としでマウントする方法あるいは第２の方法
として、ソルダに半田合金などのンフトソルダを用いソ
ルダで歪を緩和する方法がとられていた。しかし、第１
の方法は工程が繁雑になり材料費が力１さみコスト高に
なるという欠点があり、第２の方法には熱放散やソルダ
の熱疲労に問題があった。Conventionally, in order to reduce distortion in this mounting process, the first method is to mount a material with a coefficient of thermal expansion relatively close to that of silicon, such as a molybdenum plate or a tanigsten plate, as an intermediate between the stem and the pellet. Alternatively, a second method is to use a soft solder such as a solder alloy as the solder and to alleviate the strain with the solder. However, the first
The method (1) has the disadvantage that the process is complicated and the cost of materials increases, while the second method has problems with heat dissipation and thermal fatigue of the solder.

ちなみに、第３図ζこ示すようにガラスパシベーション
を施した面の反対側の面にも同様な加工を施すことによ
って、半導体基体のそりを相殺して平担ならしめ、その
後の工程における不都合を６解消する方法が示されてい
る。しかしながらこの方法に、よれば、同図に示すよう
にガラス５とシリコンとの熱膨張差により生ずる歪は改
善されるものの、ベレット１１と金属ステム９との熱膨
張差により生ずる歪に対してはいｔ　ｆ、にお十分では
なく、むしろウェーハのそりを相殺する手段として設け
られた裏面の溝１２が、ガラス皮膜５を形成した主面の
溝４と略対称位置にあることに起因して、ベレツ）１１
を樹脂封止した際、エポキシ系の封止樹脂１３の熱膨張
係数がベレット１１を形成す度上昇により熱膨張を起こ
したとき、ベレット１１を上方へ曲げようとする応力が
加わり、異なる導電型の領域からなる接合部分にもれ電
流の増加をもたらす々いう問題があった。更に上述した
ように、シリコンウェーハの両面から深い溝が略対称的
に形成されることから、使用するウェーハの工程中の機
械的強度を保つためにウェーハを必要以上ζこ厚くする
ことが余儀なくされでいた。By the way, as shown in Figure 3, by applying the same processing to the opposite side of the glass passivated side, the warpage of the semiconductor substrate can be offset and flattened, thereby eliminating any inconvenience in subsequent processes. 6. A method for solving this problem is shown. However, according to this method, as shown in the figure, although the distortion caused by the difference in thermal expansion between the glass 5 and silicon is improved, the distortion caused by the difference in thermal expansion between the pellet 11 and the metal stem 9 can be improved. tf, but rather because the grooves 12 on the back surface, which are provided as a means to offset the warpage of the wafer, are located at approximately symmetrical positions with the grooves 4 on the main surface on which the glass film 5 is formed. Berets) 11
When the epoxy-based sealing resin 13 increases in thermal expansion as the pellet 11 is formed, stress is applied that tends to bend the pellet 11 upwards, causing a difference in conductivity type. There is a problem in that the leakage current increases in the junction area consisting of the area. Furthermore, as mentioned above, since deep grooves are formed almost symmetrically from both sides of the silicon wafer, it is necessary to make the wafer thicker than necessary in order to maintain the mechanical strength of the wafer used during the process. It was.

本発明はこのような点に鑑みなされたものであり、ガラ
スパシベーション膜を形成する第１の溝を有する半導体
ウェーハの主面とは反対０ＩＩＩの面に、第１の溝と平
面形状で相似するがウエーノ・の面の方向においてずれ
た第２の溝を設け、この溝の内而に第１のガラス皮膜の
形成によって上記半導体ウェーハに生ずべきそりを防止
するようなガラス。The present invention has been made in view of these points, and the present invention has been made in the surface of 0III opposite to the main surface of a semiconductor wafer having a first groove for forming a glass passivation film, which is similar in planar shape to the first groove. A second groove is provided which is deviated in the direction of the surface of the wafer, and a first glass film is formed inside the groove to prevent warping that would otherwise occur in the semiconductor wafer.

皮膜を形成することを特徴とする。この結果ウェーハの
そりを防いで平担ならしめることができもまたこのウェ
ーハをペレットに分割して金属ステムに固着する際、ペ
レットのステム側に位置するガラス被膜が除去された第
２の溝ζこて、ベレットと金属ステム間における実効接
着面積が小さくなるとともに、この溝が緩衝手段として
の効果をともなうため、接着部における応力の集中が低
減され、もってガラスの割れシリコンの亀裂を防止した
信頼性の高い半導体装置が得られる。It is characterized by forming a film. As a result, the wafer can be flattened without warping, and when the wafer is divided into pellets and fixed to a metal stem, the second groove ζ where the glass coating located on the stem side of the pellet is removed is used. The effective adhesive area between the trowel, the pellet and the metal stem becomes smaller, and this groove also acts as a buffer, reducing the stress concentration at the adhesive part, thereby preventing glass cracking and silicone cracking. A semiconductor device with high performance can be obtained.

第４図（ａ）乃至（Ｃ）はそれぞれこの発明の方法によ
る一実施例として、ダイオードを例にとってその各段階
における状態を説明する断面図である。FIGS. 4(a) to 4(c) are cross-sectional views illustrating the state of a diode at each stage as an example of the method of the present invention.

まず第１図で説明したと陣］様に、Ｎ形シリコン牛導体
ウェーハ１の主面にＰ形層２を拡散形成して１３　Ｎ接
合３をつくり、Ｐ形層２の表面力１らＰＮ接合３を貫通
するｇ４を形成した後この溝４の内面にパシベーション
用の第１のガラス皮膜５を形成のしかしウエーノ・］の
面の方向においてずれた第２の４１４を設け、その内面
にガラス皮膜１５を形成する〔第４図（ａ）〕。この場
合、第２の溝１４の幅および深さは、ウエーノ・１に生
ずるそりを考照したうえでシリコンとガラスとの特性の
兼ね谷いに２いて任意に形成すればよく、また第２のガ
ラス皮膜１５の材質についてはパシベーション効果を有
する必要はないため、この実施例では第１のガラス皮膜
５と異なる材質でありながら熱膨張泳数の近似したガラ
スを用いている。First, as explained in FIG. After forming g4 that penetrates the joint 3, a first glass film 5 for passivation is formed on the inner surface of this groove 4. However, a second glass film 414 is provided which is shifted in the direction of the surface of the groove 4, and a glass film is formed on the inner surface of the groove 4. A film 15 is formed [FIG. 4(a)]. In this case, the width and depth of the second groove 14 may be arbitrarily formed based on the characteristics of silicon and glass, taking into consideration the warpage that occurs in the wafer 1, and the width and depth of the second groove 14. Since the material of the glass film 15 does not need to have a passivation effect, in this embodiment, a glass having a thermal expansion coefficient similar to that of the first glass film 5 is used although it is made of a different material.

このようにして、ガラスパシベーション工程を光子した
シリコンウエーノ・１の主面にあたるＰ形層の狭面と表
面にあたるＮ形Ｉ４との表面にそれぞれ電極６および７
を形成した後に、ウエーノ・のルふ而におけるもはや不
要となったガラス皮膜１５を、他の部分をホトレジスト
で保護した上でフッ累系のガラスエツチング液で光合に
味去する〔第４図（ｂ）〕。７ま２、この実施例では、
ウエーノ・の裏面に形成される電極７は、第２の溝１４
以外の全面に形成されているが、本発明は特にこれに限
定されるものではなく、例えば第１の溝４に対向する部
分１６、すなわち実質的に電流が流れない部分には、電
極７を形成しなくても良い。すなわち本発明者の実験に
よれば、金属ステムとの間で実質的に電流が流れるＮ形
シリコンの幅ａは、ウェーハの厚みｂの約半分以上あれ
ば、性能的にも変わりなく、マた機械的にも耐えられる
ことが確かめられている。これは逆に言えは、後述する
ところの溝をずらして設けたことにともなう、ウエーノ
・の厚みをおさえかつ機械的強度を保つ本発明の効果を
裏付けるものである。In this way, the electrodes 6 and 7 are formed on the narrow surface of the P-type layer, which is the main surface of the silicon wafer 1, and the N-type layer I4, which is the front surface, of the silicon wafer 1 that has undergone the glass passivation process.
After forming the glass film 15, which is no longer necessary, the other parts are protected with a photoresist and then removed with a fluorine-based glass etching solution (see Fig. 4). b)]. 7.2 In this example,
The electrode 7 formed on the back surface of the wafer is connected to the second groove 14.
However, the present invention is not particularly limited to this. For example, the electrode 7 is formed on the portion 16 facing the first groove 4, that is, the portion where no current substantially flows. It doesn't have to be formed. In other words, according to the inventor's experiments, if the width a of the N-type silicon through which current flows between the metal stem and the metal stem is approximately half or more of the wafer thickness b, there will be no change in performance and the material will remain the same. It has been confirmed that it is mechanically durable. On the contrary, this confirms the effect of the present invention in suppressing the thickness of the wafer and maintaining mechanical strength due to the staggered arrangement of the grooves, which will be described later.

次にダイシング工程て−は、第２のガラス皮膜１５が除
去された第２の溝１４を位置決め手段として積極的に利
用することによって個々のペレットに分割する〔第４図
（Ｃ）〕。すなわちウエーノ・ｌの両面にそれぞれ設け
られた第１のＩｖ１１４と第２の溝】４は互いに規則的
に設けられているので、第２の溝１４を位置決め手段と
して第１の溝に対応する部分にウェー・・１の裏面から
切り込み１７を入れ、ウエーノ・１を第１の溝に沿って
弁開することによって個々のベレットに分割することが
できる。これは、ガラス皮膜５が形成された第１の溝４
から切断機の刃を入れていた従来の方法に比べ、ガラス
皮膜にクラックが生じない、切断機の刃の目づ才りが起
こりにくく寿命が長＜　７’ａ’る等の効果がある。Next, in the dicing step, the second groove 14 from which the second glass film 15 has been removed is actively used as a positioning means to divide the pellet into individual pellets [FIG. 4(C)]. In other words, since the first Iv 114 and the second grooves 4 provided on both sides of Ueno-l are regularly provided with respect to each other, the portions corresponding to the first grooves are positioned using the second grooves 14 as positioning means. By making a cut 17 from the back side of the wafer 1 and opening the wafer 1 along the first groove, the wafer 1 can be divided into individual pellets. This is the first groove 4 in which the glass film 5 is formed.
Compared to the conventional method in which the cutting machine blade is inserted from scratch, there are advantages such as no cracking of the glass film, less chance of warping of the cutting machine blade, and a longer life span.

次に、このようにして得られた半導体ベレットを第５図
に示すように、金属ステム９にンルダ１０を介して接着
した場合について説明する。上述したように、金属ステ
ム９は通常銅を用いることが多い力％ｉｉｌの熱膨張係
数は半導体ペレット１８を構成するシリコンよりも大き
い大きいため、この熱膨張差により例えば電極はんだ何
時には大きな歪を生じている。しかしながら本発明によ
れば、金属ステム９側に設けられた第２の溝１４は、第
１の溝４と対向しない位置に設けられているため、ベレ
ット１８と金属ステム９間における実効接着面積を小さ
くするとともにこの溝は緩衝手段としての効果をともな
うため、上記熱膨張差により接着部における応力の集中
が低減される。これは本発明４）特徴とするところであ
り、この第２の溝１４の構成は、シリコンウェーハの厚
みを必敦最小限におさえることにも寄与している。更に
この第２の溝１４は、金属ステム搭載時ｔこ半田クレー
ム中に残り装置に支障をきたす窒隙やフラッフの追し出
しとしての付随効果も有する。更に韮た、この溝１４を
囲むようにして構成された周辺部１９は、ステムへの搭
載時ペレットの補強手段として作用するため、本発明と
の相乗効果が期待される。Next, a case will be described in which the semiconductor pellet thus obtained is adhered to a metal stem 9 via a binder 10, as shown in FIG. As mentioned above, the metal stem 9 is usually made of copper.The thermal expansion coefficient of the metal stem 9 is larger than that of silicon constituting the semiconductor pellet 18, so this difference in thermal expansion causes large strain when soldering electrodes, for example. It is occurring. However, according to the present invention, since the second groove 14 provided on the metal stem 9 side is provided at a position that does not face the first groove 4, the effective adhesive area between the bellet 18 and the metal stem 9 is reduced. In addition to being small, this groove also has the effect of acting as a buffer means, so that the concentration of stress at the bonded portion is reduced due to the above-mentioned difference in thermal expansion. This is a feature of the present invention (4), and the configuration of the second groove 14 also contributes to minimizing the thickness of the silicon wafer. Furthermore, this second groove 14 also has the additional effect of removing nitrogen gaps and fluff that may remain during solder cracking when a metal stem is mounted and cause trouble to the device. Furthermore, since the peripheral portion 19 configured to surround the groove 14 acts as a reinforcing means for the pellet when it is mounted on the stem, a synergistic effect with the present invention is expected.

紀６図（ａ）は、第５図にて説明した第２の溝１４を平
面的ｌこ見た形状を示す下面図であり、この実施例では
溝１４を弁状に設けていることが理解されよう。同図（
１））乃至（ｄ）は本発明の変形例を示すものであり、
ぞの目的及び効果は前述した内容と何ら変わるものでは
なく、その要旨とするところは、第１の溝に対向しない
位置に第２の溝２０．２１．２２を設けたところにある
。同図（ｂ）及び（ｄ）の構成は、前述した本発明の詳
細な説明から容易に理解されると思イつれる力Ｓ１同図
（Ｃ）の・構成はその効果にヤや特異性を有するので説
明を加えておく。Fig. 6 (a) is a bottom view showing the shape of the second groove 14 seen from above in a plane as explained in Fig. 5, and in this embodiment, the groove 14 is provided in a valve shape. be understood. Same figure (
1)) to (d) show modified examples of the present invention,
The purpose and effect of this arrangement are the same as those described above, and the gist thereof is that the second grooves 20, 21, and 22 are provided at positions that do not face the first grooves. The configurations in (b) and (d) of the same figure have a force S1 that can be easily understood from the detailed explanation of the present invention described above. , so I will add an explanation.

すなイつち第６図（Ｃ）の構成は、第２の溝として細い
格子状の溝２１を設けた点を％徴として、Ｉ５す、はん
だ付は面積が分割されることにより実効はんだ付けされ
る面積が小さくなるため、電流のυｉ１．れる量を考厘
する必要力Ｓあるが、ペレットを金属ステムに搭載する
際生じる歪は著しく低減されると共に、半田中の気孔の
押し出し効果も向上する。In other words, the configuration shown in FIG. 6(C) has a thin grid-like groove 21 as the second groove, and the effective soldering is achieved by dividing the area. Since the attached area becomes smaller, the current υi1. Although there is a necessary force S to account for the amount of pores in the solder, the strain that occurs when the pellets are mounted on the metal stem is significantly reduced, and the effect of pushing out the pores in the solder is also improved.

更に溝数が多くかつ細いため、溝が比較的浅くなりウェ
ーハの厚みを押さえることが可能となる。Furthermore, since the number of grooves is large and narrow, the grooves are relatively shallow, making it possible to suppress the thickness of the wafer.

なおこの場合でも、Ｍ２の溝を第１の溝と実質的（こ均
一に設けることにより、その清に形成されるがガラス皮
膜の条件を略同−とし、ｍｌのガラス皮膜を形成したこ
とに伴うウェー・・のそりを防ぐことが肝要である。In this case as well, by providing the M2 groove substantially uniformly with the first groove, the glass film can be formed more clearly, but the conditions for the glass film were set to be approximately the same, and a glass film of ml was formed. It is important to prevent the accompanying warping of the wafer.

以上の説明力）ら明らかなように、本発明によれば従来
半導体ウェーハのそりを防ぐために設けられる第２の溝
を、第１の溝と対向しない位置に実質的に第１の溝と均
一に設けるこさにより、半導体ペレットを金属ステムｌ
こ接着する際生じる歪を低減すると共に、その構成力）
ら生じるさまざまな効果も相俟って従来では成し得なか
った顕著な効果をＢＨするものである。As is clear from the above explanation, according to the present invention, the second groove, which is conventionally provided to prevent warpage of a semiconductor wafer, is placed substantially evenly with the first groove at a position not facing the first groove. The semiconductor pellet is attached to the metal stem by the stiffness provided in the
This reduces the strain that occurs when bonding, and also improves its structural strength)
Together with the various effects produced by this method, BH achieves remarkable effects that could not be achieved in the past.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図は従来方法を説明するためのシリコン
ウェーハの断面図、及びそのペレットのステム搭載状態
を示すルｌｌ１ｆｉｉ′図、第３図は他の従来方法を説
明するためのシリコンペレットのステム搭載状態を示す
断Ｕｆ−′１図、第４図（ａ）乃至（Ｃ）はそれぞれこ
の発明の方法の一実施例の各段階における状態を示す断
面図、第５図は本発明の一実施例によるペレットのステ
ム搭載状態を示す断面図、第６図（ａ）乃至（ｄ）は本
発明の詳細な説明するための一実施例及び変形例を示す
ペレットの下面図である。 １：シリコン半導体ウェーハ、４．：第１の溝、５：第
１のガラス皮膜、６，７：電極、９：金属ステム、１０
：ソルダ、１４．２０．２１．２２゜：第２の清、１５
：第２のガラス皮膜、１８：半導体ベレット。 才　１　閏 ’４’　　２　　口 ＋３　閃 才４閃Figures 1 and 2 are a cross-sectional view of a silicon wafer for explaining a conventional method, and a diagram showing a state in which the pellets are mounted on a stem, and Figure 3 is a silicon pellet for explaining another conventional method. 4(a) to (C) are sectional views showing the state at each stage of an embodiment of the method of the present invention, and FIG. 5 is a cross-sectional view showing the state in which the stem is mounted. A sectional view showing a pellet mounted on a stem according to an embodiment, and FIGS. 6(a) to 6(d) are bottom views of pellets showing an embodiment and a modified example for explaining the present invention in detail. 1: Silicon semiconductor wafer, 4. : first groove, 5: first glass film, 6, 7: electrode, 9: metal stem, 10
: Solder, 14.20.21.22゜: Second Qing, 15
: second glass film, 18: semiconductor pellet. Sai 1 Leap '4' 2 Mouth+3 Ingenious 4 Ingenious

Claims (1)

【特許請求の範囲】 １）ＰＮ接合を持った半導体ウェーハの主面に、状が相
似するがウェーハの面の方向においてずれた第２の溝を
設け、上記第ｌの溝の内面にパシベーション用の第１の
ガラス皮膜を形成するとともに、上記第２の溝の内面に
第１のガラス皮膜の形成によって上記半導体ウェーハに
生ずべきそりを防止するような第２のガラス皮膜を形成
し、上記半導体ウェーハに所要の加工を施した後に上記
第２のガラス皮膜を除去し、上記Ｍ１のガラス皮膜が形
成された第１のｒ４１こ沿つて上記半導体ウェーハを個
々の半導体装置に分割することを特徴とする半導体装置
の製造方法。 ２、特許請求の範囲第１項記載のものにおいて、第２の
ガラス皮膜が除去された第２の溝を位置決め手段として
半導体ウェーハの裏面から切り込みを入れること（こよ
り、該ウェーハを第１の溝に沿って骨間し個々の半導体
装置に分割することを特徴さす、る半導体装置の製造方
法。 ３）特許請求の範囲第１項記載のものにおいて、第２の
溝に形成される第２のガラス皮膜は、第１のガラス皮膜
と熱膨張係数が略同−であることを特徴とする半導体装
置の製造方法。 ４）特許請求の範囲第１項記載のものｌこおいで、実質
的に第１の溝と均一に設けられた第２の溝は格子状であ
ることを特徴とする半導体装置の製造方法。[Claims] 1) A second groove having a similar shape but shifted in the direction of the wafer surface is provided on the main surface of a semiconductor wafer having a PN junction, and a second groove is provided on the inner surface of the first groove for passivation. a first glass film is formed on the inner surface of the second groove, and a second glass film is formed on the inner surface of the second groove to prevent warping that would otherwise occur in the semiconductor wafer due to the formation of the first glass film; After performing the required processing on the semiconductor wafer, the second glass film is removed, and the semiconductor wafer is divided into individual semiconductor devices along the first r41 on which the M1 glass film is formed. A method for manufacturing a semiconductor device. 2. In the device described in claim 1, an incision is made from the back surface of the semiconductor wafer using the second groove from which the second glass film has been removed as a positioning means (thereby, the wafer is placed in the first groove). 3) A method for manufacturing a semiconductor device, characterized in that the semiconductor device is divided into individual semiconductor devices along the interbone. 3) In the semiconductor device according to claim 1, the second groove formed in the second A method of manufacturing a semiconductor device, wherein the glass film has substantially the same coefficient of thermal expansion as the first glass film. 4) A method of manufacturing a semiconductor device according to claim 1, characterized in that the second groove provided substantially uniformly with the first groove has a lattice shape.
JP57159787A 1982-09-14 1982-09-14 Manufacture of semiconductor device Pending JPS5948930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57159787A JPS5948930A (en) 1982-09-14 1982-09-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57159787A JPS5948930A (en) 1982-09-14 1982-09-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5948930A true JPS5948930A (en) 1984-03-21

Family

ID=15701256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57159787A Pending JPS5948930A (en) 1982-09-14 1982-09-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5948930A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63259022A (en) * 1987-04-15 1988-10-26 Nkk Corp Manufacture of high-mn nonmagnetic steel excellent in stability of magnetic permeability

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63259022A (en) * 1987-04-15 1988-10-26 Nkk Corp Manufacture of high-mn nonmagnetic steel excellent in stability of magnetic permeability
JPH0579727B2 (en) * 1987-04-15 1993-11-04 Nippon Kokan Kk

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