JPS5948563B2 - automatic gain adjustment device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain adjustment device used in communication equipment such as radio receivers and television receivers.

In general, radio receivers, television receivers, etc. that have automatic gain adjustment devices are already known, but those with conventional structures have extremely complicated circuit configurations and require a great deal of work to adjust the gain. Furthermore, there were drawbacks such as the high cost of the entire device.

Therefore, the present invention connects the connection point between the collector of the automatic gain adjustment transistor and the anode of the diode via a coupling capacitor to the input terminal of the high frequency amplification transistor constituting the signal amplification circuit, and connects the cathode of the diode to the negative power supply. An AG that changes in accordance with the input voltage of the received signal is connected to the base of the automatic gain adjustment transistor and the base of the intermediate frequency amplification transistor in the previous stage constituting the signal amplification circuit.
C voltage is applied, and the emitter of the automatic gain adjustment transistor, the base of the frequency conversion transistor constituting the signal amplification circuit, and the base of the subsequent intermediate frequency amplification transistor are connected between the positive power supply and the negative power supply. A potential at a connection point between a resistor and a diode in a series circuit of a resistor and a diode is applied as a bias power supply, and the AGC voltage turns on the automatic gain adjustment transistor and the diode when the received signal is input, and By configuring the voltage of the bias power supply to be reduced when the input of
- An object of the present invention is to provide an automatic gain adjustment device which can eliminate the conventional drawbacks, widen the automatic gain adjustment range to a much wider range than conventional devices, and significantly improve performance. It is.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. FIG. 1 is an electric circuit diagram of an automatic gain adjustment device according to the present invention.
In the figure, 1 is an output terminal for taking out a low frequency signal, 2 is a negative power terminal, and 3 is a positive power terminal.

Further, A is an antenna, and after the signal from this antenna A is tuned by an input tuning circuit L1, it is applied to the gate of a field effect transistor (hereinafter simply referred to as FET) Ql,
Here, the high frequency signal is amplified and applied from the drain of the FET Q1 to the frequency conversion transistor Q3 via the tuning circuit L2.

Here, a crystal oscillation circuit is constituted by the crystal oscillator X1, the transistor Q3, and the oscillation coil L3, and the input frequency and the crystal oscillation frequency are frequency-converted and used as an intermediate frequency in the next stage intermediate frequency transformer (hereinafter simply referred to as IFT). Transistor Q for intermediate frequency amplification taken out from R4
4, further tuned by the next stage IFTL5, and further amplified by the intermediate frequency amplification transistor Q,
Detected from IFTL6 by detection diode D2,
It is taken out from terminal 1 as a low frequency signal via coupling capacitor C0.

Resistor R6 is connected to diode D3. This is for biasing D4, which provides a stable voltage to frequency conversion transistor Q3 and intermediate frequency amplification transistor Q4.
, C5 as the base bias current.

The resistor R6 is a detection load resistor, and a DC voltage is generated at both ends thereof according to the signal input.

When there is no signal, the potential at the connection point between the detection diode D2 and the load resistor R6 is the same as the potential at the connection point between the detection diode D2 and the load resistor R6. It is the same as the bias power supply by D4, and when a signal is input, it gradually decreases according to the input.

The voltage that changes according to the input signal in this way is connected to the resistor R4.
The signal is then supplied to an intermediate frequency amplification transistor Q4 and an automatic gain adjustment transistor Q2 via a filter formed by a capacitor C7.

Resistors R1, R2, R3 are transistors Qa s C4r
It is the emitter resistance that determines the current of Q5.

In addition, capacitors C4, C, and C6 are connected to each transistor Q.
3 pQ4 is a bypass capacitor for C5.

Furthermore, capacitors C1, C2, C3, and C1o are bypass capacitors.

The emitter of the automatic gain adjustment transistor Q2 is a diode D3. D, connected to the bias line t by
The collector of the transistor Q2 is connected to the negative line or terminal 2 via a diode D1.

A connection point P between the collector and diode D1 of the transistor Q2 is connected to the gate of the FET Ql via a capacitor C3.

Now, when a signal is applied to antenna A, this signal is applied to each transistor Q1. Amplified by Qs, C4, and C5, I
The signal reaches the detection diode D2 from the FTL6, and is detected by this diode D2.

This detection output DC voltage is applied to the diode D3. It is lower than the bias voltage due to D-.

Since the detection output DC voltage of the intermediate frequency amplifying transistor Q4 decreases, the base bias becomes shallower, the collector current decreases, and the amplification degree decreases.

On the other hand, the base bias of the automatic gain adjustment transistor Q2 becomes deeper, and what was previously non-conductive becomes conductive, and a collector current of the automatic gain adjustment transistor Q2 flows, and a current also flows through the diode D1.

When current flows through both the transistor Q2 and the diode D1 and they become conductive, the internal impedance of both decreases, and the resonant impedance of the input tuning circuit L1 decreases under equal constraints. Prevent excessive input from being applied.

However, when the input signal becomes larger, the detection output DC voltage also decreases further, and the automatic gain adjustment transistor Q
A large amount of collector current will also flow.

Then, resistor R6 and diode D3. In the bias line t composed of diodes D4, the voltage drop across the resistor R3 becomes large due to the current flowing through the automatic gain adjustment transistor Q2, and the voltage drop across the resistor R3 increases. The current flowing through D decreases.

Therefore, diode D3. If the operating point of D is set at a point where the current is relatively small, when current flows through the automatic gain adjustment transistor Q2 at the time of a large input signal, the voltage of the bias line t will also drop, and the current of all transistors will decrease. is reduced, and it is possible to prevent distortion, etc., from occurring due to excessive input.

This situation will be explained using an experimental example.

A 6 volt power supply is applied between terminals 2 and 3, and two diodes D3. If the current characteristics with respect to the voltage of D4 are as shown in Figure 2, if the resistor R6 is set to 4.7 Ω, the diode D3
．． The current ■ flowing through D is expressed by the following equation.

In this way, the operating point indicated by point a in FIG. 2 is set.

And transistor Q2 for automatic gain adjustment at the time of large input signal.
The collector current of is 0.5 mA.

Diode D3. The current flowing through D4 decreases to 0.5 mA, the operating point in FIG. 2 moves to point b, and the bias voltage decreases from 1.2 volts to 1.05 volts.

This decrease in bias voltage causes the amplification degree of each transistor to decrease, thereby preventing the occurrence of distortion.

Figure 3 is a drawing showing the distortion characteristics for the input signal, and the characteristic C
is the characteristic when the transistor Q2, diode D1 and capacitor C3 are removed (characteristics of the conventional configuration),
The input signal begins to distort at 50 decibels.

In addition, characteristic d is obtained by experimentally using other diodes to power the automatic gain adjustment transistor Q2 and diode D.
This is when the voltages of diodes D3 and D4 do not change when a signal is input, and the input signal begins to be distorted from 90 decibels.

Characteristic e is based on the present invention, and the input signal can be amplified up to 105 decibels without distortion.

FIG. 4 is a partial electric circuit diagram showing a modified structure of the above embodiment. Even if a resistor R7 shown in the figure is used in place of the diode D40, substantially the same effects as in the previous embodiment can be achieved.

Note that in FIG. 4, the same parts as in FIG. 1 are given the same numbers and detailed explanation thereof will be omitted.

As detailed above, the present invention connects the connection point between the automatic gain adjustment transistor Q correct and the anode of the diode to the input terminal of the high frequency amplification transistor constituting the signal amplification circuit via the coupling capacitor, and connects the connection point between the automatic gain adjustment transistor Q correct and the anode of the diode, and The cathode of is connected to a negative power supply, and the detected output is applied to the base of the automatic gain adjustment transistor and the base of the intermediate frequency amplification transistor in the previous stage constituting the signal amplification circuit according to the input voltage of the received signal. A changing AGC voltage is applied to the emitter of the automatic gain adjustment transistor, the base of the frequency conversion transistor constituting the signal amplification circuit, and the base of the subsequent intermediate frequency amplification transistor between the positive power supply and the negative power supply. Applying a potential at a connection point between a resistor and a diode in a series circuit of a connected resistor and a diode as a bias power source, and turning on the automatic gain adjustment transistor and the diode at the time of inputting the received signal by the AGC voltage; In addition, since the bias power supply is configured to reduce the electrical power required when the received signal is overinput, the automatic gain adjustment range can be widened, and the number of parts can be reduced compared to the conventional device. It has various excellent advantages, such as being able to drastically reduce the amount of gas, reduce costs, and significantly improve performance.

In the above embodiment, the connection point P is connected to the input tuning circuit L1, but the above-mentioned effects can be achieved even if the connection point P is connected to any signal amplification circuit from the antenna input terminal to the intermediate frequency amplifier. Needless to say, you can get it.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram of an automatic gain adjustment device according to the present invention,
Figure 2 is a characteristic diagram of the diode used in the bias line t, Figure 3 is a distortion characteristic diagram for the input signal from the antenna,
FIG. 4 is a partial electrical circuit diagram showing a modification of FIG. 1. Q2...Transistor for dynamic gain adjustment, Dl...
P... diode, P... connection point, Ll...
...Input tuning circuit, l...Bias line, D3. D4...Diode, 1, 2, 3.
...Terminal.

Claims (1)

[Claims] 1. Connecting the connection point between the collector of the automatic gain adjustment transistor and the anode of the diode via a coupling capacitor to the input terminal of a high-frequency amplification transistor constituting a signal amplification circuit, and connecting the cathode of the diode to a negative power supply, An AGC voltage that changes according to the input voltage of the received signal obtained by smoothing the detection output is applied to the base of the automatic gain adjustment transistor and the base of the intermediate frequency amplification transistor in the previous stage constituting the signal amplification circuit, and the automatic gain is adjusted. A resistor in a series circuit of a resistor and a diode connected between the positive power supply and the negative power supply to the emitter of the adjustment transistor, the base of the frequency conversion transistor constituting the signal amplification circuit, and the base of the subsequent intermediate frequency amplification transistor. A potential at a connection point with the diode is applied as a bias power supply, the AGC voltage turns on the automatic gain adjustment transistor and the diode when the reception signal is input, and the voltage of the bias power supply is turned on when the reception signal is input excessively. An automatic gain adjustment device characterized in that it is configured to be small.