JPS5947390B2 - MIS memory sense circuit - Google Patents
MIS memory sense circuitInfo
- Publication number
- JPS5947390B2 JPS5947390B2 JP52038870A JP3887077A JPS5947390B2 JP S5947390 B2 JPS5947390 B2 JP S5947390B2 JP 52038870 A JP52038870 A JP 52038870A JP 3887077 A JP3887077 A JP 3887077A JP S5947390 B2 JPS5947390 B2 JP S5947390B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- sense circuit
- voltage
- circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Manipulation Of Pulses (AREA)
- Static Random-Access Memory (AREA)
Description
【発明の詳細な説明】
この発明は絶縁ゲート形電界効果トランジスタ（以下Ｍ
ＩＳＦＥＴという）を使用したメモリＩＣのセンス回路
に関するものである。Detailed Description of the Invention This invention relates to an insulated gate field effect transistor (hereinafter M
The present invention relates to a sense circuit for a memory IC using an ISFET.
ＭＩＳメモリの記憶データをビット線を通して読み出す
場合、負荷容量の大きいビット線の論理振幅を小さくお
さえて、読み出し速度の向上をはかることが切望される
。When reading data stored in a MIS memory through a bit line, it is desired to improve the read speed by keeping the logic amplitude of the bit line, which has a large load capacitance, small.
この場合センス回路として、ソース接地形増幅回路とし
て知られるゲート入力形の回路のかわりに第１図のよう
な負荷ＭＩＳＦＥＴＱＬとドライバ用ＭＩＳＦＥＴＱＤ
Ｉ）値列接続され、更にドライバ用ＭＩＳＦＥＴＱＤの
ゲートが定電圧源ＶＧに接続されたゲート接地形増幅回
路として知られるソース入力形の回路を用いることによ
つで、ビット線のハイレベルをドライバ用ＭＩＳＦＥＴ
ＱＤのスレシユホールド電圧程度か、またはそれ以下に
することが可能である。第１図の回路の入力電圧対出力
電圧の関係を第３図に示す。ところが第１図の回路では
入力端子１が開放されたとき、負荷ＭＩＳＦＥＴＱＬ及
びドライバ用ＭＩＳＦＥＴＱＤを流れる電流通路がなく
、出力端子２の電圧は負荷ＭＩＳＦＥＴＱ、のみによつ
て決まるハイレベルに、また入力端子１の電圧はドライ
バ用ＭＩＳＦＥＴＱＤのゲート電圧からこのＦＥＴのス
レシユホールド電圧だけ低いレベルになるため、結局動
作点は第３図の入力特性のＡ点に落ち着き、低レベルの
入力が印加されてから出力が低レベルになるまでの時間
が長くなる。この発明の目的は高速動作可能なＭＩＳＦ
ＥＴを用いたセンス回路を提供ことにある。In this case, the sense circuit uses a load MISFETQL and a driver MISFETQD as shown in Figure 1 instead of a gate input type circuit known as a grounded source amplifier circuit.
I) Drive the high level of the bit line by using a source input type circuit known as a grounded gate amplifier circuit, which is connected to the value column and further has the gate of the driver MISFET QD connected to the constant voltage source VG. MISFET for
It is possible to make it about the threshold voltage of QD or lower. The relationship between the input voltage and the output voltage of the circuit of FIG. 1 is shown in FIG. However, in the circuit of Fig. 1, when input terminal 1 is opened, there is no current path flowing through load MISFETQL and driver MISFETQD, and the voltage at output terminal 2 is at a high level determined only by load MISFETQ, and the input terminal The voltage at point 1 becomes a level lower than the gate voltage of driver MISFET QD by the threshold voltage of this FET, so the operating point eventually settles at point A of the input characteristics in Figure 3, and after a low level input is applied. It takes longer for the output to reach a low level. The purpose of this invention is to provide MISF that can operate at high speed.
An object of the present invention is to provide a sense circuit using ET.
この発明によればゲートを定電圧源に接続し、ソースを
入力端子、ドレインを出力端子にそれぞれ接続したドラ
イバ用ＭＯＳＦＥＴＱＤと、前記ドライバ用 ＭＩＳＦ
ＥＴＱＤのドレインと電源の高電位線（ＶＤＤ）とを結
合する負荷素子ＱＬと前記ドライバ用ＭＩＳＦＥＴＱＤ
のソースと共通線（ＧＮＤ）とを結合する定電流性素子
Ｑｃとを含むセンス回路が得られる。According to the present invention, there is provided a driver MOSFET QD whose gate is connected to a constant voltage source, whose source is connected to an input terminal, and whose drain is connected to an output terminal, and the driver MOSFET QD.
A load element QL that connects the drain of the ETQD and the high potential line (VDD) of the power supply, and the MISFETQD for the driver.
A sense circuit is obtained that includes a constant current element Qc that connects the source of and a common line (GND).
この発明のセンス回路では入力端子の開放時でも定電流
性素子Ｑｃ、負荷素子ＱＬ及びドライバ用ＭＩＳＦＥＴ
ＱＤによる電流通路が形成されるため入力端子及び出力
端子の電圧を、それぞれの電圧振幅のハイレベルとロー
レベルの中間の値に保つことができる。In the sense circuit of this invention, even when the input terminal is open, the constant current element Qc, the load element QL, and the driver MISFET
Since a current path is formed by the QD, the voltages at the input terminal and the output terminal can be maintained at a value intermediate between the high level and low level of the respective voltage amplitudes.
この場合入力が印加され、出力がハイレベルまたはロー
レベルになるまでの時間は電圧変動幅が、入力側、出力
側共に従来の回路の半分程度で済み、また動作点付近の
増幅度も大きくなることから、従来の回路よりも大幅に
短縮される。In this case, the time from when the input is applied to when the output becomes high or low level, the voltage fluctuation width is only about half that of conventional circuits on both the input and output sides, and the amplification near the operating point is also large. Therefore, it is much shorter than conventional circuits.
次にこの発明の実施例につき、図を用いて説明する。Next, embodiments of the present invention will be described with reference to the drawings.
第２図はこの発明の一実施例を示す回路図であり、Ｎチ
ャネルＭＩＳＩＣの構成を取つたもので、負荷素子ＱＬ
及び定電流性素子Ｑ。FIG. 2 is a circuit diagram showing one embodiment of the present invention, which has an N-channel MISIC configuration, and has a load element QL.
and constant current element Q.
としてスレシユホールド電圧ＶＴが−３Ｖ程度のデイプ
リ・シヨン形ＭＩＳＦＥＴを用い、ドライバ用ＭＩＳＦ
ＥＴＱＯとしてスレツシユホールド電圧Ｖ１が＋１Ｖ程
度のエンハンスメント型ＭＩＳＦＥＴを用いている。電
源電圧（００）を＋５Ｖ、入力電圧範囲を＋０．２から
１．５とした場合、それぞれのＭＩＳＦＥＴＱＬとＱ。
．！１１．Ｑ０の寸法（チヤンネル幅／チヤンネル長）
の比は３：２００：ｌに設定するのが好ましい。第２図
に示した実施例の入出力特性は第１図の回路と同じく第
３図のようになるが、入力端子１が開放されたときの入
力端子１及び出力端子２の電圧は、定電流性素子Ｑ。が
付加されたことによつてＡ点からＢ点に移つている。従
つてハイレベルまたはローレベルの入力が印加された時
の入力端子１及び出力端子２の電位変動幅は従来の回路
を使用した場合の半分程度となり、また、Ｂ点付近の増
幅度（入力変動幅に対する出力変動幅の比）が大きいこ
とから、信号の伝達遅延時間の短縮がはかられる。上に
本発明の一実施例を示したが、第２図の負荷素子ＱＬ及
び定電流性素子Ｑ。A dip-type MISFET with a threshold voltage VT of about -3V is used as the MISF for the driver.
An enhancement type MISFET with a threshold voltage V1 of about +1V is used as the ETQO. When the power supply voltage (00) is +5V and the input voltage range is +0.2 to 1.5, the respective MISFETQL and Q.
．． ! 11. Q0 dimensions (channel width/channel length)
The ratio is preferably set to 3:200:l. The input/output characteristics of the embodiment shown in FIG. 2 are as shown in FIG. 3, the same as the circuit shown in FIG. 1, but when input terminal 1 is open, the voltages at input terminal 1 and output terminal 2 are Current element Q. As a result of the addition of , the point has moved from point A to point B. Therefore, when a high-level or low-level input is applied, the width of potential fluctuation at input terminal 1 and output terminal 2 is about half that when using a conventional circuit, and the amplification degree (input fluctuation) near point B Since the ratio of the output fluctuation width to the output fluctuation width is large, the signal transmission delay time can be shortened. One embodiment of the present invention is shown above, and the load element QL and constant current element Q in FIG.
はデイプリーシヨン形のＭＩＳＦＥＴを使用する必要は
なく、ゲートを高電位に接続したエンハンスメント形の
ＭＩＳＦＥＴや単なる抵抗によつても置きかえることが
でき、またドライバ用ＭＩＳＦＥＴも定電源６の電圧を
適当に選ぶことによつてデイプリーシヨン形ＭＩＳＦＥ
Ｔを使用することも可能である。It is not necessary to use a depletion type MISFET, and it can be replaced with an enhancement type MISFET whose gate is connected to a high potential or a simple resistor. Depletion type MISFE by selecting
It is also possible to use T.
第１図は従来のゲート接地形増幅回路、第２図は本発明
の一実施例の回路図、第３図は第１図及び第２図の回路
の入出力特性図であり、図中、ＱＬは負荷素子用ＭＩＳ
ＦＥＴ，ＱＤはドライバ用ＭＩＳＦＥＴ，ＱＯは定電流
性素子用ＭＩＳＦＥＴを示し、更に１は入力端子、２は
出力端子をそれぞれ示す。FIG. 1 is a conventional gate grounded plane amplifier circuit, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is an input/output characteristic diagram of the circuits shown in FIGS. 1 and 2. QL is MIS for load element
FET and QD are driver MISFETs, QO is a constant current element MISFET, 1 is an input terminal, and 2 is an output terminal.
Claims (1)
び定電流性素子をこの順に直列に接続し、前記駆動用ト
ランジスタ素子の入力に定電圧を与え、前記駆動用トラ
ンジスタ素子と前記定電流性素子との接続点に入力信号
を与え、前記駆動用トランジスタ素子と前記負荷素子と
の接続点から出力を取り出すようにしたことを特徴とす
るセンス回路。1 A load element, a driving transistor element, and a constant current element are connected in series in this order between power supplies, a constant voltage is applied to the input of the driving transistor element, and the driving transistor element and the constant current element are connected in series. An input signal is applied to a connection point between the driving transistor element and the load element, and an output is taken out from a connection point between the driving transistor element and the load element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52038870A JPS5947390B2 (en) | 1977-04-04 | 1977-04-04 | MIS memory sense circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52038870A JPS5947390B2 (en) | 1977-04-04 | 1977-04-04 | MIS memory sense circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53123630A JPS53123630A (en) | 1978-10-28 |
| JPS5947390B2 true JPS5947390B2 (en) | 1984-11-19 |
Family
ID=12537238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52038870A Expired JPS5947390B2 (en) | 1977-04-04 | 1977-04-04 | MIS memory sense circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5947390B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0085123B1 (en) * | 1982-01-30 | 1985-06-19 | Deutsche ITT Industries GmbH | Isolated gate field effect transistor circuit for sensing the voltage of a knot |
-
1977
- 1977-04-04 JP JP52038870A patent/JPS5947390B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53123630A (en) | 1978-10-28 |
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