JPS5946469B2 - AGC circuit of video circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AGC circuit for video signals, and particularly to a synchronous AGC circuit.
Both peak AGC and high precision AGC are possible.
This paper attempts to propose a circuit that can perform GC.

An embodiment of the present invention will be described below with reference to FIG.

This embodiment is a case where the present invention is applied to a VTR. 1st
In the figure, reference numeral 1 denotes an input terminal to which a video signal is supplied, and a video signal from, for example, a video camera is supplied to this input terminal 1. This video signal is supplied to the variable gain amplification circuit 2,
The output is supplied to the clamp circuit 3VC, and the pedestal portion of the video signal is clamped to the reference clamp level E7. The output of the clamp circuit 3 is supplied to the FM modulation circuit 4VC for FM modulation, and the output is supplied to the rotary magnetic head 6 through the recording amplification circuit 5. A part of the output of the clamp circuit 3 is connected to first and second circuits for comparing the video signal with a reference clamp level E and a reference white level E2.
Comparator circuit T and 8VC are supplied.

+B is a power supply that generates a voltage at a reference clamp level E, and +B2 is a power supply that generates a voltage E2 at a reference white level. Both comparison outputs from the first and second comparison circuits T and 8 are supplied to a combiner 13 and added, and the added output is supplied to a peak detection circuit 9. The output from the peak detection circuit 9 is supplied to a third comparator circuit (amplifying circuit) at 10 VC and is compared with the AGC reference voltage Es from the power supply +B3.
The comparison output is supplied to a low-pass filter 11, and the output of the low-pass filter 11 is supplied as a gain control signal to the variable gain amplification circuit 2 through a DC amplification circuit 12 to control its gain. . Next, the first and second comparison circuits T and 8 in FIG. 1, the reference voltage generation circuit 15 that generates each voltage of the reference clamp level E7 and the reference white level E2, the synthesizer 13, and the peak detection circuit 9 are connected. Part 2 about specific circuits
This will be explained with reference to the figures.

The reference voltage generation circuit 15VC has an NPN transistor Q, whose collector is connected to the power supply +BVC, whose emitter is grounded through a series circuit of resistors R3 and R4, and which is connected between the power supply +B and the ground. resistor R
The connection midpoint of the series circuit of 1-R2 is the transistor Q,
The reference clamp level voltage E1 is connected to the base of the transistor Q1 from the emitter of the transistor Q1, and is connected to the base of the resistor R3 and R4.
The reference white level voltage E2 is obtained from the midpoint of the connection. The first comparator circuit 7 is composed of a differential amplification circuit consisting of PNP type transistors Q2 and Q3 and a constant current circuit 1K1 connected to the power supply +BlfC, and the emitters of the transistors Q2 and Q3 are connected to the power supply through the constant current circuit 1K1. +B and transistor Q1
The emitter of the transistor Q2 is connected to the base of the transistor Q2, and the base of the transistor Q3 is connected to the input terminal t1 to which the clamped video signal from the clamp circuit 3 is supplied.

The collector of transistor Q3 is grounded. The second comparison circuit 8 is constituted by a differential amplifier circuit consisting of PNP type transistors Q4 and Q and a constant current circuit 1K2, and each emitter of the transistors Q4 and Q5 is connected to the constant current circuit 1K2.
The midpoint between resistors R3 and R4 is connected to the base of transistor Q4, the base of transistor Q is connected to input terminal t1, and the collector of transistor Q4 is grounded.

Both comparison outputs of the first and second comparison circuits 7 and 8 are supplied to a clip circuit 161fC. Clip circuit 1611C.
NPN transistors Q6 and Q are provided, their respective emitters being grounded through resistors R and R6, respectively, and the collectors of transistors Q6 and Q being connected to the power supply +BllC. The midpoint of a series circuit of resistors R7R8 connected between power supply +B and ground is connected to the bases of transistors Q6 and Q7. The output of clip circuit 16 is supplied to combiner 13.

In the combiner 13, NPN type transistors Q8 and Q are provided, each emitter of which is connected to a resistor RlO, respectively.
It is grounded through Rll, and its respective collector is connected to the power supply +B through a load resistor R9. and,
The emitter of transistor Q6 is connected to the base of transistor Q, and the emitter of transistor Q is connected to the base of transistor Q8. The added output from the combiner 13 is supplied to the peak detection circuit 9.

In the peak detection circuit 9, a PNP transistor Q
lO is provided, its collector is grounded (and its emitter is connected to the power supply +B through a parallel circuit of resistor Rl2 and capacitor C), and an output terminal T2 is led out from its emitter, and this output The output from the terminal T2 is supplied to the third comparator circuit 10. Next, the operation of the AGC circuit of this video circuit will be explained with reference to the waveform diagram in FIG.

FIG. 3 shows an example of the waveform of the clamped video signal (negatively modulated composite video signal) from the clamp circuit 3. The video signal of FIG. 3 is supplied to the first and second comparison circuits 7 and 81fC as described above. Then, the first comparison circuit 7 detects the level Δ1 of the horizontal synchronizing signal portion of this video signal, and the second comparison circuit 8 detects that the level Δ1 of the horizontal synchronizing signal portion of this video signal exceeds the reference white level E2. Part level △2
is detected. And the peak detection circuit 9 has a level △1.
+Δ2 output is supplied. In this way, the variable gain amplification circuit 2 is subjected to both synchronous AGC and peak AGC in accordance with level Δ1 and level Δ2. In FIG. 3, the difference between reference levels E1 and E2 is defined as A. Now,
In the case of a regular video signal, △1 is 8, and △2 is △.

2, △01 and △.

If you choose so that 2 is 30% and A is 40%, △1
+△2+A is 100! ), △2 becomes △.

If it is greater than 2, the AGC will be controlled by △2, which will be the peak AGC, and △2 will be △.

If smaller than 2, AGC is △1VC. Therefore, this becomes a synchronous AGC.

Incidentally, the tag circuit 16 is provided to prevent the output of the peak detection circuit 9 from rising to the voltage of the power supply +B when there is no signal or when the signal level is abnormally low.

That is, when the signal level is abnormally low, transistors Q6 and Q7 are turned on and the output of the peak detection circuit 9 is set to a predetermined potential value. By doing so, it is possible to prevent the gain of the variable gain control circuit 2 from becoming abnormally high when there is no signal or when the signal level is abnormally low. A of the above-mentioned video circuit of the present invention
In the GC circuit, after the pedestal portion of the video signal is clamped to the reference clamp level, the clamped video signal is compared with the reference clamp level and the reference white level, and the outputs of both comparisons are supplied to the peak detection circuit. Since the gain of the variable gain amplification circuit to which the video signal is supplied is controlled by the detected output, synchronous AGC and peak A
Both AGCs of the GC are multiplied and the AGC becomes highly accurate.

Also, by varying the ratio of E, E2, synchronous AGC
peak AGClfC. The moving point can be varied.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a circuit connection diagram showing a part of the specific circuit of Fig. 1, and Fig. 3 is a waveform diagram. . 2 is a variable gain amplification circuit, 3 is a clamp circuit, 7 and 8 are first and second comparison circuits, and 9 is a peak detection circuit.

Claims (1)

[Claims] 1 A variable gain amplification circuit, a clamp circuit that clamps the pedestal portion of the video signal from the variable gain amplification circuit to a reference clamp level, and a clamp circuit that supplies the clamped video signal from the clamp circuit to the reference clamp level. It has first and second comparison circuits for comparing with a clamp level and a reference white level, and a peak detection circuit to which both comparison outputs from the first and second comparison circuits are combined and supplied. An AGC circuit for a video circuit, characterized in that the gain of the variable gain amplification circuit is controlled according to the level of the detection output from the detection circuit.