JPS5944896A - Electronic circuit device - Google Patents

Electronic circuit device

Info

Publication number
JPS5944896A
JPS5944896A JP15569282A JP15569282A JPS5944896A JP S5944896 A JPS5944896 A JP S5944896A JP 15569282 A JP15569282 A JP 15569282A JP 15569282 A JP15569282 A JP 15569282A JP S5944896 A JPS5944896 A JP S5944896A
Authority
JP
Japan
Prior art keywords
circuit
connector
electronic circuit
circuit element
electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15569282A
Other languages
Japanese (ja)
Inventor
影山 精一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP15569282A priority Critical patent/JPS5944896A/en
Publication of JPS5944896A publication Critical patent/JPS5944896A/en
Pending legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [発明の技術分野1 本発明は電子回路装置に係り、特に電子回路素子を複数
連結接続しC回路の拡張を可能にした電子回路具1Gに
関りる。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention 1] The present invention relates to an electronic circuit device, and particularly to an electronic circuit device 1G in which a plurality of electronic circuit elements are interconnected and a C circuit can be expanded.

[発明の技術的背景1 電子回路装置、例えば、メモリ回路装置にあつ(、回路
の拡張を図る場合には、回路基板を実装したラックのあ
まっているス[lツI〜に回路基板を追加しC取(=J
りたり、第1図に示t J:うに複数のメモリ回路素子
1を搭載した回路基板2上にスベー“す3を介して別の
回路基板4を取(Jす、この回路基板4に拡張用のメ[
り回路素子1)を1ハ載りることが行われCいる。
[Technical Background of the Invention 1] When expanding the circuit of an electronic circuit device, such as a memory circuit device, it is necessary to add circuit boards to an unused rack on which circuit boards are mounted. Shi C (= J
Alternatively, as shown in FIG. The menu for
One circuit element 1) is mounted on the other hand.

また、回路の拡張が小規模Cある場合に(よ、第2図に
示り゛ように、多め回路基板2に設(〕られたメモリ回
路素子拡張用のスペースいわゆるサービスエリア6に拡
張用のメモリ回路素子を1八載し0行なわれる。なおこ
のようにサービス丁り)′6を用いる例としては、ワン
ボード・マイク+−+ ニー+ンビュータ等によ〈実施
され−Cいる。
In addition, if the circuit expansion is on a small scale (as shown in Fig. 2), a space for expansion of memory circuit elements provided on the circuit board 2 (as shown in Fig. 2) is provided in the so-called service area 6 for expansion. It is implemented by mounting 18 memory circuit elements and using the above-mentioned service specifications.

[背景技術の問題点1 しかしながら°、上述のように回路基板2上にスペー→
)3を介して別の回路基板4を川ね(メ1り回路を拡大
する場合には、それぞれの回路基板2.4を」ネクタ等
で結線す゛る必要があり、配線が複雑となって組立が面
倒であるうえ、外観も良好(Jならない欠点がある。
[Problem 1 in Background Art However, as mentioned above, there is no space on the circuit board 2→
) 3 to another circuit board 4 (me 1) When expanding the circuit, it is necessary to connect each circuit board 2.4 with a connector etc., making the wiring complicated and making assembly difficult. Not only is it troublesome, but the appearance is also good (J has some drawbacks).

しかも、回路基板2十に別の回路基板1を配tiするス
ペースがない場合には実施することかC′イない。
Moreover, if there is no space on the circuit board 20 to arrange another circuit board 1, it is impossible to carry out this process.

また、予め回路基板2に設()たリービス」リノ26に
メしり回路A〜rを実装しく回路の拡張を図る場合には
、回路基板2の人形化を防ぐ観点から、僅かな回路の拡
張しかひきないfjt点があり、また当初から拡張の程
庭も不確定(゛あることl)+ fう、適切な規模のリ
ービスエリア6を予め回路基板2に設りることは極め−
C困デ1]ひある。
In addition, when expanding the circuit by mounting the circuits A to R on the Revis Reno 26 previously installed on the circuit board 2, it is necessary to expand the circuit slightly in order to prevent the circuit board 2 from turning into a doll. There is a point fjt that can only be drawn, and the extent of expansion is uncertain from the beginning.
C Trouble De 1] Hiyaru.

[発明の目的] 本発明はこのよう4【従′)1この欠点をM沃するため
になされたしので・、回路基板での回路の拡張が極めて
容易でか′つ電子回路素子の実]・超密度を向[りるこ
との可能な電子回路装置の提供を1]的とづる。
[Object of the Invention] The present invention has been made in order to overcome these drawbacks, and therefore provides an electronic circuit element in which circuit expansion on a circuit board is extremely easy.・Our goal is to provide an electronic circuit device that can achieve ultra-high density.

1光明の棚要] この目的を達成4るlCめに木考案(41バツクージさ
れた複数の電子回路装置各々にd3いて、−側面から接
続子を突出さμるとどもに異なる側iniに前記接続子
と同様な接続子の挿入接続可能な=1ネクタ部祠を備え
、−の電子回路素子の上記接続子を他の電子回路素子の
4]二記コネクタ部材へ挿入接続し、上記複数の電子回
路素子を連結接続し4なることを特徴とりるものひある
To achieve this objective, a wooden device was devised (41) to each of the plurality of electronic circuit devices that had been installed, and by protruding the connectors from the sides, the connectors were placed on different sides of the It is equipped with a =1 connector part shrine in which a connector similar to the connector can be inserted and connected, and the connector of the - electronic circuit element is inserted and connected to the connector member of the other electronic circuit element, and the plurality of One feature is that four electronic circuit elements are connected together.

[発明の実施例1 以下本発明の詳細な説明りる1゜ 第3図および第4図は本発明の電子回路装「¥4構成す
る個々の電子回路素子を示J斜祝図、13よび側面図ぐ
ある。
[Embodiment 1 of the Invention The present invention will be described in detail below. 1. Figures 3 and 4 show individual electronic circuit elements constituting the electronic circuit system of the present invention. There is a side view.

図におい−C合成樹脂等ぐバッタージされた電を回路素
子としCのメモリ回路素子1(3未、内部に32にパイ
1−メモリジー1−ルを内蔵し、比較的偏平に成形され
たパッケージ7の側面からは横〕“i向にのびる接続子
8が突設され−Cいる。
In the figure, the memory circuit element 1 (3) of C is made of a battery packed with a synthetic resin or the like as a circuit element, and the package 7 is formed into a relatively flat shape, with a pie 1-memory gear 1 built-in at 32. A connector 8 is protruded from the side surface of the connector 8 and extends in the horizontal direction.

接続子Bは、メモリ回路素子1のパッケージ7から一体
的に突設されI〔断面凸状の突設片?〕と、この突設片
9の表面に形成されかつバック−シフ    ′内部の
メモリモジコール(図示Uず)に電気的に接続された複
数の接続電tIIi10からなつ(いる。
The connector B is integrally provided to protrude from the package 7 of the memory circuit element 1, and is a protruding piece with a convex cross section I? ], and a plurality of connecting terminals tIIi10 formed on the surface of the projecting piece 9 and electrically connected to a memory module (not shown) inside the back shifter.

メモリ回路素子1にJ3りる接続子ε3との反対側面に
は、上記接続子8と同様な構成の接続子の挿入可能な]
ネクタ8(ロイ11が形成され(いる。1ネクタ部4.
!l 11 tよ、接続子ε3より1.)1吊か(こ大
径の凹)jへ12と、この凹溝12内に配りI1され、
かつ接続子の接続電極に接触り゛るとと−しに内部のメ
しりモジコールに接続される接続端子13からなつCい
る。
A connector having the same configuration as the connector 8 described above can be inserted on the opposite side of the memory circuit element 1 from the connector ε3 connected to J3.]
Connector 8 (Roy 11 is formed. 1 connector part 4.
! l 11 t, from connector ε3 1. ) 1 hanger (large diameter concave) 12 and distributed in this concave groove 12,
When it comes into contact with the connection electrode of the connector, it is connected to the connection terminal 13 which is connected to the internal module module.

ぞしC1図中符号171は各メtり回路素子1にJハノ
る後)ボするチツブセレク1−(GE)端子の番地指定
を目的どりるD I Pスイツブーぐある。
Reference numeral 171 in the figure C1 is a DIP switch whose purpose is to designate the address of the chip select 1-(GE) terminal that is to be inserted after each meter circuit element 1 is connected.

このJ:うに構成されたメしり回路素子1【、上、第5
図に示1J、うに、メしり回路素子′1のT1ネクタ部
材11に同様に構成された別のメtり回路素子1aの接
続子ε3ン1を挿入し、接続子8の接続1′1?極(図
示せず)と二1ンクタ部月11の接続端子13を接続し
てメ七り回路!!i侃が構成される。
This J: Meshiri circuit element 1 [, top, fifth
As shown in the figure 1J, the connector ε3 of another mesh circuit element 1a having the same structure is inserted into the T1 connector member 11 of the mesh circuit element '1, and the connection 1'1 of the connector 8 is inserted. ? Connect the terminal (not shown) and the connecting terminal 13 of the 21st connector part 11 to complete the circuit! ! The i side is configured.

第(5図はメ1−り回路素子゛1.1a 、 ill 
、icを4個連結接続してメモリ回路装置を4jり成さ
く!た状態を承り斜視図ひある。
(Figure 5 shows the main circuit element 1.1a, ill
, create a 4J memory circuit device by connecting four ICs together! There is a perspective view of the state.

このJ、うに4個連結された7トJ”回路装置にお【)
る回路構成は、例えば第7図のJ、うに接続される。
This J is a 7-to-J" circuit device that connects four sea urchins.
The circuit configuration shown in FIG. 7 is connected, for example, to J in FIG.

−リなわら、各メモリ回路素子1〜ICIよ、ε3ビツ
トの入出力端子、′155ピッ1〜のノlドレス指定端
子Ao〜Δ14、CF娼1子、13よびW/1<端子を
右しCおり、それぞれの端子が上述の接続子と3.1ネ
クタ部材を介しく独立しC’+9出されるよう(Jなっ
ている。
- In addition, each memory circuit element 1 to ICI, ε3 bit input/output terminal, '155 pin 1 to address designation terminal Ao to Δ14, CF 1 to 13, and W/1< terminal to the right. Then, each terminal is connected to C'+9 independently via the above-mentioned connector and 3.1 connector member (J).

そして、回路基板(図示けり゛)に実装した1易合、2
ピツ1〜の入力端子■0、I2をイ1りるデー1−ダ回
路15の出力端子YO〜Y3を各メLり回路素子1〜1
Cの各CE端子に接続し、W / Rl;’;号および
ノアドレス信号をイれぞれのメ−しり回路素子′1〜1
CのW/R端子およびアドレス指定端−rに接続′りる
。なお、デコーダ回路15の人力をノ′ドレス指定端子
A+ 4 、A+ 5とづれば、各メしり回路素子tよ
見かiづ上17ビツ1−のアドレス指定’1jJ能に機
能りる。
Then, 1 case, 2 case mounted on a circuit board (as shown in the figure).
The output terminals YO to Y3 of the data circuit 15 are connected to each of the circuit elements 1 to 1.
Connect to each CE terminal of C, and send the W/Rl;'; and address signals to each of the circuit elements'1 to 1.
It is connected to the W/R terminal of C and the addressing terminal -r. If the decoder circuit 15 is manually operated by the address designation terminals A+ 4 and A+ 5, it functions to designate the address of each of the 17 bits 1- of each of the circuit elements t.

第8図は、−]−述の第6図に示づ4個のメ1−り回路
素子1〜1Cを、接続子88〜8Cを]ネクタ部月11
〜111〕に挿入接続し−C連結したメモリ回路装置を
、回路基板1G士(こ実装した状態を示?i断百図であ
る。
FIG. 8 shows the four relay circuit elements 1 to 1C shown in FIG.
This is a cross-sectional view showing the state in which the memory circuit device inserted and connected to the circuit board 1G (111) and connected to the circuit board 1G (111) and connected by -C is mounted.

連結されたメt−り回路装置′1−・1 cにJ’iり
る両端のメIlり回路素子1.1cは、回路基板10上
に立設された支持ターミプル17.18間に支持される
どどもに、メ■:り回路素子1の接続子ε3が支持ター
ミノル17の出力端子10に接続しC1回に′8J、を
板゛16の回路パターン(図示Uす゛)に接続されてい
る。
The parallel circuit elements 1.1c at both ends of the connected parallel circuit devices '1-.1c are supported between support termiple 17. For those who are doing so, the connector ε3 of the circuit element 1 is connected to the output terminal 10 of the support terminal 17, and the connector ε3 of the circuit element 1 is connected to the circuit pattern of the board 16 (as shown in the figure). There is.

支持ターミノ−ル17.18間に支持されたメしり回路
装置と回路基板16の間にはスペース20が生じるのひ
、このスペース20を利用しCフラットパッケージ形電
子回路素子21X5チップ形1代抗22等を回路基板1
6上に実装りることか′Cさる。
A space 20 is created between the circuit board 16 and the mesh circuit device supported between the support terminals 17 and 18. This space 20 is used to attach the C flat package type electronic circuit element 21x5 chip type single generation resistor. 22 etc. to circuit board 1
Is it possible to implement it on 6?

」−述の実施例にa月ノる接続子8〜8Gとし゛(−は
、メEり回路素子1〜1cの側面から凸状の突設片9を
一体的に突設し、ぞの突t々ハ()に接続電極10を形
成する例を説明1ノたが、本発明にあっC(まこれに限
定されることなく、例えばff19図に承り、ように、
メ[り回路素子゛1の側面からり〜ドビン233を複数
突設りることによっU ’t)iiJ nuであり、連
結されるメ七り回路素f′1・〜1cの−1ネクタ部材
11としては、このリートピン23からなる接続子24
の挿入接続の11能なIM造に41う成りれ【、[、J
In the embodiment described above, the connectors 8 to 8G have been added to the connectors 8 to 8G for a month. Although an example of forming the connection electrode 10 in t and t() has been described above, the present invention is not limited to this, and for example, as shown in FIG.
By protruding a plurality of dobbins 233 from the side surface of the main circuit element 1, the -1 connector of the connected main circuit elements f'1 to 1c is obtained. As the member 11, a connector 24 made of this lead pin 23 is used.
41 results for the 11-capable IM structure of insertion connection [, [, J
.

い。stomach.

なJ3、接続子8へ−8Cおにび−1ネクタ部祠1′1
〜11cにdH)る回路接点の数Ij1、メUり回路素
子1〜1Cにお1.Jるメモリしジコールの容吊りなり
ちアドレス指定端子等に応じU (I意にj式定rl 
fliiCある。
J3, to connector 8-8C Onibi-1 connector part shrine 1'1
The number of circuit contacts Ij1 in ~11c, and 1 in the circuit elements 1~1C. Depending on the address specification terminal, etc., the memory of J
There is fliiC.

さらにま)〔、上3Jiのメモリ回路素子1・〜’I 
c It:あっては、接続子8〜8 Cおよび二1ンク
タ部祠′11.11cを−でれぞれ対向りる側面に形成
したが、連結づる方向に合i!てそれぞれ異なる側面に
形成すれば本発明の目的)構成が可能である。。
Further, the memory circuit element 1 of the upper 3Ji ~'I
c It: In this case, the connectors 8 to 8 C and the connector part 11 and 11c were formed on opposite sides at -, but they were aligned in the direction of connection. If they are formed on different sides, the object of the present invention) can be achieved. .

なお、電子回路素子どlノCは、メしり回路索r1〜1
Gのイljlイるいろな電j’ 1jil路永J′−1
,la3イ(応用Cきることはいうよr′tJない。
In addition, the electronic circuit elements 1-C are connected to the mesh circuit lines r1 to 1.
G's Iljl Iruiro na Denj' 1jil Michinaga J'-1
, la3 i (application C can be done, but r'tJ is not.

[発明の効果」 以上説明したように本発明の電子面&8 装置f”−は
、パッケージされた複数の゛市了回路素子各77(こ、
−側面から接続子を突出させるとともに異なる側面に1
記接続了と同様4f接続子の挿入接続可能な゛二1オク
タ部祠を備え、−の電子回路素子の1−記接続了を他の
電子回路素子の−L n+、 ”ネクタ部イ・イl\挿
入接続(]′cjル枯したので、電子回路素子に備えた
接続子を他の電子回路素子の−1ネクタ部4Aに挿入接
続づるだ【プひ直接複数の電子回路素子を連結接続可能
となり、極め(簡単に電子1ijl路素子の回路拡張が
できる。
[Effects of the Invention] As explained above, the electronic device f”- of the present invention includes a plurality of packaged commercially available circuit elements 77 (these,
- With the connector protruding from the side and one on a different side
It is equipped with a 21 octater part which can be connected by inserting a 4F connector in the same way as the above connection. l\Insertion connection ()'cj Now that the connector has run out, insert and connect the connector provided on the electronic circuit element to the -1 connector part 4A of another electronic circuit element. This makes it possible to easily expand the circuit of electronic circuit elements.

しかも、枚数の電子回路素子を直接連結接続りることが
可能CあるhS tら、電子面A’8 i子の占める実
装面梢が小さく、回路基板上の実装密度を向上させるこ
とができる、。
Moreover, it is possible to directly connect and connect several electronic circuit elements, and the mounting surface occupied by the electronic surface A'8 is small, making it possible to improve the mounting density on the circuit board. .

また、連結された電子回路素子を支持ターミプル等を介
しく回路基板上に実装づる場合には、電了回路素」′ど
回路基数間にスペースが生じるの(゛、このスペースを
イ1効に利用し℃他の電r部品を回路基板に実装づるこ
とがjす能と4.−リ、大幅な実装密度の向上を図るこ
とがC゛きる。
In addition, when mounting connected electronic circuit elements on a circuit board via support terminals, a space is created between the power supply circuit elements and circuit boards. By utilizing the ability to mount other electrical components on a circuit board, it is possible to significantly improve the packaging density.

【図面の簡単な説明】[Brief explanation of the drawing]

第1 図13よ(j ’d52 図ハ(+r g< (
1) 電flid路H!!”f 、11ota明する斜
視図J3よび平面図、第3図J3.」、び第4図は本発
明の電子回路装置を構成りる個々の電子回路素子の一実
施例を示V斜祝図および側1iTi図、第5図および第
6図は第3図に示り゛電子回路素子を連結覆る状態を示
ず部分断面図および斜視図、第7図は第6図に示−り電
子回路装置Nの接続を示すノ[−1ツク図、第8図は本
発明の電子回路装置を回路基板上に実装りる状態を示v
l−断面図、第0図は本発明の電子回路装置の電子回路
素子の他の実fArIfailを示1斜視図である。 1.1a−・1C・・・・・・・・・電子回路素子(メ
■り回路素r) 7・・・・・・・・・・・・・・・・・・・・・バラ今
一ジ8、ε3a〜8C・・・接続子 10・・・・・・・・・・・・・・・・・・・・・接続
電極11.11a−・′11G・・・・・・−」ネクタ
部材12・・・・・・・・・・・・・・・・・・・・・
凹溝13・・・・・・・・・・・・・・・・・・・・・
接続端子15・・・・・・・・・・・・・・・・・・・
・・デ]−夕回路16・・・・・・・・・・・・・・・
・・・・・・回路阜仮代理人か理−1須 山 111一 第1図 第乙図
1st Figure 13(j 'd52 Figure C(+r g< (
1) Electric flid route H! ! "F, 11 Ota Revealing Perspective View J3 and Plan View, Figure 3 J3." and Figure 4 are V perspective views showing one embodiment of the individual electronic circuit elements constituting the electronic circuit device of the present invention. and side 1iTi views, FIGS. 5 and 6 are shown in FIG. 3, and FIG. Figure 8 shows the electronic circuit device of the present invention mounted on a circuit board.
1-1 cross-sectional view and FIG. 0 are perspective views showing another actual electronic circuit element fArIfail of the electronic circuit device of the present invention. 1.1a-・1C・・・・・・Electronic circuit element (Mail circuit element r) 7・・・・・・・・・・・・・・・・・・・・・・・・Release date One wire 8, ε3a~8C...Connector 10...Connection electrode 11.11a-・'11G...- ” Connector member 12・・・・・・・・・・・・・・・・・・・・・
Groove 13・・・・・・・・・・・・・・・・・・
Connection terminal 15・・・・・・・・・・・・・・・・・・
・・・De]-Evening circuit 16・・・・・・・・・・・・・・・
...Circuit temporary agent or logic - 1 Suyama 111-Figure 1 Figure B

Claims (1)

【特許請求の範囲】[Claims] (1)パッケージされた複数の電子回路素子名々におい
で、−側面から接続子を突出さゼるとともに異なる側面
に前記接続子とIr11様な接続子の挿入接続可能な1
ネクタ部材を備え、−の電子回路素子の前記接続子を他
の電子回路素子の前記ニ】ネクタ81;祠へ挿入接続し
、前記複数の電子回路素子を連結接続しくなることを特
徴とづる゛電子回路装置。
(1) In a plurality of packaged electronic circuit elements, a connector can be protruded from one side and the connector and an Ir11-like connector can be inserted and connected to a different side.
It is characterized by comprising a connector member, and inserting and connecting the connector of the - electronic circuit element to the connector 81 of another electronic circuit element to connect and connect the plurality of electronic circuit elements. Electronic circuit equipment.
JP15569282A 1982-09-07 1982-09-07 Electronic circuit device Pending JPS5944896A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15569282A JPS5944896A (en) 1982-09-07 1982-09-07 Electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15569282A JPS5944896A (en) 1982-09-07 1982-09-07 Electronic circuit device

Publications (1)

Publication Number Publication Date
JPS5944896A true JPS5944896A (en) 1984-03-13

Family

ID=15611453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15569282A Pending JPS5944896A (en) 1982-09-07 1982-09-07 Electronic circuit device

Country Status (1)

Country Link
JP (1) JPS5944896A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02251245A (en) * 1989-03-24 1990-10-09 Kao Corp Preparation of copper-iron-aluminum catalyst

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02251245A (en) * 1989-03-24 1990-10-09 Kao Corp Preparation of copper-iron-aluminum catalyst

Similar Documents

Publication Publication Date Title
JPS5944896A (en) Electronic circuit device
JPS61120454A (en) Package of integrated circuit for data memory
JPS605224U (en) integrated wire coupler
JPS6023895Y2 (en) connection device
JPH08185942A (en) Extension ic socket
JPS608375Y2 (en) Protector module socket
JPS5855808Y2 (en) Mounting structure of high-density logic circuit
JPH0215324Y2 (en)
JPS63246887A (en) Surface mount component package
JPS58159359A (en) Chip case for integrated circuit
JPS63249362A (en) Package for surface-mounting parts
JPS58158472U (en) Printed board
JPS6062133U (en) connector device
JPS5933769A (en) Wiring structure between circuit boards
JPS6075986U (en) connector device
JPS6124899U (en) memory expansion device
JPS59149697U (en) switching circuit parts
JPS6049656U (en) Printed wiring board for extension
JPS6026178U (en) branch terminal block
JPS5915215U (en) Structure of laminated circuit board
JPS5989446A (en) Coupling device for semiconductor device
JPS606269U (en) Substrate for hybrid integrated circuits
JPS609260U (en) Printed board connection structure
JPS58106944U (en) probe card
JPS6039576U (en) Bulk pressure welding multi-core cable for branching