JPS5944895A - Method of producing multilayer printed circuit board - Google Patents

Method of producing multilayer printed circuit board

Info

Publication number
JPS5944895A
JPS5944895A JP15605082A JP15605082A JPS5944895A JP S5944895 A JPS5944895 A JP S5944895A JP 15605082 A JP15605082 A JP 15605082A JP 15605082 A JP15605082 A JP 15605082A JP S5944895 A JPS5944895 A JP S5944895A
Authority
JP
Japan
Prior art keywords
multilayer printed
circuit board
mark
copper
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15605082A
Other languages
Japanese (ja)
Inventor
高林 弘二
近藤 輝武
利根川 治夫
塩崎 晴美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP15605082A priority Critical patent/JPS5944895A/en
Publication of JPS5944895A publication Critical patent/JPS5944895A/en
Pending legal-status Critical Current

Links

Classifications

    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16NLUBRICATING
    • F16N7/00Arrangements for supplying oil or unspecified lubricant from a stationary reservoir or the equivalent in or on the machine or member to be lubricated
    • F16N7/12Arrangements for supplying oil or unspecified lubricant from a stationary reservoir or the equivalent in or on the machine or member to be lubricated with feed by capillary action, e.g. by wicks

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は多層印刷配線板VJ袈装造に関丁ゐ。[Detailed description of the invention] The present invention is applicable to multilayer printed wiring board VJ cover construction.

従米多層印刷配−4Piケ衷造する除、ガイドマーク及
び必袋な回路パターンを南する内層回踊板りガイドマー
ク上にあらかじめ#V41F!’i’!月料孕貼り付け
その表面にガラス基拐グリグレグケ弁して、姉曽り又は
ガラス布水材片曲針]シ長稙層・1反ケ剖i1?山が外
面に配にさ!【匂ように沖ね台せ全体ケカ(1熱加圧槓
H・一体化しに後ガイドマーク上(/、1帖泊及び基材
を旨1(型4A科と共に同時Vこ取−り除きカイトマー
クを詠出芒ぜ蕗出芒−ぎ北カイドマークケ基準点として
外面の鋼箔ケ内層回路と位置付セ“葡行いながら回路加
工業して多層印刷配酬叡ケ製造していた。
Multi-layer printing arrangement - Except for the 4Pi case, the guide mark and the required circuit pattern are placed on the inner layer circular board guide mark in advance #V41F! 'i'! Glue pasted on its surface with a glass base and a curved needle on the glass cloth material] Mountains are placed on the outside! [The entire surface of the deck is placed offshore (1 heat pressurized and integrated, then on the guide mark (/, 1 board and the base material is removed at the same time as type 4A) The marks were drawn, the awns were drawn, and the marks were used as reference points for the outer steel foil inner layer circuits and positioning, while the circuit processing industry was used to manufacture multi-layer printed circuit boards.

上記方法で装造した多層印刷配線板は、ガイドマーク上
にP#、型材料?貼り付り々Cとにより、都型月料の厚
情により隼ねザせゐ除、ガラス力・;狗フリグレク層に
ボイド葡殆生Bぜゐ原因となる。又耐振材料がカイトマ
ーク以外の必りな141路パターンに1で1肘しテラば
ネーションの原因となり多層印刷配線板に悪影竹ケ及は
す。
The multilayer printed wiring board assembled using the above method has P# and mold material on the guide marks. Due to the stickiness C, due to the kindness of metropolitan monthly fee, Hayabusa Nazari removal, glass force and dog friglex layer cause void grapes and almost all B. In addition, the anti-vibration material is exposed to the necessary 141-way patterns other than the kite mark, causing terrarism and causing an adverse effect on the multilayer printed wiring board.

本発明にこのよ′)1点に亀みでなさノtたもりでカイ
トマーク及び必要な回路パターン會・1する内層回路板
の六■にカラス鯖拐7リグレグr介して銅箔又はガラス
恭拐片間銅彊槙層伍才餉:り箔が夕>+fuに配匣芒1
1る工f) fig哄ね付せ、全14弓1゛加熱加圧接
層一体化した後、カイドマーターヒGiJ銅箔及び基材
層?、ガイドマーク台・44J別し侍な厚みのカイトマ
ークに接する基材層會残して除去し、ガイドマーク勿基
準点として外…I tl’l ?−の回路加工ケ行うこ
とを特徴とするものである〇丁lわち本発明は多層印刷
配岬&r装瑣丁々除、カイトマーク、及び必97r、回
路パターン盆有する内層回路板 の衣+ruにカラスイ
IJ古と躬グリプレグケ弁しで餉消又fユヵラス亜泰材
片面銅′71?槓jel板金銅?kが外1t11に配h
atさ才りゐように小ね付せ全体ケ加熱力11圧一体化
した抜ツノ1ドマーク上り銅箔及び九材會エンドミル等
會用いて1b1時に取り除くか私材層についてQコ完全
に除去ぜr、0.05〜0.50w11vI基4J”r
残し、4月層kmしてカイトマークを認識3−る0又カ
イトマークをより良く認識丁/b77、め、基拐に搗性
の良い液を耶丸藺IL性の良い液とは、エタノール:グ
リセリン=0.1〜0.5 : Iの溶成が艮い。
In accordance with the present invention, the kite mark and the necessary circuit pattern must be placed at one point in the inner layer circuit board. Between the pieces of gold, there is a layer of gold and silver.
1) After attaching the fig and integrating all 14 bows with heat and pressure bonding layer, apply Kaidomatahi GiJ copper foil and base material layer. , separate the guide mark stand 44J and remove the base material layer that is in contact with the kite mark with a thick thickness, leaving the guide mark as a reference point...I tl'l? - The present invention is characterized by carrying out circuit processing of multi-layer printed cape & r mounting, kite mark, and inner layer circuit board with circuit pattern tray. Karasui IJ old and tsumigri pregke valve with a sushi mata f Yukarasu ayatai wood one side copper '71? Sheet metal copper? k is placed outside 1t11
At the time of 1b1, remove the whole part with a heating power of 11 pressure by using an integrated cutting edge, 1 mark, copper foil and a 9-material end mill, etc., or completely remove the private material layer. r, 0.05-0.50w11vI group 4J"r
The liquid with good IL properties is ethanol. : Glycerin = 0.1 to 0.5: Dissolution of I is obvious.

認識したカイトVこ穴ありy忙行ない多層印刷配線板ケ
製造する。
Manufacture multilayer printed wiring boards with recognized kites and holes.

図面はカイトマーク上の銅箔と基祠の一部ケ除去し、ア
ルコール、クリセリ(1)混ぜ敢オ塗布した状態を示し
に護「]川図であり、1は卸1陥、2にガイドマーク、
5は基伺泗、1.X内層回路パターン、5t;I内層回
路&基拐層、6は混台准ケ示す。
The drawing shows a state where part of the copper foil and the base shrine on the kite mark have been removed and a mixture of alcohol and Chriselin (1) has been applied. mark,
5 is Motokito, 1. X Inner layer circuit pattern, 5t; I Inner layer circuit & base layer, 6 indicates a mixed board.

以上説明したように本発明に於てに(Kり幼果が達fi
y、をtl、る〇 (リ 多111印A11ll配線板會裟造゛す゛ゐ院に
、内層回路板りガイドマーク上に瀦!ちり月相ケ用いな
いため、 ’jtiねせ〜釦ゐ際カラクイ15基材グり
フ゛レク1ψ・′−に離助拐料り厚みによ々ホイドり発
生かなくlv1欣中性が同上する。又、g+[m祠何か
カイトマーク以/Aり必吸な回路パターンに1・J7:
’Aしてう6生丁ゐテラだネーション〃)無くなる。
As explained above, in the present invention (Kri young fruit reaches fi
y, tl, ru〇(Re) 111 mark A11ll In the wiring board assembly, place it on the inner layer circuit board guide mark! Because the dust phase is not used, 'jti nese~button ゛Karakui 15 base material fiber 1ψ・'- has a separation material depending on the thickness, and the lv1 neutrality is the same as above. Circuit pattern 1.J7:
'A 6 raw terada nation〃) will be gone.

(2)  ガイドマークケー識する顧、−・:iJj消
と示拐り−st取9除いたカイトマーク上の示伺に關7
L性l:/J艮い液?塗1−1.1(よIH1箔カイカ
イトマーク3′θさせたとILll等のカイトマークに
ノー、呟かできゐO
(2) A friend who knows about the guide mark case, -: IJJ disappearance and kidnapping - regarding the inspection on the kite mark except for the st take 9.
L sex l:/J 议水? Coating 1-1.1 (Yo, IH1 foil kite mark 3'θ is no, I can't make it to the kite mark such as ILll.

【図面の簡単な説明】[Brief explanation of the drawing]

図面Vl多層印刷配耐&すFgr面図である0符号CI
)6兄明
0 code CI which is drawing Vl multilayer printing distribution & Fgr side view
) 6th brother Akira

Claims (1)

【特許請求の範囲】 1、 ガイドマーク及び必JAIな回路パターンケ肩す
る内層回路板(1)表面にガラスメ占利ノ゛リグレグを
介して銅箔又げカラス2!!j1片囲鉋j張槙層&會銅
紬が外面に配置さtIるL9にjl+ね付せ。 全体を加熱加圧積層一体化した伎、ザイドマータ土の銅
箔及び基JSノーtガイドマークを11」別し得る厚み
のガイドマークt゛こ接すゐ左材層ヶ残して除去し、カ
イトマーク會基準点として外向銅粕υ回陥加工ケ行うこ
とケ付徴とする多層印刷配線板の製造法。
[Scope of Claims] 1. Inner layer circuit board (1) on which guide marks and required JAI circuit patterns are carried (1) Copper foil straddled crow 2! ! Attach jl+ to L9 where j1 one side plane j tension layer & kai copper pongee are placed on the outer surface. The whole was heated and pressurized and laminated into one piece, and the copper foil and base JS notebook guide marks of 11" thickness were removed, leaving only the left material layer in contact, and the kite marks were removed. A method for producing a multilayer printed wiring board with an additional feature of performing an outward copper sludge turning process as a reference point.
JP15605082A 1982-09-08 1982-09-08 Method of producing multilayer printed circuit board Pending JPS5944895A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15605082A JPS5944895A (en) 1982-09-08 1982-09-08 Method of producing multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15605082A JPS5944895A (en) 1982-09-08 1982-09-08 Method of producing multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS5944895A true JPS5944895A (en) 1984-03-13

Family

ID=15619214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15605082A Pending JPS5944895A (en) 1982-09-08 1982-09-08 Method of producing multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS5944895A (en)

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