JPS5944666B2 - character reading device - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a character reading device, and more specifically, it has a function to prevent damage and danger caused by misreading by inspecting character quality at the same time as character reading. It relates to a character reading device.

A normal character reading device scans the characters written on a form etc. using a television camera, etc., and then determines the brightness of the image signal obtained by scanning between "'1" (dark part) and "'0"('0'). The quantized video signal is quantized into bright areas), this quantized video signal is processed to narrow it down to create a skeleton pattern, and features are extracted and recognized from this skeleton pattern according to a predetermined rule. In this type of character reading device, the above-mentioned feature extraction circuit and recognition circuit are arranged in tandem with each other in order to improve the reading rate of characters that have irregular shapes, poor printing, and other various deformation factors. Improvements have been made in line with the design policy of individually increasing the functionality of a limited number of circuits. The increase in power and the improvement in the functions of these individual circuits are accompanied by an increase in the price of the device and a decrease in processing speed, and there is a limit to the improvement in performance of the recognition device as a whole. In addition, with highly functional conventional devices, the main focus is to increase the reading rate, that is, to provide some kind of recognition result even for confusing characters. does not have any function to notify the outside. Figure 1 is a block diagram showing the configuration of a conventional device. 1 is a screen such as a form on which the characters to be read are drawn, and 2 is a television camera. 3 is a quantization circuit for video signals, 4 is a narrowing circuit for quantized video signals, 5 is a feature extraction circuit, and 6 is a recognition circuit.

These circuits are connected in series and operate as described above. FIG. 2 is a diagram showing an example in which misreading of characters occurs in the conventional device.

21 in the figure is the correctly printed alphabet ``P''
', 22 are characters printed with the lower part of 'P' faded, and 23 are characters printed with almost all of the part of 'P' missing.These characters 22 and 23 When read with a conventional character reading device, it will be read as the alphabet “D”, and an incorrect reading result “D” will be output as shown in 24. In this way, some of the characters may be There are many examples of misreading caused by omissions or blurring, even if it is limited to the alphabet, such as E (!: F,, B, or R and P. This can cause misreading. Printing defects are usually caused by some kind of defect in the printing mechanism itself, so incorrect readings are repeated over a long period of time until the defect is discovered, and it takes a lot of effort to correct the incorrect readings. In particular,
If the object to be read is a label attached to a medicine or dangerous substance, misreading may cause considerable danger. Therefore, one object of the present invention is to always check the reliability of reading by checking the quality of the characters to be read in parallel with character reading, and when the quality of the characters falls below a certain level, the reliability is checked. It is an object of the present invention to provide a reading device having a function of notifying the outside without performing low reading.

Another object of the present invention is to connect all the circuits for quality inspection in parallel with the circuits for reading.
It is an object of the present invention to provide a character reading device configured so that the operating speed of the reading device does not decrease. Further details of the present invention will be explained below with reference to embodiments.0 Fig. 3 is a block diagram of an embodiment of the present invention, and the same reference numerals as in Fig. 1 refer to the same reference numbers as those in Fig. 1. It is the same circuit as the one.

30 is a character quality inspection circuit which returns the inspection result to the recognition circuit 6 via a signal line 35, and when the character quality falls below a predetermined level, invalidates the recognition result and performs a parallel operation. The quality of the test result is notified to the outside by printing or the like via the signal line 36 or independently.

The inspection circuit 30 is comprised of a character height inspection circuit 31, a line width inspection circuit 32, a flaw inspection circuit 33, and an OR gate 34 for performing OR logic on the outputs of these circuits.
FIG. 4 is a block diagram of one embodiment of the character height inspection circuit 31, in which 40 is a shift register, 41 is an OR gate, and 42 is a block diagram of an embodiment of the character height inspection circuit 31.
is an AND gate, 43 is a horizontal synchronization signal input terminal, 4
4 is a pulse counter, and 45 is an input terminal for a vertical synchronizing signal.

The pixel signal "11" or "0" of the character pattern divided into grids by the quantization means 3 is input to the shift register 40, and is input into the shift register 40 every time the scanning circuit 2 shown in FIG. 3 scans one pixel. The pixel signal is advanced one bit at a time. When one horizontal scan from left to right by the scanning circuit 2 is completed, the pixel signal from one horizontal scan is set in the shift register 40. The signal of each bit of the shift register 40 is input to the OR gate 41, and this OR logic output is input to the gate 42.The input terminal 43 of the gate 42
A horizontal synchronizing signal is applied to each horizontal scan, and therefore, the OR logic output of all the pixel signals in the shift register is input to the pulse counter 44 every horizontal scan. The pulse counter 44 counts the output pulses of the AND gate 42 while vertical scanning is being performed from top to bottom, and when the vertical synchronizing pulse is input to the input terminal 45, the counted value exceeds a predetermined value. For example, when an overflow occurs, the logic “O” indicating that the test result is good is determined based on the fact that the
”, and the logical “” indicating that the result is bad when no overflow occurs is the OR gate 34 in FIG. 3.
The configuration can be configured to output the count value and clear the count value. Therefore, if a force deviation or chipping occurs in the character to be read due to a printing defect, the input pulse to the counter 44 is interrupted or the continuous period is shortened, so that an overflow exceeding a predetermined count value does not occur and the character is read. The height is defective.
The D signal is output to OR gate 34 in FIG.

Instead of using the counter, a configuration may be adopted in which interruptions in the output pulses of the AND gate 42, which should normally be continuous, are detected during continuous horizontal and vertical scanning. Such a circuit can be easily constructed by a combination of a one-shot multi-type timer circuit and an AND gate. Fifth
The figure is a block diagram of one embodiment of the line width inspection circuit 32.
,52,...55 is a shift register, 56,5
7, 58, 59 are delay circuits, 60 is an AND gate, 6
1 is a pulse counter. The pixel signal of “1” or “0” output from the quantization means 3 is transferred to the shift register 5.
1, and is shifted by 1 bit each time the scanning circuit 2 shown in FIG. 3 scans one pixel. The last bit signal of shift register 51 is input to shift register 52 through delay circuit 56. Furthermore, the delay time of the delay circuit 56 is set so that the time taken to pass through the shift register 51 and the delay circuit 56 is equal to the time required for the scanning circuit 2 of FIG. 3 to horizontally scan once from left to right. shift register 52
and a delay circuit 57, a shift register 53 and a delay circuit 58,
Shift register 54, delay circuit 59, shift register 5
5 are connected in sequence, and each delay time is set so that the time required for passing through these shift registers and delay circuits is equal to the time required for one horizontal scan by the scanning circuit 2. With the above configuration, the signals of each bit of the shift registers 51 to 55 are arranged adjacent to each other on the actual character, for example (
5×5=)25 pixels. When the center point (pixel) of the above 5x5 mesh and the surrounding points V1 to V24 are input to the AND gate 60, if all 25 pixels are "D", that is, the line width of the character is 5 pixels or more, In this case, the AND gate 60 outputs the signal ゜“D゛.

When a pixel signal for one character is input to the line width inspection circuit 32 configured in this way, the counter 61 counts the locations where the line width is 5 pixels or more, and if this count value is greater than a predetermined value, the line width is For example, the counter 61
When the count exceeds a predetermined value, an overflow occurs, and when a vertical synchronizing signal is input to the input terminal 62, a "D" signal indicating a line width defect is output to the OR gate 34 in FIG. 3, and the counted value is cleared. It can be configured as follows.
FIG. 6 is a block diagram of one embodiment of the flaw inspection circuit 33, in which 71, 72, 73 are shift registers, 74, 75 are delay circuits, 76 is an OR gate, 77 is an AND gate,
78 is a pulse counter.

The operation of this test circuit will be explained with reference to the conceptual diagram of FIG. From the quantization circuit 3, for example, the letter "C" 81 (FIG. 7) in the alpha alphabet is inputted to the thinning circuit 4, and the core pattern 82 (FIG. 7) created through thinning processing is input to the shift register 71. is input. The pixel signal of "D" or "0" input to the shift register 71 is advanced one bit at a time in the shift register in synchronization with the narrowing circuit 4 sending out one pixel.The last bit signal of the shift register 71 is input to the next stage shift register 72 through the delay circuit 74.
1, the time to pass through the delay circuit 74, and the scanning circuit 2 in FIG.
The delay time is set so that the time required for one scan from left to right is equal to the time required for one scan from left to right. Shift register 72 and delay circuit 75
The same applies to With this configuration, the signals of each bit of the shift registers 71, 72, and 73 are made to correspond to nine (3×3=) pixels adjacent to each other on the actual character. When the center point Vx of the 3×3 mesh and the four points V1 to V4 closest to it are input to the OR gate 76 and their logical sum is taken, the output is the character 8 in FIG.
As shown in FIG. 3, the original core pattern 82 is uniformly enlarged.

The output of the OR gate 76 and the pixel signal before the narrowing process are input to an AND gate JMOV to perform AND logic. And Gate J Mo V only exists when the character 81 before thinning is thinner than the character 83 which is uniformly enlarged after being thinned once, that is, the hatched part 84 in Fig. 7 exists. The counter 78 counts the output pulses of the AND gate JMOV, and determines that the flaw inspection result is defective when the counted value exceeds a predetermined value. For example, counter 7
8 counts over a predetermined value, causing an overflow, and when a vertical synchronizing signal is input to the input terminal 79, a "D" signal indicating a defective flaw inspection result is sent to the OR gate 3 in FIG.
It is possible to have a configuration in which the count value is output to 4 and the count value is cleared. The embodiments of the present invention have been described above with respect to a configuration in which each inspection circuit has its own dedicated shift register, but the narrowing circuit 4 uses the shift register originally provided in the circuit for character recognition, and the shift register It is possible to adopt a configuration in which the signal is inputted to the aforementioned OR gate 41, AND gate 60, etc.

In this way, if the configuration is such that the circuit components for recognition and the circuit components for quality inspection are shared, the character reading device It is possible to achieve an expansion of the functions of Furthermore, as described above, since the circuit for quality inspection is connected in parallel with the circuit for recognition, there is no reduction in the operating speed of the character reading device. Note that the scanning means used in the character reading device of the present invention may be a television camera, an area type diode array camera using a semiconductor photoelectric conversion array, or a document, label, or container on which characters to be read are printed. If the object is moving at a constant speed, a linear diode array camera may be used as the input means.

In addition to characters, the objects to be read include similar symbols,
It may be a symbol or something else. According to the character reading device of the present invention, it is possible not only to effectively avoid damage and danger caused by misrecognition that occurs when the quality of the characters to be read falls below a predetermined level, but also to effectively avoid the damage and danger caused by misrecognition. It is possible to quickly take measures against mechanical failures, etc., and therefore the effect is great.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional character reading device, and Fig. 2 is a conceptual diagram for explaining the operation of the conventional example shown in Fig. 1. , FIG. 3 is a block diagram of one embodiment of the present invention, FIGS. 4, 5, and 6.
The figures are block diagrams of one embodiment of the character height inspection circuit 31, line width inspection circuit 32, and flaw inspection circuit 33 shown in FIG. 3, respectively, and FIG. 7 is a conceptual diagram for explaining the operation of the embodiment of FIG. 6. It is a diagram. 1...Screen, 2...Scanning circuit, 3...
...Quantization circuit, 4...Narrowing circuit, 5...
...Feature extraction circuit, 6...Recognition circuit, 30
...Character quality inspection circuit, 31...Character height inspection circuit, 32...Line width inspection circuit, 33.
:...Flaw inspection circuit, 34, 41, 76...
Or Gate, 40, 51-55, 71-73...
...Shift register, 56-59, 74, 75...
...Delay circuit, 44, 61, 78... Pulse counter, 42, 60, 77... AND gate.

Claims (1)

[Claims] 1. Input means for scanning characters to obtain a video signal; quantization means for quantizing the video signal into "0" and "1" signals to obtain a quantized video signal; a character recognition means for performing recognition of the character recognition means; A character reading device comprising character quality inspection means having one or both of the functions for notification.