JPS5943753B2 - Display method on cathode ray tube display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cathode ray tube display device, in which particularly minute display information can be written at any position on the screen, and characters, figures, etc. displayed on the screen can be edited. The present invention relates to a display method for a cathode ray tube display device.

More specifically, the present invention divides a scanning line into a large number of picture elements, controls the brightness of each picture element, and uses a plurality of vertical and horizontal picture element matrices to display characters, figures, etc. The present invention relates to a cathode ray tube display device that forms an image and displays it on a screen.

Generally, this type of device has a one-on-one relationship with each of all picture elements on the screen.
The refresh memory (or pattern memory) corresponding to each storage address is read out in synchronization with the raster scanning of the cathode ray tube, and all information stored in this memory is displayed on the screen.

Writing and erasing information displayed on the screen is performed directly on the screen using, for example, input keys or a light detection device called a light pen. The present invention aims to provide a cathode ray tube display device that can be applied to a device in which writing and erasing of information is performed in units of minute picture elements on the screen, especially when writing and erasing information with a light pen. .

Conventionally, when writing or erasing information directly on the screen using a light pen, the light pen first detects raster light, and when obtaining this detection output, the information on the screen is generally refreshed. The position of the light pen on the screen is determined by latching the count value of the address counter.

The count value of this address counter corresponds to the picture element on the screen. Therefore, when writing and erasing information on the screen pixel by pixel using a light pen,
The raster light that traverses the raster light sensing range or field of view of the light pen must be correspondingly very fine so that the position indicated by the light pen does not shift.

On the other hand, in order to make the above-mentioned position determination accurate, it is necessary to make the detection output of the light pen stable. In order to stabilize the detection output of this light pen, it is desirable to widen the field of view of the light pen. Therefore, the field of view of a light pen is usually wide enough to detect several picture elements. As a result, the pixels are made even finer to increase the amount of information displayed on the screen, while the number of pixels detected by the light pen increases to stabilize the detection output. Therefore, even a slight shift of the light pen causes the above-mentioned count value for determining the position to change. Therefore, writing and erasing on a pixel-by-pixel basis is difficult because the position of the pixel tends to shift. In addition, the finer the picture elements and the denser the picture elements displayed on the screen, the more precise the movements of the hand that operates the light pen are required, but in reality, the hand cannot move with precision. Can not. As a result, the smaller the picture elements are made to increase the amount of information displayed on the screen, the more difficult it becomes to write and erase each picture element. In particular, all the information displayed on the screen is divided into 15 characters horizontally and 8 lines vertically, with 256 dots (picture elements) horizontally and 1 vertically, as shown in Figure 1.
If it is something that is displayed with 92 lines,
One character is displayed within a block formed by 16 horizontal dots and 24 vertical lines, and when writing characters with fine lines such as kanji in this display area, the position of the light pen is determined by the angle of the pen, etc. This made it more likely to shift, making it difficult to write accurately.

The present invention has been made in view of this point, and the picture elements for one character described above are enlarged and displayed on the same screen, and on this enlarged screen of the cathode ray tube, writing and erasing, in other words, correction of lines. After doing this, switch the display to the screen where all the information is displayed again, and transfer the display information on the cathode ray tube screen to the display storage area for one character at the appropriate position on this screen. The present invention aims to provide an optimal display method when applied to a cathode ray tube display device that can be edited. Therefore, an object of the present invention is to provide a device in which there is a relative relationship between the size of one pixel and the field of view of a light pen, so that writing and erasing can be performed accurately in minute units of one pixel. The object of the present invention is to provide a display method that can be applied to a cathode ray tube display device.

Another object of the present invention is to write and erase information directly on the cathode ray tube screen on which all information is displayed, and to divide the displayed information into a plurality of regular and appropriate blocks.
Pixel block For example, information for one character is enlarged and displayed on the same cathode ray tube screen, the image is corrected or new writing is performed on this enlarged cathode ray tube screen, and the information is displayed again on the screen where all the information is displayed. The object of the present invention is to provide a display method that can be applied to a cathode ray tube display device that can transfer images to the display area of a pixel block at any position on a cathode ray tube screen that has been switched.

Another object of the present invention is to maximize the display area of a vertically long one pixel block on the horizontally long display screen of a cathode ray tube without changing the total number of pixels included in this block. It is in. Another feature of the present invention is that the display area of one pixel included in a pixel block is enlarged while maintaining the aspect ratio of the pixel block before the enlarged display, and the enlarged one picture By establishing the relationship that the display area of an element is 2n (n is an integer) times the display area of one pixel before being enlarged, address data for each pixel before enlargement and enlargement can be created. The advantage is that the address counter can be composed of one common counter.

The present invention will be explained below with reference to the drawings.

FIG. 2 is a block circuit diagram showing the configuration of an apparatus according to the present invention, in which 1 is a cathode ray tube, 3 is a central processing unit (hereinafter simply CPU).
4 is a light pen, and 5 is a key switch for applying a plurality of key inputs to the embodiment device as shown in FIG. The cathode ray tube 1 also has a first memory in which all the information displayed on the screen is stored, namely a pattern memo 1, a parallel/serial data converter 12, and a parallel/serial data converter 12.
) bus buffer 13, (1) selector 14, and a second memory, in which information for one character, for example, obtained by dividing the information displayed on this screen into predetermined regular picture element blocks, is stored, that is, a memory in this case. The cathode ray tube display unit is composed of the character memory 21, the parallel/serial data converter 22, (2) the bus buffer 23, (2) the selector 24, the switching circuit 16, the output amplifier 10, and the deflection circuit 17. . In the pattern memory 11, each storage address has a one-to-one correspondence with each of all picture elements on the screen of the cathode ray tube 1, and reading is performed in synchronization with raster scanning of the cathode ray tube 1. On the other hand, in the character memory 21, each storage address is one-to-one with each pixel of a one-pixel plotter into which pattern memory information is divided.
Correspondingly, readout is similarly performed in synchronization with the raster scanning of the cathode ray tube 1. The output of the parallel/serial data converter 22 and the output of the parallel/serial data converter 12 are connected to the input of the switching circuit 16 . This switching circuit 16 is CP
According to the command from U, refresh display data of the information stored in the character memory 21, which is the output of the parallel/serial data converter 22, and refresh display data of the information stored in the pattern memory 11, which is the output of the parallel/serial data converter 12. To selectively switch and output only one of refresh display data of information. As a result, the stored data of the character memory or the stored data of the pattern memory selected by the switching circuit 16 is refreshed and displayed on the screen of the cathode ray tube 1. Furthermore, data stored at each address of the pattern memory 11 is inputted and outputted via (1) a bus buffer 13, and address data is supplied from (1) a selector 14. On the other hand, in the character memory 21, data stored at each address is inputted and outputted via (2) a bus buffer 23, and address data is supplied from (2) a selector 24. Here, the pattern memory 11 displayed on the cathode ray tube 1
The total information stored in the screen is as shown in FIG. 1, and an example will be given in which all the picture elements to be displayed are regularly divided into one block of 16×24 dots.

Therefore, when one block of all information is enlarged and displayed on cathode ray tube 1, the total number of picture elements is 16 as shown in Figure 3.
x24 dots. In addition, here, the pattern of characters etc. displayed on one block is the area shown by diagonal lines in Figure 3,
A total of six lines (three lines above and below) and the first dot are used as margins for distinguishing patterns between adjacent blocks. Reference numeral 6 in FIG. 2 denotes a synchronization signal generator, which generates a vertical synchronization signal (hereinafter simply referred to as VD) and a horizontal synchronization signal (hereinafter simply referred to as HD) for the cathode ray tube 1 based on the clock signal output from the oscillator 60. Composite synchronization signal C. SYNC and
Create and output a blanking pulse BLK.

A clock generator 7 generates and outputs a dot clock CP corresponding to the picture element of the pattern memory displayed on the cathode ray tube 1 from a clock signal. 15 is a pattern address counter, which corresponds to the above-mentioned VD, HDl dot clock C.
P is input, and by counting HD with D as a reference, each storage address of the pattern memory 11 and character memory 21 corresponding to the pixel position in the screen vertical direction (hereinafter referred to as the Y direction) of the cathode ray tube 1 is represented. By counting the Y address counter that outputs memory Y address data and the dot clock CP (for example, 5.73 MHz) with HD as a reference, a pattern corresponding to the pixel position in the screen horizontal direction (hereinafter referred to as the X direction) is calculated. It is composed of a memory 11 and an X address counter that outputs memory X address data representing each storage address of the character memory 21.

The Y address counter output is supplied to the selector 14 (1) in 8 bits in parallel as Y address data for pattern memory refresh, and is also supplied to the latch circuit 41 at the same time. The lower 5 bits of the Y address counter output are used as Y address data for character memory refresh (
2) supplied to the selector 24; On the other hand, the upper 5 bits of the X address counter output are supplied to the selector 14 (1) as X address data for refreshing in 8-bit units of the pattern memory, and the upper 2 bits are supplied as X address data for refreshing in 8-bit units of the character memory. (2) Supplied to the selector 24. Further, the 8-bit X address counter output is supplied to the latch circuit 41. The above-mentioned (1) selector 14 and (2) selector 24 are connected to the address bus AB from the CPU, which will be described later, as the other input.

The (1) and (2) selectors 14 and 24 select one of the two inputs using the blanking pulse BLK. That is, during the screen refresh display period, in other words, during the non-blanking period, (1) the selector 14 inputs the memory X and Y from the address counter 15;
Address data input is selected and supplied to pattern memory 11. During the same period, (2) the selector 24 selects the memory X and Y address data input from the address counter 15 and supplies it to the character memory 21; At this time, (1) the bus buffer 13 and (2) the bus buffer 23 are
Since the chips are not selected, the bus and ports leading to the data bus DB are maintained at high impedance. Therefore, during the above display period, the memory X and Y address data supplied from the address counter 15 are (1) given to the pattern memory 11 via the selector 14, so that the data at the storage address corresponding to the address data is (here, data in units of 8 bits) is output to the data bus.

Similarly, the character memory 21 is given the memory X and Y address data supplied from the address counter 15, and the data at the storage address corresponding to the data (
Similarly, data (in 8-bit units here) is output to the data bus. The data output to these data buses 1 and 2 are respectively output to parallel/serial converters 1 and 2, as is well known.
loaded into shift registers forming 2 and 22;
1 from this by dot clocks CP and XC2 (third output from the bottom of the X address counter), respectively.
It is read out pixel by pixel.

The read data is input to two input terminals of the switching circuit 16, and only one input selected by a command from the CPU is output as is, and the other input is cut off. This switching circuit 16 can be realized by a circuit including a flip-flop 16a, an AND gate 16b, and a 16c1 OR gate 16d as shown in FIG. That is, one input of the AND gate 16b is connected to the parallel/serial data converter 12 that outputs pattern display data, and the other input is connected to the flip-flop 1.
6a0Q output is connected. Therefore, when the Q output of this flip-flop 16a is 1) and is at the low level V1, the pattern display data passes through the AND gate 16b,
It is supplied to the output amplifier 10 through the OR gate 16d. A parallel/serial data converter 22 that outputs character display data is connected to one input of the AND gate 16c, and a flip-flop 16a (7) is connected to the other input.
Q output is connected. Therefore, when the flip-flop 16a0)Q output is at high level 1, the character display data passes through the AND gate 16c and is supplied to the output amplifier 10 through the OR gate 16d. The data input terminal of the flip-flop 16a is connected to the data bus DB, and the clock input terminal is connected to the output of the address decoder 1. When the Q output is set to high level 11 by a command from the CPU, high level 1 is supplied to the data input terminal of the flip-flop 16a through the data bus DB, and this low level F1 signal is supplied to the address decoder ( 1) It is sufficient to capture the data at the timing of the output signal. The flip-flop 16a then
In order to maintain the same state until a switching command is received from the PU, the pattern display data supplied from the parallel/serial data converter 12 by its Q output passes through the gate and is supplied to the output amplifier 10, where the cathode line The signal is amplified to drive the tube 1, is supplied to the cathode of the cathode ray tube 1, and is displayed as a bright spot on the screen. When the power is turned on, each part of the apparatus of this embodiment is set to an initial state, and thereafter the control processing of each part is started by key inputs using the keyboard switch 5 and the light pen 4 as shown in FIG.

Therefore, the main routine of the CPU 3 is programmed to be based on key input. The key inputs shown in FIG. 5 are 1 whole T5 and 1 part 1 key switch and 1W write - 1 erase? f? 1 editing 11 are independent from each other, and one of the two switches is selected from each other.

In addition, when one of the key switches for the "1 whole 17" and "part 11" screens is selected, the other is released.
1! Write-71 erase! Each of the key switches in ``, 11 Edit 1 is also configured to release the others by being pressed alternatively.Thus, these switches switch to the corresponding mode by being pressed. The keyboard switch 5 shown in FIG. 2 instructs the CPU 3 to execute the process in response to such key inputs.In other words, the keyboard switch 5 shown in FIG. When 5 is pressed, a key press flag is set, and the main routine of the CPU is set in advance to search for this flag, and the binary code data of the corresponding switch translated by the encoder 51 is sent to (4) the bus buffer 52 and the data bus DB. Based on this data, the CPU 3 determines which key input is to be input and executes it.The key inputs given to the CPU 3 are organized as follows.

First, when writing directly into the pattern memory 11 displayed on the screen of the cathode ray tube 1 with the light pen 4, the fifth
Writing is performed on the corresponding picture element by pressing the keyboard switch 11 shown in the figure, then pressing the keyboard switch 1W for 1W writing, and applying the light pen 4 to the screen of the cathode ray tube 1. Further, when writing to the character memory 21 displayed on the screen of the cathode ray tube 1, all that is required is to press the keyboard switch of the 1W portion 11 described above, and the subsequent operations are performed in the same manner.

As already mentioned, ′! This is because the keyboard switch for write 11 maintains its previous state. When erasing picture elements on the cathode ray tube 1, select the erasure memory displayed on the cathode ray tube 1! This is done by selecting the whole 11 part 51 with the keyboard switch and switching the key switch of 15 writing "1" mentioned above to f1 erasing 51. Next, the data is displayed and drawn on the screen of the cathode ray tube 1. To transfer the information in the character memory 21 to any one block in the pattern memory 11, first press the keyboard switch for 1 section 11, and then press the keyboard switch for 1"edit 1. At this time,
By inputting data of 1 high level 11 to the flip-flop 16a of the switching circuit 16 in response to a command from the CPU 3 according to the program, the Q output is set to low level 11,
Project pattern display data on the entire screen. By applying the light pen 4 to one block on the screen of the cathode ray tube 1 on which the pattern display data is projected, the block at the position specified by the light pen 4 is placed on the screen before pressing the 1W Edit 1 key. The image data displayed in the character memory 21 is transferred. Conversely, when the image data of one block of the pattern memory 11 displayed on the screen of the cathode ray tube 1 is transferred to the character memory 21 and only that one block is enlarged and displayed on the screen at the same time, the entire 11 is transferred. 1
This is done by pressing the V keyboard switch, pressing the 1W editing 1 keyboard switch, and applying the light pen 4 to a desired block on the screen of the cathode ray tube 1.

At this time, the image data of one block in the pattern memory 11 corresponding to the position indicated by the light pen 4 is transferred to the character memory 21, and at the same time, by switching the switching circuit 16, the character display data is enlarged and displayed on the screen. do. Also, the moment the character display data is enlarged and displayed by the program, the entire 1V selected earlier is 1!
1 edit il key is each il part! Fushi! 1 write q Switched to key 1. Based on the key inputs for the operations described above, the CPU 3 controls each section and connects the data bus D.
B and address bus AB are processed, and since the write operation to the character memory 21 is almost the same as the write operation to the pattern memory 11, this will be explained below.

When the light pen 4 is applied to the screen of the cathode ray tube, it detects raster light scanning the screen in a well-known manner and generates pulses.

Therefore, the sensing output or pulse output from the light pen 4 is generated when the raster light passes within the field of view. As already mentioned, the address counter 15 supplies the memory X and Y address data to the latch circuit 41, so when it receives the detection output from the light pen 4, it latches the supplied address data.

Since this memory X and Y address data indicates the horizontal and vertical positions of picture elements on the screen, the data latched by the latch circuit 41 becomes data indicating the position on the screen where the light pen 4 is applied. . The data latched by the latch circuit 41 is transferred to pattern memory address data (3) that specifies the storage address of the corresponding pattern memory 11.
) to the bus buffer 42. The (3) bus buffer 42 is opened by a command from the CPU 3, and drops the above-mentioned pattern memory write address data onto the data bus DB. The command from the CPU 3 here consists of 16-bit parallel address data and is output to the address bus AB. For example, if (3) address data for selecting bus buffer 42 is output to address bus AB, this address data is decoded by (2) address decoder 32 and sent to (3) bus buffer 42 via line 451. Let it open. This (3
) The timing for opening the bus buffer 42 is here performed at the same time as the timing for reading the memory. CPU3
(3) Opens the bus buffer 42, takes in the memory address data carried on the data bus DB, and stores it in a predetermined built-in register. This operation of the CPU 3 is performed in sequence in a short period of time. Based on this captured memory address data, the CPU 3 outputs memory address data representing the corresponding storage address of the pattern memory 11 to the address bus AB, and this data is (1) supplied to the pattern memory 11 via the selector 14; be done.

At this time, the CPU 3 sends a memory write control signal to the line 31 representing the writing timing of the pattern memory 11.
1 to the read/write terminal of the pattern memory 11 to put the memory into a write state. at the same time,(
1) The bus buffer 13 is opened, and the write data stored in the CPU 3 described above is supplied to the pattern memory 11 on the data buses DB and A. Writing to the pattern memory 11 is completed as described above, and instructions for writing and reading from this memory are executed by the CPU 3.

This command from the CPU 3 is executed during the blanking period so that refresh data and external write data do not collide on the data bus DB. If it is a color display device using a color cathode ray tube, this writing operation will be performed for red, green,
This will be repeated three times, each corresponding to blue. The write operation of the pattern memory 11 has been described above, but the write operation of the character memory 21 is performed in the same way.

In this case, the light pen 4 is applied onto the screen of the cathode ray tube 1 as described above, and the operations of the latch circuit 41 and (3) bus buffer 42 are the same as in the case of the pattern memory 11 described above. The response is slightly different. That is, the lowest 5 bits of the latched Y address counter output are used as the Y address for writing to the character memory 21, and the upper 4 bits of the output of the X address counter, excluding the most significant bit, are used as the X address for writing to the character memory 11 in the CPU 3. Incorporate into. The following write operation is the same as that for the pattern memory 11. Next, an explanation will be given of the operation when information drawn on the screen of the cathode ray tube 1 by writing into the character memory 21 as described above is transferred to one block of the pattern memory 11.

In this case, CPU3, as already mentioned, 1W part 1
5 and! Key input by the keyboard switch of 1 editing 1f is given. ``Part 1!→11 Edit 15 The operation of the CPU 3 by the key input is performed by the switching circuit 1 as already mentioned.
6 controls the pattern memory data to be displayed and output, and the detection output of the light pen 4 is output to the address counter 15.
The program is configured to cause the latch circuit 41 to latch the memory X and Y address data of the pattern memory 11, and (3) to take in the address data of the pattern memory 11 from the bus buffer 42. On the other hand, the CPU 3 is provided with pattern memory address data that is regularly divided into predetermined blocks in advance, and when it receives the key input of "5 edit 1?", it executes a predetermined routine (3).
It calculates which plotter the memory address data fetched from the bus buffer 42 belongs to and outputs it to the address bus AB as block address data. As a result, the pattern memory 11 is addressed in block units at the corresponding storage address. Here, one block is shown as being divided into one character of 24 lines and 16 dots, as shown in FIG. Therefore, 1
When the key input for 1 editing V1 is given to the CPU 3 and the light pen 4 is applied to the 1 plotter of the pattern memory 11 displayed on the screen of the cathode ray tube 1, the pattern memory address data indicating the position in 1 bit units is displayed as (3). bus bus 42
It is taken into the CPU 3 and stored.

Then, the CPU 3 stores the pattern memory 11 corresponding to the plotter to which the position indicated by the light pen belongs, as described above.
The data stored in the character memory 21 is sequentially transferred to the storage address of. At this time, the data in the character memory 21 to be transferred is transferred from the data input/output terminal to the mechanical DB.
- It is written into the pattern memory 11 along the path of Iha.
The operations of the various parts that control the data transfer and the flow of address data as described above are carried out from the CPU 3 to the address bus AB.
It is executed by the command output to .

This order of execution is determined by a routine preset in the CPU 3. The case where the image data of the character memory 21 enlarged and displayed on the cathode ray tube 1 is transferred to any one tank of the pattern memory 11 has been described above, but each part operates in the same manner in the reverse case.

In this case, 1! Part 1 key input for entire q1! This is executed by switching to key input 5 and placing the light pen 4 on the plotter to which the pattern memory data displayed on the cathode ray tube 1 is to be transferred in the same manner as described above. The keyboard switch operation explained above is performed by CPU3.
This can be changed as appropriate by changing the routines that are set up. Therefore, 11 whole 1111 part 11
Even if a single switch is used instead of the keyboard switch to instruct the transfer from the character memory 21 to the pattern memory 11 or vice versa, this does not affect the spirit of the present invention. Although the present invention has been described above with reference to a black and white cathode ray tube display device, the present invention can also be applied to a color cathode ray tube display device.

In this case, the memory capacity may be tripled for red, green, and blue, and the same operation as described above may be performed for each of the three primary colors. In addition, the present invention can be used to write and erase information directly on the screen of a cathode ray tube on which all information is displayed, and to divide this displayed information into a plurality of regular and appropriate blocks. The information is enlarged and displayed on the same cathode ray tube screen, and the image is corrected or new information is written on the enlarged cathode ray tube screen.
The explanation has been given with reference to an example of a cathode ray tube display device in which the display can be transferred to the display area of one pixel block at any position on the cathode ray tube screen, and the display is switched to the screen where all information is displayed again. The display method of the present invention can be applied even when there are two cathode ray tubes or even when the device does not have a transfer function.

As described above, according to the present invention, a scanning line is divided into a large number of picture elements, the brightness is controlled for each picture element, and a character such as "5:0" is displayed using a plurality of vertical and horizontal picture element matrices. In a cathode ray tube display device that displays images such as figures on the screen, the total number of picture elements included in the horizontally long display area of the cathode ray tube is divided into regular plurality of vertically long display areas, with a certain appropriate number of picture elements as one unit. Divide into picture element blocks, and keep the aspect ratio of each picture element block constant.
Enlarged display is performed in a horizontally long display area of the cathode ray tube without changing the total number of pixels included in the picture element block, and during this enlarged display, the display area of one pixel when the enlarged display is performed is expanded. The total vertical number of pixels before being enlarged and displayed in the horizontally long display area is 2n (n is an integer) times the display area of the previous one pixel, and the maximum magnification is the vertical number of pixels of the one pixel block. The purpose of the present invention is to provide a display method for a cathode ray tube display device having a relationship of multiplying the square of the value divided by the total number of picture elements.

[Brief explanation of drawings]

1 is a diagram showing an example of the display format of the present invention, FIG. 2 is a block circuit diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a diagram showing an example of the enlarged display format of the present invention. FIG. 4 is a circuit diagram of the main parts of the present invention, and FIG. 5 is a diagram showing an example of the configuration of the key input means of the present invention. 11, 12, 13...first memory means, 21,
22, 23... second memory means, 10, 16...
...Switching means, 4, 41, 42, 15...
Position detection means, 15, 3, 31, 32... Discrimination means, 4, 41, 42, 3, 13, 23... Circuit means, 14, 24, 42, 3, 31, 32...
・First transfer means, 14, 24, 42, 3, 31, 32・
...Second transfer means, 5, 51, 52, 3, 31,
32... Command means.

Claims (1)

[Claims] 1. A cathode ray that divides a scanning line into a large number of picture elements, controls the brightness of each picture element, and displays images of characters, figures, etc. on the screen using a plurality of vertical and horizontal picture element matrices. In a tube display device, the total number of picture elements included in a horizontally long display area of a cathode ray tube is divided into a plurality of regular vertically long blocks with a certain appropriate number of picture elements as one unit, and each picture element block is divided into a plurality of regular vertically long blocks. While keeping the aspect ratio constant, the total number of pixels included in this one pixel block is enlarged and displayed in the horizontally long display area of the cathode ray tube, and during this enlarged display, the The display area of one pixel is a predetermined multiple of the display area of one pixel before being enlarged, and the maximum magnification is the vertical area included in the horizontally long display area before being enlarged. A display method for a cathode ray tube display device having a relationship such that the total number of picture elements is divided by the total number of vertical picture elements of the one picture element block times the square of the value.