JPS5943651A - Data transmission system - Google Patents

Abstract

PURPOSE:To improve the data transmission efficiency, by transmitting a transmission signal having a prescribed bit number comprising an address of a destination and a data from one of plural independent nodes to all nodes in parallel via a communication managing device. CONSTITUTION:The nodes 10i (i=1-n) performing plural independent processings and the communication managing device 11 are connected with a read bus 12 and a write bus 13. Each node has an input stack 16i of plural-stage constitution stacking a transmission signal comprising a token having a prescribed bit number to the 1st stage. The device 11 designates one of plural nodes, the token having a prescribed bit number comprising the address of destination and data representing the node to be transmitted is transmitted from the node to the device 11 in parallel via a bus 12, and the device 11 supplies the transmitted token to all nodes in parallel via a bus 13. Each node compares the address of the transmitted token with the own address at a comparator 15i, the coincident token is stacked in the stack 16i and a CPU18i processes this data.

Description

DETAILED DESCRIPTION OF THE INVENTION The fourth aspect of the present invention relates to a take transmission system, in which an input stack is provided to each of a plurality of nodes, and a certain number of transmission signals are transmitted in parallel from a node designated by a communication management station. The handshake between the i31N 1t11,1 and the received (11 nodes) The purpose of the present invention is to provide a take transmission system with short transmission time and no battle time.

In general, networks that connect multiple processors
When performing take transmission in the system, the transmission signal was transmitted serially. This transmission (m number is Pi 51 from header 1. destination address 2, text start 3. data 4. text end 5, as shown in Figure 1), and this transmission signal is transmitted repeatedly by C''. However, the time required to transmit information other than theta 5, which is originally important transmission information, was a battle, and the transmission time became long.In addition, parallel transmission was performed in units of several bits compared to conventional methods. However, this set of transmission signals is shown in Figure 2.
(f141 signal 8.Data 91) forms an IA communication packet (1.j) and transmits this communication packet in a defined manner.However, this platform also has a destination address 6, a source address 7, and a control signal. The time to transmit 8 is a battle,
This had the disadvantage of wasting time and wasting time.

Fujomei is a version that eliminates the above drawbacks, and it is one of the solutions shown in Figures 3 and below. 51・a per 11.

FIG. 3 shows a block diagram of an embodiment of the take transmission system according to the present invention. In the figure, 101 to IQ (n is a positive integer are nodes, 11)
'Atonement, and these nodes 10. ~10117&-bi song/f correction pipe lψ installation: ;& 11 is the address or 'j
(Nodes 101 to 10n (!: The communication tube silicon device 11a's l'rtl I/''IIIJ-de bus 12 and write bus 13 are connected to Wtt. corresponds to the negative W 4171!70, for example, it is made up of 16 bits (4), and 14a of these 16 bits is a 1-bit bit used to identify whether the transmitted data is a valid take or an invalid take. Act pick 1-, even if (the value of the set of control data is "1").Also, 14b indicates whether the take is a numerical data or an instruction to another no-1'. persimmon 6
j5 - 3 bit tough for Hoe distinction, 1
4clt This data is the 4-bit destination address indicating the destination, and 14dlj is the operand for the 8-bit take of the 61-bit data or other node. Transmission information is read bus 12. Light bus] 30 above 4th! Transmit data in units of 16 bits as shown in Figure 9.Hereafter, the 16 bits shown in Figure 4 will be transmitted as 1 - Kun]4
And To-1.

Nodes 10, ~10n are all internally related to one controller, and one of them is node 10□. The 0-ratio conversion profit 15□ supplied to the 161 compares the destination address 14c of the supplied token j4 with the address of the white star note 101, and only when they match, sends a "1" signal to the AND circuit 171. One input terminal of
Supply to □. A write signal is sent from the communication device 11 to the input terminal of the AND 1.1 Raku 171 and F5, and the output signal is sent to the input stack 16t +
:1. Input stack 161 (well, 1st level Iko1 I+
The number of stages that can be stacked in the 1-+ 1-kuntei stack is i: i C
P TJ 18. θ) which can be changed by
(1-kun 145-1 is given 1 by the light bus 13 that is at 4% control, stacks 1-kun 145-1, and stacks 1-kun 14) and stacks it to Ino J, the token CP from 14 to shellfish [supply to J181. CP
U18 is ratio gear 15. When the second mooring bow is rOJ, take the input stack 161 ζ
cormorant. Also, CPU 18. If there is an abnormality in the node 101 when 1.-4 is stacked on the total level of the input stack 161, then the auspicious "I'm going to stop it" will be uttered and this will be performed. Information management device 20 of Soharu 11 ((
supply Further, when a take to be transmitted occurs, the token 14 of this data is stored in the output register 1.91. When a polling pulse of 7fK is supplied from the timing pulse generation circuit 21 of the communication management device 11, this 114 output register 91 (sister 9.i) is stored. .tai--kun14
is output via the read bus 12 (intermediate U7). After this,
Lead bus 12 Sat token 14 is communication management% @ 1
Input/output in 1/H' to Sister 23, hold it, 4-skin monk''
'Br logic f ~ AND117 in 11] from path 22 -1' pulse -'i; When output, this read pulse f
)(supplied to CPU 181, (-P U IL, 1
1 + # output 1 no sister 9゜Act pick l□ 14a of token 14 in 1-0'', this token 14
(Correct :': 1 gun ゛1゛1 armor), !ir
That it was transmitted! -: Become. size, l5-1CP1,'
1.8 s ia order ζ (event sending - 4 power information (1--
(Ii, this is the act bit 'i l' 1 j l 1.y and the output L/register 91 (this is supplied.

i+′〈 に ]「li 471 pipe dri jl, j
i presentation 1d ψ 1 1 implausibility day 14 zuru
. ;1111-, f JiP-le gf
θ11's imminc pulse 1i'; output 1-IJ pulse from any one of 21. to 211 and 21. ., a borlink pulse is output from the output terminal 211. Then, the token 14 from the output register 9. of the node 10. is supplied to the read bus 121.
- Destination Al' + Female 1.4c in Kun 14 only;
It is supplied to two input terminals, C and C. D: The coater 24 reads the destination address 14c, and the destination address 14, C is the node 101 to 10.
When specifying the number 6-re of n, the part υ corresponding to this destination Atlus, see rlJ lucky number, comparator 20
7 White and Purpose 1. Address register 23 contains r Il. J and F6 Den]] 5. I
A word 11).

Hi Somu 20 is 1'jJf Notes 101 to 10, respectively, i list 11 - Eve-ke koi (L kanji sai 9ru!) 1 solid woman 4' □: `` old, iζ When there are 11 nodes that supply signals from the decoder 24 corresponding to these nodes 101 to 10n to each other, and both corresponding nodes are both 11''. The node pointed to by the long length L1 tt!a address 14C is token 1
Only when it is possible to receive 4, a coincidence signal of 1 and 7 is generated and supplied to the input terminal of the AND1 circuit 22 and the timing pulse generation circuit 21. After this, the timing pulse gate circuit 21 generates one read pulse, and when it is supplied to the - input terminal of the AND circuit 22, the signal is supplied to the input/output register 23t. 1-1 14 on 12 is connected to this input/output register 231
- Shake the ζ latch. Here, the input/output register 23 receives a control signal from the lever 924, which is [-1], that is, a token 14, or a communication'(l'fi).
! Device]. ], l) The latched I-kun 14 of the combination is supplied to the second instruction coder 25. If it is for a 1-kun 14 or a note, this latches and puni token 14 (1 write bus 13-kun).
At the same time, a timing pulse is generated [one write pulse from Idaji 21 is output from node 101 to
10,1 are supplied to the AND circuits 171-17n, and the token 14 of the write bus 13 is stacked on the input stack of the node pointed to its destination address 14c.

Here, each node 10□ to 10n can vary the number of stages of the respective input stacks 161 to 16n, and
: From the token 141, a command is transmitted to the communication tube 1jl captive 11. From this, it is possible to change the light receiving intensity of each of the notebooks 101 to 10n. In the case where node 10 manages devices that require high-speed input/output functions, node 1010) CPU
181 is no F Hl, 6δ order to investigate the data in a gentleman's manner and find out the h9) A token 14 is generated and sent to the output register 191.This node 101 is the link to which the node 101 is linked, and this 1-kun 14 (t It is supplied from the output 1/sister 23 to the iIN instruction decoder 25, where it is input to the operan F14d (
t') is solved if the command ζ is solved.
Timing pulse 211[]Il (supplied to the timing pulse generation circuit 21. This causes the timing pulse 4p
The raw circuit 21 outputs the first few baud link pulses from the output i'lifl child 211. child! 1, in the above middle b
Since the input stack 16 ζ of this node 10n is continuously supplied to the input stack 16, ζ, the C p U 18n of the notebook '10.1 is supplied to the input stack 16, . Stack data 4 - Process. In this case, even if the CPU 18 is performing various processing, the input stack 16 can output the token of the data to be transmitted at any time as long as the input stack 16 is in a stackable state, and the node 101 and the node ]0 old Time for a handshake? Furthermore, by supplying commands to the communication management device 11, a large number of data can be transmitted.3 Not only input and output data can be exchanged between two nodes, but also tasks can be exchanged and distributed between nodes. It is also possible to do this, and it is possible to organically combine the processors of each node.

Note that the input stack 16 of each node 10, to 10n.

~16n is each node 101~10nO> CPU
The number of stacked stages can be changed by nodes 181 to 18; ~10o If the device to bury your friend's anger is decided, input stack 161~
16.1 The number of stages may be set at the beginning. Also, node 10. , I: When reading data continuously,
The timing pulse generation circuit 21 outputs I from the output terminal 21□.
- Do not output polling pulses for the number of times 14, but output 4z polling pulses as "1" from the output terminal 14 child 211 during the period that is necessary for this continuous 3.1 seepage]. , the read pulse output from the timing pulse generation circuit 21 during this "Ji" period (-1.-kun 14 may be extracted by one or nine times from the hood 10.
1-Execution (limited to 11pm, looks like f).

As mentioned above, a data transmission system that achieves +i0 brightness requires a multi-stage input stack in which a fixed number of transmission bits supplied to each stack are stacked in one stage, and each stage is processed independently. Specify a plurality of notes that can be entered, and any one of the plurality of nodes. It consists of a communication management device that transmits the transmission signal of the number of hits in parallel, and supplies the transmitted transmission signal in parallel to one distributed node. 1
・In order to connect and transmit data between multiple nodes by stacking on the input stack of 7 nodes indicated by one destination address, The take can be transmitted even if it is performing strange processing, and the transmission Ill and reception (
i (node husband of 1, !70) For the CPU to transfer the data (・this time for handshake is required ν
data transmission time is shortened, and l1lj(
,'(Management j % Btj(is 61' of the transmission signal to /l)
Since it is possible to change the number of times and the order in which each of the γ1 nodes is designated by the i command, a node that wishes to transmit a large amount of data can be sent ahead of other nodes f, f and the entire system This is to improve the efficiency of data input)) 3.

[Brief explanation of the drawing]

Figures 1 and 2 schematically show the forms of each side of a conventional transmission port [Figure 3 is a block system diagram of one implementation of the data transmission system according to the present invention]. 1. 4th
The figure is a non-schematic illustration of the form of the transfer number in the system shown in the third figure. 10 ~ ] 0 ・Kentai node, 11 ... 4-■
Management equipment, 1 n 12.13” No. 9 bus, 14 @... Token, 15 □ ~
1.5.20...Hicho device, 16□~16n-φ・Input custom r] Tsuku, 171~17n, 22 @...AND circuit, 1
8, ~18r4...Ko-Shoji-, r-equipment+iZ, (CP
U, ), 191-19n...output resistor, 23・Φ
・I/O Resisk, 24...Tekota 25 se
e-instruction - Coater 1 Figure 2 Figure 1

Claims (2)

[Claims] (1) A 44-sentence node that can fix a multi-stage input stack in which transmission signals of a certain number of bits supplied to each node are stacked in one stage, and that can eliminate independent processing for each node, and 3 multi-stage nodes. Finger at any of the pain nodes +
From the nuclear node to at least the destination node 5: send the transmission signal of the number of hits in parallel to the specified destination A1-1/S and the number of hits specified by the Stake or Rei. The transmission signal is provided in parallel to the plurality of node bridges. 1- A take-up i% system that specifically represents data transmission by connecting multiple nodes by stacking them on a human-powered stack. (2) For the 4-track credit confirmation device, the destination address corresponds.]
The take transmission system according to claim 1, characterized in that the number of times each of the plurality of nodes is specified and the IFi order can be changed by the command ζ of the transmission signal instructing the IO communication. .