JPS5943563A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS5943563A JPS5943563A JP15259082A JP15259082A JPS5943563A JP S5943563 A JPS5943563 A JP S5943563A JP 15259082 A JP15259082 A JP 15259082A JP 15259082 A JP15259082 A JP 15259082A JP S5943563 A JPS5943563 A JP S5943563A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit
- circuits
- diodes
- diffusion region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 2
- 241001024304 Mino Species 0.000 description 1
- 241000270708 Testudinidae Species 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 この発明は、半導体集積回路装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device.
Ｐ形半導体基板を用いた一般のバイポーラ集積回路では
、各素子間を分離絶縁するための分離拡散領域を、常に
回路内の最低電位に保つ必要がある。しかし、いずれが
低いか電位の不確定な複数の負電源（例えば電圧が常時
変化する複数の負ｃｌ。In a general bipolar integrated circuit using a P-type semiconductor substrate, it is necessary to always maintain an isolation diffusion region for isolating and insulating each element at the lowest potential in the circuit. However, there are multiple negative power supplies whose potential is uncertain as to which one is lower (for example, multiple negative CL whose voltage constantly changes).
源）によって動作する回路を、一体に４１４積回路化し
た場合、その分離拡散領域を常に回路内の最低電位（こ
保つことが困難となり、でのため、複数の回路を別個の
千ノブで構成しなければならないなどの不便があった。When a circuit operated by a power source is integrated into a 414-product circuit, it becomes difficult to maintain the isolation diffusion region at the lowest potential within the circuit. There were inconveniences such as having to do so.
本願発明は、従来のＰ形基板を用いるバイポーラ集積回
路のかかる欠点を解消すべくなされたもので、各回路の
電源端子及び分離拡散領域と、負電源との間にそれぞれ
タイオー ドを挿入接続し７て、分離拡散領域を常に最
低電位に保持させ、複数回路を四−千ノブ内に形成でき
るようイこした半導体集積回路装置を提供することを目
的とするものである。The present invention was made in order to eliminate such drawbacks of the conventional bipolar integrated circuit using a P-type substrate, and a diode is inserted and connected between the power supply terminal and isolation diffusion region of each circuit and the negative power supply. Another object of the present invention is to provide a semiconductor integrated circuit device in which a separation diffusion region is always maintained at the lowest potential, and a plurality of circuits can be formed within a four-thousand knob.
ｂノ、下実施例に基−〕き本願発明の詳細な説明する。B. The present invention will be described in detail based on the following examples.
第１図は、本願発明に係る半導体集績回路装置道の実施
例の回路（１部成図であ６゜図におい（“］、２．３．
４はそれぞれタイＡ−ド−？？、タイＡ −１−” １
は、回路５の負′亀源端子Ｘと第１の負電源７（１ｄ圧
は−ｖＥＥ１）との間に接続され、ダイオ−ド２は回路
６の頁７戊諒端丁）古＾３２の負１ｉ曽８（１１璽１屓
ま一■＋：ｐ；２）との出口こ接かｆｉ：ＪメＡＬ、」
］／、二、り・イ」 １・３．４はそれぞれ回路５、（
５の分離域１１１．領域に後続される端、、ｆ Ｚと、
ＡＩ’＋ ］ Ｍ ’ｒｕ、 ｉｉ’；ｊ ７又は、＋
４．２ 工ｔ ’４１．Ｑ ８との間に接続され−Ｃい
る。第１１ネ１において、破線で囲まれた部分が同一−
−ｆｌ、プ内に集積回路化されて形成されて１、タリ、
一方タイオード１〜・４は外付け（トｖ成にｊ了ってい
る。FIG. 1 is a partial circuit diagram of an embodiment of a semiconductor integrated circuit device according to the present invention.
4 are each tied A-do? ? , tie A -1-" 1
is connected between the negative terminal X of the circuit 5 and the first negative power supply 7 (1d voltage is -vEE1), and the diode 2 is connected between the negative terminal The exit of the negative 1i so 8 (11㎽1屓ま一■+:p;2) is connected to fi:JmeAL,''
] /, 2, ri・i'' 1, 3.4 are respectively circuit 5, (
5 separation zone 111. The edges followed by the region, , f Z and
AI'+] M'ru, ii';j 7 or +
4.2 Engineering '41. It is connected between Q8 and -C. In the 11th page 1, the parts surrounded by broken lines are the same -
-fl, formed as an integrated circuit in the 1, tari,
On the other hand, diodes 1 to 4 are externally connected.
この構成ｊｒｌおいご、ｊ） ’Ｆｉｌ＃拡散領域拡散
領域端子房Ａン、グ・イオ−ド４が」ノ占なり、端子Ｚ
のｉ４位Ｖｚは、タイイー ドの順方向電圧をＶＤとす
る古、ＶＺ ＝ −Ｖ ＥＥＩ ＋ ＶＤ
乏なる。一方、ＩＶＥＥＩ ｌ （ｌ ＶＥＥ２１の場
合、タイＡ−Ｆ ３が４−）、ダイ］−ド４かＡノ（Ｊ
二なり、ψｊ４子Ｚの′ｆＫ位Ｖｙ、は、
’ＩＩＺ ＝＝ −ＶＥＬｚ ４− ＶＤきなる。夕・
イオ−ド１．２は回路５．６への’ｔＭ、 ＆：′屯ｊ
１１を、夕・イオードのｒ犀圧降ドＶｌ）分たり醒Ｍを
Ｌげるためのものであり、したがり′Ｃ１回路５の端子
Ｘにおける電位Ｖｘおよび、回路６の端子Ｙにおける電
位Ｖｙは、
ＶＸ−：−−−■ＥＥＩ−ＩＶＤ
Ｖｙ ＝ −ＶＥＥ２ ＋ＶＤ
となる。This configuration jrl, j) 'Fil #diffusion area diffusion area terminal tuft A, G iode 4 is 'no' fortune, terminal Z
Vz at the i4th position is VZ = -VEEI + VD, where VD is the forward voltage of the tie. On the other hand, IVEEI l (in the case of l VEE21, tie A-F 3 is 4-), die]-do 4 or A-(J
2, 'fK position Vy of ψj4 child Z becomes 'IIZ == -VELz 4- VD. evening·
Iode 1.2 is 'tM, &:'tonj to circuit 5.6
11, to reduce the voltage drop Vl) of the diode, so that the potential Vx at the terminal X of the C1 circuit 5 and the potential Vy at the terminal Y of the circuit 6 VX-:---EEI-IVD Vy = -VEE2 +VD.
（−こて、ダイオード１．２．３．４のｊ喧方向・亀Ｌ
Ｅｆ、’；： ；Ｈ，ソｔＬ Ｖｎ＋ 、 ＶＤ２、Ｖ
１１３、ＶＤ４とし、ＶＤＩ ＞Ｖｎｓ、ＶＤ２ ：＞
ＶＤ４１ｃ Ｗｋ 定すると、ｌ Ｖｐ：ｇ＋ ））
ＩＶＥＥ２ ｌのとき、ＩＶＺＩ ＞ ＩＶＸＩ ＞
１Ｖ１ｔさなり、一方、
ＩＶＥＥＩ ｌ （ｌ ＶＦＪ：ｚ ｌのとき、ＩＶＺ
ｌ＞ １Ｖｙｌ ＞ＩＶＸＩとなり、分前拡散領域端子
Ｚの電位ＶＺは、常（こ回路５及び６の最低電位にクラ
ンプされることになる。(-trowel, diode 1.2.3.4 direction/tortoise L
Ef,';: ;H, sotL Vn+, VD2, V
113, VD4, VDI >Vns, VD2:>
When VD41c Wk is determined, l Vp:g+ ))
When IVEE2 l, IVZI > IVXI >
1V1t, on the other hand, when IVEEI l (l VFJ:z l, IVZ
l>1Vyl>IVXI, and the potential VZ of the front diffusion region terminal Z is always clamped to the lowest potential of the circuits 5 and 6.
第２図は、第１図（こ示し７だ実施例（こおいて、外付
は構成古し、たタイオードを、Ｐ形基板を用いたバ・イ
ボーラ集債回路吉同−チツブ内に組み込み形成した実施
例を示す。第２図において、１１はＰ形基板、１２はＹ
゛形分離拡故領域、１３はＮ形エピタキシャル層、１４
はＰ形ベース拡散領域、１５はＮエミッタ拡散領域、１
６はＰ形分離拡故領域］２に設けたＮ拡散領域である。Figure 2 shows Figure 1 (shown in Figure 7). An example formed is shown. In Fig. 2, 11 is a P type substrate, 12 is a Y type substrate.
13 is an N-type epitaxial layer, 14 is an N-type epitaxial layer;
is a P type base diffusion region, 15 is an N emitter diffusion region, 1
Reference numeral 6 denotes an N diffusion region provided in the P-type separation expansion region]2.
破線で図示したＡ部で、第Ｊ図イこお（・）る９イｉ−
１” ］に対応するダイ」−ドを形成しており、同じく
Ｂ部、（２部及びＤ部で、それぞれ第１図におけるクイ
オ＝−ド３．４．２に対応するダイオードを形成しＣ−
いる。また、］７、Ｉ８はハ心諒、Ｘ、Ｙは、同一基板
に形成された、第１図１こおける回路５．６１こ対応Ａ
る回路の負電源接続部への接続端である。In part A indicated by the broken line, go to Figure J.
A diode corresponding to the diode 3.4.2 in FIG. −
There is. In addition, ]7, I8 are C, X and Y are A corresponding to the circuit 5.61 in FIG. 1, which is formed on the same substrate.
This is the connection end to the negative power supply connection of the circuit.
なｔり、Ｎ拡散領域】６は、負’ｄ源吉分離拡散領域と
の間に接続されるタイオー ドの通力向＋ｌｉ圧を上げ
るために、Ｎ工こツタ拡赦碩域Ｊ５とは別の拡散工程を
用いで形成しでいるが、このダイオ−ドの逆方向耐圧が
小さくてもよい場合（こは、Ｎ拡散領域１６はＮエミッ
タ拡散領域１５．’ｚ回−拡散二Ｅ程で形成４−るこ吉
ができる。。In order to increase the current direction + li pressure of the diode connected between the negative 'd Genkichi separation and diffusion area] 6 is a Although the diode is formed using a diffusion process, if the reverse breakdown voltage of this diode may be small (in this case, the N diffusion region 16 is formed using the N emitter diffusion region 15. 4- I can do Rukokichi.
以上実施例に基づき詳細に説明したように、本願発明に
よれば、複数の回路の各員′［イ源端子及び分離拡散領
域端Ｐ吉、複数の負電源との間にそれぞれダイオードを
配置し７て、分離拡散領域を常１こ各回路の最低電位に
保持できるようにしたので、従来の如く複数の回路を別
個の千ノブで形成する必要はなく、同一チノブ内に形成
−イることができ、また、挿入接続されるターｆ Ｊ〜
［・を各回路を形成する同一ヂノブ内に一体に組み込
み形成し、：１ノバクトな′４Ｌ導体）も積回路装置を
構成Ａることができるなどの効果が得られる。、As described above in detail based on the embodiments, according to the present invention, a diode is disposed between each member of the plurality of circuits, the source terminal, the end of the isolation diffusion region, and the plurality of negative power supplies. 7) Since the separation diffusion region can always be held at the lowest potential of each circuit, there is no need to form multiple circuits in separate circuits as in the past, but they can be formed in the same circuit. can be inserted and connected to the target f J~
Effects such as the ability to form an integrated circuit device by integrally incorporating and forming the . ,
第１図は、本願発明に係る半導体集積回路装置の一実施
例の回路構成図、第２図は、本願発明の他の実施例の一
部省略構成図である。
図面中、１，２．３．４はダイオード、５．６は回路、
７．８は負電源、Ｘ、Ｙは回路５．６の買電σ・ハ噛子
、Ｚは回路５．６の分＋Ｉｉｌ拡散領域端子、】１はＰ
形基板、１２ＩＪＰ形分瑚１拡敵領域、１３ｉ１Ｎ、Ｉ
ヒコ−ビタキジＶ几層、１・１はＰ形ヘース拡散領域、
１５＋
はＮＬミノ力拡散頃域、１６はＮ拡散領域、１７，１８
は負電源を示す。
勃訂出入１１１人 オリンパス光学工業株式会社代理
人弁理士 最 上 健 治′ ゛＼FIG. 1 is a circuit configuration diagram of one embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a partially omitted configuration diagram of another embodiment of the present invention. In the drawing, 1, 2, 3, 4 are diodes, 5.6 is a circuit,
7.8 is the negative power supply, X and Y are the power purchase σ and ha of circuit 5.6, Z is the terminal of circuit 5.6 + Iil diffusion region, ]1 is P
shape board, 12IJP shape bungo 1 enemy expansion area, 13i1N, I
Hiko-Bitakiji V-layer, 1.1 is P-type Heath diffusion region,
15+ is the NL mino force diffusion region, 16 is the N diffusion region, 17, 18
indicates a negative power supply. 111 people entering and leaving Olympus Optical Industry Co., Ltd. Patent attorney Kenji Mogami'゛＼
Claims (3)
られる複数の回路を有するＰ形半導体基板を用いたバイ
ポーラ集積回路において、前記各回路の各電源端子と前
記各電源さの間、並ひに前記各回路の分離拡散領域と前
記各′屯諒との間にタイオードを挿入接続し、前記分＾
ＩＬ拡散領域を常に最低電位に保持せしめるように構成
したこ吉を特徴とする半導体−央績回路装置。(1) In a bipolar integrated circuit using a P-type semiconductor substrate having a plurality of circuits operated by a plurality of negative I4 sources of uncertain potential, between each power terminal of each circuit and each power source, At the same time, a diode is inserted and connected between the isolation diffusion region of each of the circuits and each of the above-mentioned terminals.
A semiconductor-integrated circuit device characterized by a semiconductor device configured to always maintain an IL diffusion region at the lowest potential.
に対し、九個は構成古されていることを特徴とする特許
請求のわ、間第ｊ、ＩＪ′ｉ記載の半導体集積回路装置
。(2) The semiconductor integrated circuit device according to claim 1, wherein nine of the diodes are older than those of the integrated circuit.
路内イこ一体に糺み込み構成さ、ｌｉていることを特徴
とする特許請求の範囲第１項記載の半導体集積回路装置
。(3) The semiconductor integrated circuit device according to claim 1, wherein the diode is integrated into the bipolar integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15259082A JPS5943563A (en) | 1982-09-03 | 1982-09-03 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15259082A JPS5943563A (en) | 1982-09-03 | 1982-09-03 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5943563A true JPS5943563A (en) | 1984-03-10 |
Family
ID=15543767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15259082A Pending JPS5943563A (en) | 1982-09-03 | 1982-09-03 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5943563A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0255125A2 (en) * | 1986-07-30 | 1988-02-03 | Nec Corporation | Integrated circuit having two circuit blocks therein independently energized through different power supply terminals |
| JPS63151066A (en) * | 1986-12-16 | 1988-06-23 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| EP0464452A2 (en) * | 1990-06-21 | 1992-01-08 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
-
1982
- 1982-09-03 JP JP15259082A patent/JPS5943563A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0255125A2 (en) * | 1986-07-30 | 1988-02-03 | Nec Corporation | Integrated circuit having two circuit blocks therein independently energized through different power supply terminals |
| JPS63151066A (en) * | 1986-12-16 | 1988-06-23 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| EP0464452A2 (en) * | 1990-06-21 | 1992-01-08 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit |
| US5231300A (en) * | 1990-06-21 | 1993-07-27 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit having a digital circuit |
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