JPS5942830B2 - Test pattern generator - Google Patents
Test pattern generatorInfo
- Publication number
- JPS5942830B2 JPS5942830B2 JP52158891A JP15889177A JPS5942830B2 JP S5942830 B2 JPS5942830 B2 JP S5942830B2 JP 52158891 A JP52158891 A JP 52158891A JP 15889177 A JP15889177 A JP 15889177A JP S5942830 B2 JPS5942830 B2 JP S5942830B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- pattern generator
- test pattern
- output
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
【発明の詳細な説明】
この発明は例えばメモリ等の集積回路素子を試験する場
合に用いられる試験パターン発生装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test pattern generator used for testing integrated circuit elements such as memories.
集積回路素子の試験方法として数種のデータを時分割的
に切換ながら与えて動作させなければならない素子があ
る。As a test method for integrated circuit devices, some devices must be operated by applying several types of data while being switched in a time-division manner.
このような場合例えば第１図に示すようにパターン発生
器１から複数のデータａ０、ａ２、ａ３・・・・・・
ａｍを出力させ、この出力データａｌ、ａ２、ａ３・・
・・・・ ａｍを切換回路２にて順次切換、出力端子３
に出力データａｌ、ａ２、ａ３・・・・・・ａｍを時分
割的に取り出すことが行なわれる。然し乍らこの構成に
よれば切換回路２から得られる時分割信号はデータａｌ
、ａ２、ａ３゜゜゜’’゜ａｍ、ａｌａ２ａ３・・・・
・・ ａｍの順になり、その順序を変更することができ
ない。従つて自由な組合せのパターンデータを得ること
ができない欠点がある。この発明の目的は自由な組合せ
のパターンデータを得ることができる試験パターン発生
装置を提供するにある。In such a case, for example, as shown in FIG. 1, a plurality of data a0, a2, a3...
am is output, and this output data al, a2, a3...
....am is sequentially switched by switching circuit 2, output terminal 3
The output data al, a2, a3, . . . am are extracted in a time-division manner. However, according to this configuration, the time division signal obtained from the switching circuit 2 is
, a2, a3゜゜゜''゜am, ala2a3...
...The order is am, and the order cannot be changed. Therefore, there is a drawback that pattern data of a free combination cannot be obtained. An object of the present invention is to provide a test pattern generating device that can obtain pattern data in any combination.
この発明では切換回路の前段に複数の選択回路を設け、
この複数の選択回路において任意のデータを選択して出
力させこの選択された信号を切換回路にて順次時分割的
に切換るようにしたものである。In this invention, a plurality of selection circuits are provided before the switching circuit,
The plurality of selection circuits select and output arbitrary data, and the switching circuit sequentially switches the selected signals in a time-division manner.
第２図はこの発明の一実施例を示す。FIG. 2 shows an embodiment of the invention.
図中１はパターン発生器を示す。このパターン発生器１
からは例えば出力データａｌ、ａ２、ａ３・・・・・・
一の如くｍ個の出力データが出力されているものとす
る。これらの出力データａ１〜ａｍはｎ個の選択回路４
ａ、４ｂ、・・・・・・ ４ｎにそれぞれ供給される。
ここでｍ＞ｎに選定され、各選択回路４ａ〜４ｎより適
当に組合された選択データＣ１、Ｃ２・・・・・・Ｃｎ
を得る。この選択データＣ１〜Ｃｎの組合せは選択回路
４ａ〜４ｎに供給される選択信号ｂｌ、ｂ２、ｂ３、、
、、、、ｂｎによつて任意に切換ることができる。各選
択回路４ａ〜４ｎにて選択されたｎ個のデータｃ１〜ｃ
ｎは切換回路２に供給され、この切換回路２にてデータ
Ｃ１〜Ｃｎは外部からのリアルタイム切換信号５により
、逐次時分割的に出力端子３に出力される。従つてこの
発明によれは各選択回路４ａ〜４ｎにおいて選択する信
号を適宜選択することにより時分割的に出力されるパタ
ーンデータの配列の組合せを変化させることがでさる。In the figure, 1 indicates a pattern generator. This pattern generator 1
For example, output data al, a2, a3...
It is assumed that m pieces of output data such as 1 are output. These output data a1 to am are sent to n selection circuits 4.
a, 4b, . . . 4n, respectively.
Here, selection data C1, C2...Cn selected such that m>n is selected and appropriately combined from each selection circuit 4a to 4n.
get. The combination of selection data C1-Cn is the selection signal bl, b2, b3, . . . supplied to the selection circuits 4a-4n.
, , , bn can be arbitrarily switched. n pieces of data c1 to c selected by each selection circuit 4a to 4n
n is supplied to a switching circuit 2, and in this switching circuit 2, data C1 to Cn are sequentially and time-divisionally outputted to an output terminal 3 in response to an external real-time switching signal 5. Therefore, according to the present invention, by appropriately selecting the signals to be selected in each of the selection circuits 4a to 4n, it is possible to change the arrangement combination of pattern data output in a time-divisional manner.
また選択する信号をリアルタイムに切換ることにより時
分割的に出力されるパターンデータの配列をリアルタイ
ムで切換ることもでき種々の集積回路素子を試験する場
合に適用して好適である。Furthermore, by switching the selected signal in real time, the arrangement of pattern data output in a time-divisional manner can be switched in real time, which is suitable for application when testing various integrated circuit elements.
第１図は従来の試験パターン発生装置を説明するための
系統図、第２図はこの発明の一実施例を示す系統図であ
る。
１■パターン発生器、２：切換回路、４ａ〜４ｎ：選択
回路。FIG. 1 is a system diagram for explaining a conventional test pattern generator, and FIG. 2 is a system diagram showing an embodiment of the present invention. 1 ■ Pattern generator, 2: switching circuit, 4a to 4n: selection circuit.
Claims (1)
ーン発生器から出力されるｍ個のデータから任意のデー
タを選択するｎ個の選択回路と、選択されたｎ個のデー
タを時分割的に取り出す切換回路とを具備して成る試験
パターン発生装置。1. A pattern generator that generates m pieces of data, n selection circuits that select arbitrary data from the m pieces of data output from the pattern generator, and time-divisional processing of the selected n pieces of data. A test pattern generator comprising: a switching circuit for extracting a test pattern;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52158891A JPS5942830B2 (en) | 1977-12-29 | 1977-12-29 | Test pattern generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52158891A JPS5942830B2 (en) | 1977-12-29 | 1977-12-29 | Test pattern generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5492066A JPS5492066A (en) | 1979-07-20 |
| JPS5942830B2 true JPS5942830B2 (en) | 1984-10-17 |
Family
ID=15681630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52158891A Expired JPS5942830B2 (en) | 1977-12-29 | 1977-12-29 | Test pattern generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5942830B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5972531A (en) * | 1982-10-20 | 1984-04-24 | Fanuc Ltd | Data input/output device |
-
1977
- 1977-12-29 JP JP52158891A patent/JPS5942830B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5492066A (en) | 1979-07-20 |
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